Abstract: A Not and Flash (Nandflash) controller and a data transmission method with the Nandflash controller are provided. The Nandflash controller includes a parameter configuration device, configured to receive an operation command from outside, wherein the operation command indicates a current transmission type, number of times needed for transmitting data, size of which is same as that of a buffer in the Nandflash, and command parameters used by each execution; a transmission controlling device, configured to transmit data of a precoded size to/from the Nandflash during each data transmission according to the current transmission type and the command parameters used by this execution the number of times indicated by the operation command. The controller and method advantageously avoid configuring a command for the next operation each time the data of the precoded size is transmitted, save time and clock resources, and greatly improves transmission efficiency.

Abstract: A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block.

Abstract: Remote memory can be used for a number idle pages located on a virtual machine. A number of idle pages can be sent to the remote memory according to a placement policy, where the placement policy can include a number of weighting factors. A hypervisor on a computing device can record a local size and a remote page fault frequency of the number of virtual machines. The hypervisor can scan local memory to determine the number of idle pages and a number of idle virtual machines. The number of idle pages, including a page map and a remote address destination for each idle page, can be sent to the remote memory by the hypervisor. The number of virtual machines can be analyzed to determine a per-virtual machine local memory allocation.

Abstract: Provided are a method, computer program product and system for determining an end of valid log in a log of write records. Records are written to a log in a storage device in a sequential order, wherein the records include a next pointer addressing a next record in a write order and a far ahead pointer addressing a far ahead record in the write order following the record. The far ahead pointer and the next pointer in a plurality of records are used to determine an end of valid log from which to start writing further records.

Abstract: A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block. J:\SAM\1309\subspecredline.

Abstract: An input/output control method and apparatus optimized for a flash memory, which can improve the performance of the flash memory. The input/output control method optimized for a flash memory includes determining whether a random write operation of data occurs in a flash memory, and successively writing randomly input data in a predetermined surplus region of the flash memory if it is judged that the random write operation occurs.

Abstract: A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n (n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access.

Abstract: Provided are a method, computer program product and system for determining an end of valid log in a log of write records. Records are written to a log in a storage device in a sequential order, wherein the records include a next pointer addressing a next record in a write order and a far ahead pointer addressing a far ahead record in the write order following the record. The far ahead pointer and the next pointer in a plurality of records are used to determine an end of valid log from which to start writing further records.

Abstract: A video storage system includes a storage area network and at least one local cache storage unit. Both the storage mechanism and the local cache storage unit store at least some content in common. In response to a react request, a read director determines which of the storage mechanism and local cache storage unit contains the requested content. Upon determining that the requested content resides on the local cache storage unit, the read director directs the content request to the local cache storage unit, thereby reducing the demand on the storage mechanism. If the content does not reside on the local cache storage unit, read director directs the request to the storage mechanism, but if the content is unavailable, the content request will be filled with filler data from a filler data source.

Abstract: A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.

Abstract: Provided are techniques for introducing a delay in responding to host write requests. A percentage of fullness of a write cache is determined. Based on the determined percentage of fullness of the write cache (f), a low cache threshold (L), alpha (?), and k, an amount of delay to introduce into responding to a host write request is determined. Techniques wait the amount of the delay before responding to the host write request although the host write request processing has completed.

Abstract: To include an address generating unit that generates a series of access destination addresses at a time of performing a burst access to the external memory, starting from an initial address to be accessed, so that number of inverted bits along with the address change becomes smallest, and a data processing unit that reads data held in a data holding unit and writes the data in an external memory in order of the access destination addresses, or reads data from the external memory in order of the access destination addresses and writes the data in the data holding unit.

Abstract: A cache memory includes a write-back determination unit and a burst length determination unit. The write-back determination unit determines whether a block is a write-back block based on an n-bit dirty value of the block. The burst length determination unit determines a burst length of write-back data included in the write-back block based on the n-bit dirty value and an minimum burst length, when the block is the write-back block.