With Pre-fetch (epo) Patents (Class 711/E12.057)
  • Patent number: 11119776
    Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: September 14, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Joseph Raymond Michael Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad, David M. Thompson
  • Patent number: 10719321
    Abstract: Technology related to prefetching instruction blocks is disclosed. In one example of the disclosed technology, a processor comprises a block-based processor core for executing a program comprising a plurality of instruction blocks. The block-based processor core can include prefetch logic and a local buffer. The prefetch logic can be configured to receive a reference to a predicted instruction block and to determine a mapping of the predicted instruction block to one or more lines. The local buffer can be configured to selectively store portions of the predicted instruction block and to provide the stored portions of the predicted instruction block when control of the program passes along a predicted execution path to the predicted instruction block.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 21, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Douglas C. Burger
  • Patent number: 10613869
    Abstract: An apparatus and method of operating an apparatus are provided. The apparatus comprises execution circuitry to perform data processing operations specified by instructions and instruction retrieval circuitry to retrieve the instructions from memory, wherein the instructions comprise branch instructions. The instruction retrieval circuitry comprises branch target storage to store target instruction addresses for the branch instructions and branch target prefetch circuitry to prepopulate the branch target storage with predicted target instruction addresses for the branch instructions. An improved hit rate in the branch target storage may thereby be supported.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 7, 2020
    Assignee: ARM Limited
    Inventors: Peter Richard Greenhalgh, Frederic Claude Marie Piry, Jose Gonzalez-Gonzalez
  • Patent number: 9697128
    Abstract: Embodiments relate to a prefetch threshold for cache restoration. An aspect includes determining, based on a task switch from an outgoing task to a current task in a processor, a prefetch threshold for a next task, the prefetch threshold corresponding to an expected runtime of the current task and an amount of time required to prefetch data for the next task. Another aspect includes starting prefetching for the next task while the current task is executing based on the prefetch threshold.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: July 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold W. Cain, III, David M. Daly, Brian R. Prasky, Vijayalakshmi Srinivasan
  • Patent number: 9043579
    Abstract: A prefetch optimizer tool for an information handling system (IHS) may improve effective memory access time by controlling both hardware prefetch operations and software prefetch operations. The prefetch optimizer tool selectively disables prefetch instructions in an instruction sequence of interest within an application. The tool measures execution times of the instruction sequence of interest when different prefetch instructions are disabled. The tool may hold hardware prefetch depth constant while cycling through disabling different prefetch instructions and taking corresponding execution time measurements. Alternatively, for each disabled prefetch instruction in the instruction sequence of interest, the tool may cycle through different hardware prefetch depths and take corresponding execution time measurements at each hardware prefetch depth.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventor: Randall Ray Heisch
  • Patent number: 9037810
    Abstract: Some of the embodiments of the present disclosure provide a method comprising receiving a data packet, and storing the received data packet in a memory; generating a descriptor for the data packet, the descriptor including information for fetching at least a portion of the data packet from the memory; and in advance of a processing core requesting the at least a portion of the data packet to execute a processing operation on the at least a portion of the data packet, fetching the at least a portion of the data packet to a cache based at least in part on information in the descriptor. Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: May 19, 2015
    Assignee: Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Adi Habusha, Alon Pais, Rabeeh Khoury
  • Patent number: 9026740
    Abstract: A computer-implemented method and system for improving efficiency in a delta compression process selects a data chunk to delta compress and generate matching criteria for the selected data chunk. The method and system searches for a similar data chunk using the matching criteria and loads a best match data chunk from the search. Locality data for the best match data chunk is determined and a plurality of data chunks with matching locality data are pre-fetched.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: May 5, 2015
    Assignee: EMC Corporation
    Inventors: Philip N. Shilane, Grant R. Wallace, Mark L. Huang
  • Patent number: 8924651
    Abstract: An apparatus and method is described herein for optimization to prefetch throttling, which potentially enhances performance, reduces power consumption, and maintains positive gain for workloads that benefit from prefetching. More specifically, the optimizations described herein allow for bandwidth congestion and prefetch accuracy to be taken into account as feedbacks for throttling at the source of prefetch generation. As a result, when there is low congestion, full prefetch generation is allowed, even if the prefetch is inaccurate, since there is available bandwidth. However, when congestion is high, the determination of throttling falls to prefetch accuracy. If accuracy is high—miss rate is low—then less throttling is needed, because the prefetches are being utilized—performance is being enhanced.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Perry P. Tang, Hemant G. Rotithor, Ryan L. Carlson, Nagi Aboulenein
  • Patent number: 8909866
    Abstract: A processor transfers prefetch requests from their targeted cache to another cache in a memory hierarchy based on a fullness of a miss address buffer (MAB) or based on confidence levels of the prefetch requests. Each cache in the memory hierarchy is assigned a number of slots at the MAB. In response to determining the fullness of the slots assigned to a cache is above a threshold when a prefetch request to the cache is received, the processor transfers the prefetch request to the next lower level cache in the memory hierarchy. In response, the data targeted by the access request is prefetched to the next lower level cache in the memory hierarchy, and is therefore available for subsequent provision to the cache. In addition, the processor can transfer a prefetch request to lower level caches based on a confidence level of a prefetch request.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: December 9, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Ravindra Nath Bhargava, Ramkumar Jayaseelan
  • Patent number: 8892822
    Abstract: The disclosed embodiments relate to a system that selectively drops a prefetch request at a cache. During operation, the system receives the prefetch request at the cache. Next, the system identifies a prefetch source for the prefetch request, and then uses accuracy information for the identified prefetch source to determine whether to drop the prefetch request. In some embodiments, the accuracy information includes accuracy information for different prefetch sources. In this case, determining whether to drop the prefetch request involves first identifying a prefetch source for the prefetch request, and then using accuracy information for the identified prefetch source to determine whether to drop the prefetch request.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: November 18, 2014
    Assignee: Oracle International Corporation
    Inventor: Yuan C. Chou
  • Patent number: 8880807
    Abstract: A data prefetcher in a microprocessor. The data prefetcher includes a plurality of period match counters associated with a corresponding plurality of different pattern periods. The data prefetcher also includes control logic that updates the plurality of period match counters in response to accesses to a memory block by the microprocessor, determines a clear pattern period based on the plurality of period match counters and prefetches into the microprocessor non-fetched cache lines within the memory block based on a pattern having the clear pattern period determined based on the plurality of period match counters.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: November 4, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Rodney E. Hooker, John Michael Greer
  • Patent number: 8880847
    Abstract: A prefetching system receives a memory read request having an associated address. In response to a determination that a most significant portion of the associated address is not present within slots of an array for storing the most significant portion of predicted addresses, a prefetch FIFO (First In-First Out) counter is modified to point to a next slot of the array and a new predicted address is generated in response to the received most significant portion of the associated address and is placed in the next slot of the array. The prefetch FIFO counter cycles through the slots of the array before wrapping around to a first slot of the array for storing the most significant portion of predicted addresses.
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Kai Chirca
  • Patent number: 8872677
    Abstract: A compression method applies a selection rule to input symbols and generates a reduced partial set of symbols. The partial set is checked against a dictionary-index for a match. A match identifies a range of matching symbols in a dictionary. The length of the matching range is iteratively increased by checking previous and next symbols in the input data and the dictionary until a matching range length meets a threshold limit or the length of the matching range cannot be increased further. Compressed data corresponding to the input symbols is provided where input symbols are copied over and symbols in a matched range of data are replaced with a representation of their corresponding start location and length in the dictionary.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Dialogic Networks (Israel) Ltd.
    Inventors: Oleg Litvak, Amir Ilan
  • Patent number: 8856453
    Abstract: A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jason N. Dale, Miles R. Dooley, Richard J. Eickemeyer, Bradly G. Frey, Yaoqing Gao, Francis P. O'Connell, Jeffrey A. Stuecheli
  • Patent number: 8856451
    Abstract: The present invention provides a method and apparatus for adapting aggressiveness of a pre-fetcher in a processor-based system. One embodiment includes modifying a rate for pre-fetching data from a memory into one or more caches by comparing a first address of a memory access request to addresses in an address window that includes one or more previously fetched addresses and one or more addresses to be fetched.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: October 7, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephen P. Thompson, Tarun Nakra
  • Patent number: 8819342
    Abstract: An instruction in an instruction cache line having a first portion that is cacheable, a second portion that is from a page that is non-cacheable, and crosses a cache line is prevented from executing from the instruction cache. An attribute associated with the non-cacheable second portion is tracked separately from the attributes of the rest of the instructions in the cache line. If the page crossing instruction is reached for execution, the page crossing instruction and instructions following are flushed and a non-cacheable request is made to memory for at least the second portion. Once the second portion is received, the whole page crossing instruction is reconstructed from the first portion saved in the previous fetch group. The page crossing instruction or portion thereof is returned with the proper attribute for a non-cached fetched instruction and the reconstructed instruction can be executed without being cached.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: August 26, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Leslie Mark DeBruyne, James Norris Dieffenderfer, Michael Scott Mcilvaine, Brian Michael Stempel
  • Patent number: 8812790
    Abstract: A controller is communicatively coupled with a storage medium and with a cache device and configured to interface with a processor or a memory of a computer system. The controller is further configured to receive a specified quantity of address references associated with a storage system; determine a spatial distribution of references to addresses of the storage system based at least in part on the received specified quantity of the address references, where to perform a determination of the spatial distribution, the controller is further configured to omit a random quantity of address references between previous determination of the spatial distribution and said determination of the spatial distribution; combine the determined spatial distribution with the previous determination of the spatial distribution into a spatial locality metric of the storage system; and output the spatial locality metric to use in caching data from the storage medium to the cache device.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 19, 2014
    Assignee: Marvell World Trade Ltd.
    Inventor: Arvind Pruthi
  • Patent number: 8806145
    Abstract: Methods and apparatuses are disclosed for improving speculation success in processors. In some embodiments, the method may include executing a plurality of threads of program code, the plurality of threads comprising a first speculative load request, setting an indicator bit corresponding to a cache line in response to the first speculative load request, and in the event that a second speculative load request from the plurality of threads refers to a first cache line with the indicator bit set, determining if a second cache line is available.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: August 12, 2014
    Assignee: Oracle America, Inc.
    Inventors: Zoran Radovic, Erik Martin Roland Karlsson
  • Patent number: 8775741
    Abstract: A storage control system includes a prefetch controller that identifies memory regions for prefetching according to temporal memory access patterns. The memory access patterns identify a number of sequential memory accesses within different time ranges and a highest number of memory accesses to the different memory regions within a predetermine time period.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: July 8, 2014
    Assignee: Violin Memory Inc.
    Inventor: Erik de la Iglesia
  • Patent number: 8775742
    Abstract: A system and method for caching file data is disclosed. In one embodiment, in a method for caching file data stored in a storage device, wherein the file data is used by an application running on a computing system having a processor, a file system residing in memory, and a storage controller, file data required by the application running on the processor is determined and file access data is generated. Then, physical file mapping information related to the file access data on the storage device is determined. The physical file mapping information includes logical block information, associated physical block information, and a next block hint needed for caching portions of the file data for each subsequent logical block. Further, read commands are generated from the storage controller to read-ahead file data stored in the storage device using the physical file mapping information.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: July 8, 2014
    Assignee: LSI Corporation
    Inventor: Venkata Kumar Duvvuru
  • Patent number: 8762649
    Abstract: A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintains a largest address and a smallest address of the accesses and counts of changes to the largest and smallest addresses and maintains a history of recently accessed cache lines implicated by the access addresses within the memory block. The prefetcher also determines a predominant access direction based on the counts and determines a predominant access pattern based on the history. The prefetcher also prefetches into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: June 24, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Rodney E. Hooker, John Michael Greer
  • Patent number: 8732405
    Abstract: A method of operating a predictive data cache includes receiving a request for telematics service from a telematics service requester, determining the subject matter of the request, querying a predictive data cache to determine if the predictive data cache includes a service response to the subject matter of the request and, if the predictive data cache includes the service response, then providing the service response to the requester and updating the predictive data cache using the subject matter of the request. The subject matter can include one or more of: an event description, an event period, or an event location based on the request.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: May 20, 2014
    Assignee: General Motors LLC
    Inventors: Kannan Ramamurthy, Navjot Sidhu
  • Publication number: 20140136794
    Abstract: Methods and systems for application controlled pre-fetch are described. The system receives pre-fetch information, over a network, at a first load balancer. The pre-fetch information is received from a first application server and includes a plurality of element identifiers that respectively identify a plurality of interface elements included in an interface. The system identifies a first element identifier from the plurality of element identifiers in the pre-fetch information. The first element identifier identifies a first interface element. The system retrieves the first interface element by communication of a request to a second application server. The request includes the first element identifier.
    Type: Application
    Filed: November 14, 2012
    Publication date: May 15, 2014
    Applicant: eBay Inc.
    Inventor: Srinivasan Raman
  • Publication number: 20140129780
    Abstract: Methods and systems for prefetching data for a processor are provided. A system is configured for and a method includes selecting one of a first prefetching control logic and a second prefetching control logic of the processor as a candidate feature, capturing the performance metric of the processor over an inactive sample period when the candidate feature is inactive, capturing a performance metric of the processor over an active sample period when the candidate feature is active, comparing the performance metric of the processor for the active and inactive sample periods, and setting a status of the candidate feature as enabled when the performance metric in the active period indicates improvement over the performance metric in the inactive period, and as disabled when the performance metric in the inactive period indicates improvement over the performance metric in the active period.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Sharad Dilip Bade, Alok Garg, John Kalamatianos, Paul Keltcher, Marius Evers, Chitresh Narasimhaiah
  • Publication number: 20140129775
    Abstract: Disclosed is a method of pre-fetching NFA instructions to an NFA cell array. The method and system fetch instructions for use in an L1 cache during NFA instruction execution. Successive instructions from a current active state are fetched and loaded in the L1 cache. Disclosed is a system comprising an external memory, a cache line fetcher, and an L1 cache where the L1 cache is accessible and searchable by an NFA cell array and where successive instructions from a current active state in the NFA are fetched from external memory in an atomic cache line manner into a plurality of banks in the L1 cache.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: LSI CORPORATION
    Inventor: Michael Ruehle
  • Publication number: 20140129772
    Abstract: A processor transfers prefetch requests from their targeted cache to another cache in a memory hierarchy based on a fullness of a miss address buffer (MAB) or based on confidence levels of the prefetch requests. Each cache in the memory hierarchy is assigned a number of slots at the MAB. In response to determining the fullness of the slots assigned to a cache is above a threshold when a prefetch request to the cache is received, the processor transfers the prefetch request to the next lower level cache in the memory hierarchy. In response, the data targeted by the access request is prefetched to the next lower level cache in the memory hierarchy, and is therefore available for subsequent provision to the cache. In addition, the processor can transfer a prefetch request to lower level caches based on a confidence level of a prefetch request.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Ravindra Nath Bhargava, Ramkumar Jayaseelan
  • Patent number: 8719510
    Abstract: A microprocessor includes a cache memory and a data prefetcher. The data prefetcher detects a pattern of memory accesses within a first memory block and prefetch into the cache memory cache lines from the first memory block based on the pattern. The data prefetcher also observes a new memory access request to a second memory block. The data prefetcher also determines that the first memory block is virtually adjacent to the second memory block and that the pattern, when continued from the first memory block to the second memory block, predicts an access to a cache line implicated by the new request within the second memory block. The data prefetcher also responsively prefetches into the cache memory cache lines from the second memory block based on the pattern.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: May 6, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Rodney E. Hooker, John Michael Greer
  • Publication number: 20140122807
    Abstract: Memory address translations are disclosed. An example memory controller includes an address translator to translate an intermediate memory address into a hardware memory address based on a function, the address translator to select the function based on at least a portion of the intermediate memory address, the intermediate memory address being identified by a processor. The example memory controller includes a cache to store the function in association with an address range of the intermediate memory sector, the intermediate memory address being within the intermediate memory sector. Further, the example memory controller includes a memory accesser to access a memory module at the hardware memory address.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: Hewlett-Packard Development Company, LP.
    Inventors: Jichuan Chang, Doe Hyun Yoon, Parthasarathy Ranganathan
  • Publication number: 20140115263
    Abstract: Disclosed is a method and apparatus for pre-fetching child states in an NFA cell array. A pre-fetch depth value is determined for each transition in an NFA graph. The pre-fetch depth value is accessed for transition from an active state in the NFA graph. The child states of the active state are pre-fetched to the depth of the pre-fetch depth value recursively. A loader loads the pre-fetched states into the NFA cell array.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: LSI CORPORATION
    Inventor: Michael Ruehle
  • Publication number: 20140108739
    Abstract: A method for weak stream software data and instruction prefetching using a hardware data prefetcher is disclosed. A method includes, determining if software includes software prefetch instructions, using a hardware data prefetcher, and, accessing the software prefetch instructions if the software includes software prefetch instructions. Using the hardware data prefetcher, weak stream software data and instruction prefetching operations are executed based on the software prefetch instructions, free of training operations.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: SOFT MACHINES, INC.
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
  • Publication number: 20140108740
    Abstract: A processing system monitors memory bandwidth available to transfer data from memory to a cache. In addition, the processing system monitors a prefetching accuracy for prefetched data. If the amount of available memory bandwidth is low and the prefetching accuracy is also low, prefetching can be throttled by reducing the amount of data prefetched. The prefetching can be throttled by changing the frequency of prefetching, prefetching depth, prefetching confidence levels, and the like.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 17, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Todd Rafacz, Marius Evers, Chitresh Narasimhaiah
  • Publication number: 20140108729
    Abstract: Systems and methods for load canceling in a processor that is connected to an external interconnect fabric are disclosed. As a part of a method for load canceling in a processor that is connected to an external bus, and responsive to a flush request and a corresponding cancellation of pending speculative loads from a load queue, a type of one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor, is converted from load to prefetch. Data corresponding to one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor is accessed and returned to cache as prefetch data. The prefetch data is retired in a cache location of the processor.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: SOFT MACHINES, INC.
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
  • Publication number: 20140101388
    Abstract: A method and apparatus for controlling the aggressiveness of a prefetcher based on thrash events is presented. An aggressiveness of a prefetcher for a cache is controlled based upon a number of thrashed cache lines that are replaced by a prefetched cache line and subsequently written back into the cache before the prefetched cache line has been accessed.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Donald W. McCauley
  • Publication number: 20140089598
    Abstract: An instruction in an instruction cache line having a first portion that is cacheable, a second portion that is from a page that is non-cacheable, and crosses a cache line is prevented from executing from the instruction cache. An attribute associated with the non-cacheable second portion is tracked separately from the attributes of the rest of the instructions in the cache line. If the page crossing instruction is reached for execution, the page crossing instruction and instructions following are flushed and a non-cacheable request is made to memory for at least the second portion. Once the second portion is received, the whole page crossing instruction is reconstructed from the first portion saved in the previous fetch group. The page crossing instruction or portion thereof is returned with the proper attribute for a non-cached fetched instruction and the reconstructed instruction can be executed without being cached.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Leslie Mark DeBruyne, James Norris Dieffenderfer, Michael Scott McIlvaine, Brian Michael Stempel
  • Patent number: 8683138
    Abstract: A prefetch data machine instruction having an M field performs a function on a cache line of data specifying an address of an operand. The operation comprises either prefetching a cache line of data from memory to a cache or reducing the access ownership of store and fetch or fetch only of the cache line in the cache or a combination thereof. The address of the operand is either based on a register value or the program counter value pointing to the prefetch data machine instruction.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dan F Greiner, Timothy J Slegel
  • Publication number: 20140082286
    Abstract: A method and apparatus for determining data to be prefetched based on previous cache miss history is disclosed. In one embodiment, a processor includes a first cache memory and a controller circuit. The controller circuit is configured to load data from a first address into the first cache memory responsive to a cache miss corresponding to the first address. The controller circuit is further configured to determine, responsive to a cache miss for the first address, if a previous cache miss occurred at a second address. Responsive to determining that the previous cache miss occurred at the second address, the controller circuit is configured to load data from a second address into the first cache.
    Type: Application
    Filed: September 18, 2012
    Publication date: March 20, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventor: Yuan C. Chou
  • Publication number: 20140082324
    Abstract: A method and storage device for using file system data to predict host device operations are disclosed. In one embodiment, a storage device is disclosed having a first memory storing data and file system metadata, a second memory, and a controller. In response to receiving a command from the host device to read a first address in the first memory, the controller reads data from the first address in the first memory and returns it to the host device. The controller predicts a second address in the first memory to be read by a subsequent read command from the host device, reads the data from the predicted second address, and stores it in the second memory.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventors: Reuven Elhamias, Boris Dolgunov
  • Publication number: 20140059299
    Abstract: The disclosed embodiments relate to a method for dynamically changing a prefetching configuration in a computer system, wherein the prefetching configuration specifies how to change an ahead distance that specifies how many references ahead to prefetch for each stream. During operation of the computer system, the method keeps track of one or more stream lengths, wherein a stream is a sequence of memory references with a constant stride. Next, the method dynamically changes the prefetching configuration for the computer system based on observed stream lengths in a most-recent window of time.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Suryanarayana Murthy Durbhakula, Yuan C. Chou
  • Publication number: 20140052927
    Abstract: The present invention provides a method and apparatus for using prefetch hints. One embodiment of the method includes bypassing, at a first prefetcher associated with a first cache, issuing requests to prefetch data from a number of memory addresses in a sequence of memory addresses determined by the first prefetcher. The number is indicated in a request received from a second prefetcher associated with a second cache. This embodiment of the method also includes issuing, from the first prefetcher, a request to prefetch data from a memory address subsequent to the bypassed memory addresses.
    Type: Application
    Filed: August 17, 2012
    Publication date: February 20, 2014
    Inventors: Donald W. McCauley, Stephen P. Thompson
  • Patent number: 8656111
    Abstract: A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintains a largest address and a smallest address of the accesses and counts of changes to the largest and smallest addresses and maintains a history of recently accessed cache lines implicated by the access addresses within the memory block. The prefetcher also determines a predominant access direction based on the counts and determines a predominant access pattern based on the history. The prefetcher also prefetches into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: February 18, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Rodney E. Hooker, John Michael Greer
  • Patent number: 8645631
    Abstract: A microprocessor includes a first-level cache memory, a second-level cache memory, and a data prefetcher that detects a predominant direction and pattern of recent memory accesses presented to the second-level cache memory and prefetches cache lines into the second-level cache memory based on the predominant direction and pattern. The data prefetcher also receives from the first-level cache memory an address of a memory access received by the first-level cache memory, wherein the address implicates a cache line. The data prefetcher also determines one or more cache lines indicated by the pattern beyond the implicated cache line in the predominant direction. The data prefetcher also causes the one or more cache lines to be prefetched into the first-level cache memory.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: February 4, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Rodney E. Hooker, John Michael Greer
  • Patent number: 8639886
    Abstract: A system and method to optimize runahead operation for a processor without use of a separate explicit runahead cache structure. Rather than simply dropping store instructions in a processor runahead mode, store instructions write their results in an existing processor store queue, although store instructions are not allowed to update processor caches and system memory. Use of the store queue during runahead mode to hold store instruction results allows more recent runahead load instructions to search retired store queue entries in the store queue for matching addresses to utilize data from the retired, but still searchable, store instructions. Retired store instructions could be either runahead store instructions retired, or retired store instructions that executed before entering runahead mode.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gordon Bell, Anil Krishna, Srinivasan Ramani
  • Patent number: 8639870
    Abstract: Systems and methods for retrieving data stored on a peripheral storage device such as a magnetic tape drive or disk drive include string searching using the peripheral storage device resources without transferring data to the requesting host computer and transferring only data blocks with matching data to the associated host computer to conserve host resources and data channel and/or network bandwidth.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 28, 2014
    Assignee: Oracle International Corporation
    Inventors: David G. Hostetter, Gregory S. Toles, Bradley Edwin Whitney
  • Publication number: 20140025892
    Abstract: Methods, apparatuses, and processors for reducing memory latency in the presence of barriers. When a barrier operation is executed, subsequent memory access operations are delayed until the barrier operation retires. While the memory access operation is delayed, the memory access operation is converted into a prefetch request and sent to the L2 cache. Then, data corresponding to the prefetch request is retrieved and stored in the L1 data cache. When the memory access operation wakes up, the data for the operation will already be stored in the L1 data cache, reducing the memory latency of the operation.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Inventor: Gerard R. Williams III
  • Publication number: 20140006718
    Abstract: A hardware data prefetcher includes a queue of indexed storage elements into which are queued strides associated with a stream of temporally adjacent load requests. Each stride is a difference between cache line offsets of memory addresses of respective adjacent load requests. Hardware logic calculates a current stride between a current load request and a newest previous load request. The hardware logic compares the current stride and a stride M in the queue and compares the newest of the queued strides with a queued stride M+1, which is older than and adjacent to stride M. When the comparisons match, the hardware logic prefetches a cache line whose offset is the sum of the offset of the current load request and a stride M?1. Stride M?1 is newer than and adjacent to stride M in the queue.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Meera Ramani-Augustin, John Michael Greer
  • Patent number: 8621157
    Abstract: An apparatus is disclosed for performing cache prefetching from non-uniform memories. The apparatus includes a processor configured to access multiple system memories with different respective performance characteristics. Each memory stores a respective subset of system memory data. The apparatus includes caching logic configured to determine a portion of the system memory to prefetch into the data cache. The caching logic determines the portion to prefetch based on one or more of the respective performance characteristics of the system memory that stores the portion of data.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: December 31, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Gabriel H. Loh
  • Publication number: 20130346704
    Abstract: Described is a technology by which a link to content is visibly augmented to convey information related to a cached status of the linked-to content. In one aspect, a cached versus not cached indication may be provided to convey such cache-related information to a user. Staleness of cached content also may be indicated. Also described is pre-fetching and/or updating cache content, which may be conveyed to the user by the conveyed cache-related status information.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Applicant: MICROSOFT CORPORATION
    Inventors: Douglas Christopher Burger, Anoop Gupta, Jie Liu
  • Publication number: 20130346703
    Abstract: The present invention provides a method and apparatus for throttling prefetch requests for a cache. One embodiment of the method includes selecting a sequence of relative addresses for prefetching data from a memory into lines of a cache in response to detecting a cache miss to a first address. The sequence of relative addresses is determined relative to the first address. This embodiment of the method also includes issuing a prefetch request for data from a memory address indicated by one of the sequence of relative addresses when at least one previous prefetch stream accessed prefetched data associated with this one of the sequence of relative addresses.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 26, 2013
    Inventors: Donald W. McCauley, Stephen P. Thompson
  • Publication number: 20130339625
    Abstract: According to exemplary embodiments, a computer program product, system, and method for prefetching in memory include determining a missed access request for a first line in a first cache level and accessing an entry in a prefetch table, wherein the entry corresponds to a memory block, wherein the entry includes segments of the memory block. Further, the embodiment includes determining a demand segment of the segments in the entry, the demand segment corresponding to a segment of the memory block that includes the first line, reading a first field in the demand segment to determine if a second line in the demand segment is spatially related with respect to accesses of the demand segment and reading a second field in the demand segment to determine if a second segment in the entry is temporally related to the demand segment.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: International Business Machines Corporation
    Inventors: Brian R. Prasky, Chung-Lung K. Shum
  • Publication number: 20130318307
    Abstract: An apparatus including a tag comparison logic and a fetch-ahead generation logic. The tag comparison logic may be configured to present a miss address in response to detecting a cache miss. The fetch-ahead generation logic may be configured to select between a plurality of predefined fetch ahead policies in response to a memory access request and generate one or more fetch addresses based upon the miss address and a selected fetch ahead policy.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Inventors: Alexander Rabinovitch, Leonid Dubrovin, Vladimir Kopilevitch