For Peripheral Accesses To Main Memory, E.g., Dma, Etc. (epo) Patents (Class 711/E12.067)
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Patent number: 11949740Abstract: The present disclosure provides devices and methods relating to remote direct memory access (RDMA). In one implementation, a target device of the RDMA operation is configured to receive a packet including a first destination address and a destination key, obtain one or more offset values, and obtain a second destination address based on the first destination address, the destination key, and the one or more offset values. Further, the target device is configured to initiate the RDMA operation on a memory based on the second destination address.Type: GrantFiled: November 8, 2022Date of Patent: April 2, 2024Assignee: Huawei Technologies Co., Ltd.Inventors: Alex Margolin, Ben-Shahar Belkar, Ronen Hyatt, Danny Volkind, Lior Khermosh, Tal Mizrahi, Guy Shattah
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Patent number: 11714780Abstract: The technology disclosed partitions a dataflow graph of a high-level program into memory allocations and execution fragments. The memory allocations represent creation of logical memory spaces in on-processor and/or off-processor memories for data required to implement the dataflow graph. The execution fragments represent operations on the data. The technology disclosed designates the memory allocations to virtual memory units and the execution fragments to virtual compute units. The technology disclosed partitions the execution fragments into memory fragments and compute fragments, and assigns the memory fragments to the virtual memory units and the compute fragments to the virtual compute units. The technology disclosed then allocates the virtual memory units to physical memory units and the virtual compute units to physical compute units.Type: GrantFiled: May 20, 2021Date of Patent: August 1, 2023Assignee: SambaNova Systems, Inc.Inventors: David Alan Koeplinger, Raghu Prabhakar, Sumti Jairath
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Patent number: 11474720Abstract: Disclosed is a heap memory manager that manages an entry and a removal of data from a single allocated block of memory. The heap memory manager may receive a set of nodes from a tree-based representation of a point cloud or another image, may allocate a single block of memory for processing and/or rendering the set of nodes, may assign each node of the set of nodes to an exclusive range of addresses within the single block of memory, and may upload data of each of the set of nodes to the single block of memory in the exclusive range of addresses assigned to each node. A controller may then invoke a compute kernel with one or more compute kernel instances processing an address range that is different than the exclusive range of addresses assigned to each node of the set of nodes.Type: GrantFiled: April 4, 2022Date of Patent: October 18, 2022Assignee: Illuscio, Inc.Inventors: Daniel Buhrig, A Young Ryu
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Patent number: 8949522Abstract: Systems, apparatusses, and methods are disclosed for improving performance of a stride-based prefetcher on an out-of-order central processing unit (CPU). The present disclosure teaches a processor system that employs out-of-order stride prefetch units. The out-of-order stride prefetch units are utilized for issuing prefetches for out-of-order stride access patterns. In one or more embodiments, the out-of-order stride prefetch units examine the offsets between past virtual address (VA) accesses and the directions of the past VA accesses in order to generate an estimate of the underlying VA access stride of the executed program code (PC). In at least one embodiment, the out-of-order stride prefetch units use the estimate of the VA access stride in order to generate a prediction of future VA accesses. In some embodiments, after the out-of-order stride prefetch units have generated the prediction of future VA accesses, the out-of-order stride prefetch units prefetch the predicted future VA accesses.Type: GrantFiled: June 21, 2011Date of Patent: February 3, 2015Assignee: Netlogic Microsystems, Inc.Inventors: Gaurav Garg, David T. Hass
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Patent number: 8812770Abstract: Methods and devices are provided for adapting an I/O pattern, with respect to a processing device using a non-volatile block storage device based on feedback from the non-volatile block storage device. The feedback may include information indicating a status of the non-volatile block storage device. In response to receiving the feedback, a storage subsystem, included in an operating system executing on processing device, may change a behavior with respect to the non-volatile block storage device in order to avoid, or reduce, a negative impact to the non-volatile block storage device or to enhance an aspect of the non-volatile block storage device. The feedback may include performance information and/or operating environmental information of the non-volatile block storage device. When the non-volatile block storage device is not capable of providing the feedback, the processing device may request information about the non-volatile block storage device from a database service.Type: GrantFiled: July 13, 2009Date of Patent: August 19, 2014Assignee: Microsoft CorporationInventors: Vladimir Sadovsky, Nathan Steven Obr, James C. Bovee, Robin A. Alexander
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Patent number: 8798085Abstract: Techniques are described herein that can be used to process inbound network protocol units. In some implementations, the techniques may process inbound DDP segments. In some implementations, a steering tag of an inbound network protocol unit may be used to access a context accessible to a network component. In some implementations, the context may include an array useful to determine whether all segments in a group have been received by the network component. In some implementations, the segments may be stored in a first buffer and transferred to a second buffer after all segments in a group have been received.Type: GrantFiled: June 20, 2006Date of Patent: August 5, 2014Assignee: Intel CorporationInventor: Mark W. Wunderlich
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Patent number: 8788609Abstract: An automation device comprising a first functional unit, a second functional unit, a first network connection for connection to a first data network and a bus master unit for connecting a peripheral component. The first functional unit includes a first interface unit that is assigned a first network address, and the second functional unit includes a second interface unit that is assigned a second network address. A partitioning device can be used to logically partition an address space of the peripheral component, and a first address space can be directly assigned, as a partitioned part of the address space, to a superordinate computation unit that can be connected through the first network connection.Type: GrantFiled: May 6, 2010Date of Patent: July 22, 2014Assignee: Siemens AGInventors: Andreas Biedermann, Bernhard Weissbach
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Patent number: 8688944Abstract: An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.Type: GrantFiled: September 20, 2011Date of Patent: April 1, 2014Assignee: Nuvoton Technology CorporationInventors: Moshe Alon, Michal Schramm, Nir Tasher
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Patent number: 8635412Abstract: A multi-processor system is disclosed comprising a first processor, a first memory coupled to the first processor, a second processor, and a shared memory subsystem including a shared memory and a data transfer unit. The first processor is configured to build a data structure in the first memory and to send a direct memory access (DMA) transfer request to the data transfer unit of the shared memory subsystem, the DMA transfer request including an address of the data structure in the first memory. The data transfer unit is configured to retrieve the data structure from the first memory based on the DMA transfer request, to store the data structure in the shared memory, and to send a shared memory pointer to the second processor indicating an address of the data structure in the shared memory.Type: GrantFiled: June 23, 2011Date of Patent: January 21, 2014Assignee: Western Digital Technologies, Inc.Inventor: James C. Wilshire
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Publication number: 20130275649Abstract: An access optimization method for a main memory database based on page-coloring is described. An access sequence of all data pages of a weak locality dataset is ordered by page-color, and all the data pages are grouped by page-color, and then all the data pages of the weak locality dataset are scanned in a sequence of page-color grouping. Further, a number of memory pages having the same page-color are preset as a page-color queue, in which the page-color queue serves as a memory cache before a memory page is loaded into a CPU cache; the data page of the weak locality dataset first enters the page-color queue in an asynchronous mode, and is then loaded into the CPU cache to complete data processing. Accordingly, cache conflicts between datasets with different data locality strengths can be effectively reduced.Type: ApplicationFiled: May 16, 2012Publication date: October 17, 2013Applicant: RENMIN UNIVERSITY OF CHINAInventors: Yan-Song Zhang, Shan Wang, Xuan Zhou, Min Jiao, Zhan-Wei Wang
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Patent number: 8407422Abstract: Methods and apparatus relating to improving address translation caching and/or input/output (I/O) cache performance in virtualized environments are described. In one embodiment, a hint provided by an endpoint device may be utilized to update information stored in an I/O cache. Such information may be utilized for implementation of a more efficient replacement policy in an embodiment. Other embodiments are also disclosed.Type: GrantFiled: April 17, 2012Date of Patent: March 26, 2013Assignee: Intel CorporationInventors: Mahesh Wagh, Jasmin Ajanovic
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Patent number: 8161243Abstract: Methods and apparatus relating to improving address translation caching and/or input/output (I/O) cache performance in virtualized environments are described. In one embodiment, a hint provided by an endpoint device may be utilized to update information stored in an I/O cache. Such information may be utilized for implementation of a more efficient replacement policy in an embodiment. Other embodiments are also disclosed.Type: GrantFiled: September 28, 2007Date of Patent: April 17, 2012Assignee: Intel CorporationInventors: Mahesh Wagh, Jasmin Ajanovic
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Publication number: 20120072666Abstract: An integrated circuit comprises trace logic for operably coupling to at least one memory element and for providing trace information for a signal processing system. The trace logic comprises trigger detection logic for detecting at least one trace trigger, memory access logic arranged to perform, upon detection of the at least one trace trigger, at least one read operation for at least one memory location of the at least one memory element associated with the at least one detected trigger, memory content message generation logic arranged to generate at least one memory content message comprising information relating to a result of the at least one read operation performed by the memory access logic, and output logic for outputting the at least one memory content message.Type: ApplicationFiled: May 29, 2009Publication date: March 22, 2012Applicant: FreescaleSemiconductor, Inc.Inventors: Bertrand Deleris, Rich Collins
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Publication number: 20110231593Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.Type: ApplicationFiled: December 1, 2010Publication date: September 22, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenta YASUFUKU, Shigeaki IWASA, Yasuhiko KUROSAWA, Hiroo HAYASHI, Seiji MAEDA, Mitsuo SAITO
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Patent number: 7809881Abstract: A recording medium, such as a high-density and/or optical recording medium including segment information recorded thereon, and apparatus and methods for recording to and reproducing from the recording medium, in order to improve data protection, data management and/or reproduction compatibility. The recording medium may contain at least one segment area which is an area on the disc controlled by a plurality of valid PACs and if the designated segment areas overlap with one another, control information of the respective PACs which control the overlapped area may be applied to control the overlapped area.Type: GrantFiled: November 24, 2008Date of Patent: October 5, 2010Assignee: LG Electronics Inc.Inventor: Yong Cheol Park
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Patent number: 7761529Abstract: Provided are a method, system, and program for managing memory requests for logic blocks or clients of a device. In one embodiment, busses are separated by the type of data to be carried by the busses. In another aspect, data transfers are decoupled from the memory requests which initiate the data transfers. In another aspect, clients competing for busses are arbitrated and selected memory requests may be provided programmable higher priority than other memory operations of a similar type.Type: GrantFiled: June 30, 2004Date of Patent: July 20, 2010Assignee: Intel CorporationInventors: Ashish V. Choubal, Madhu R. Gumma, Christopher T. Foulds, Mohannad M. Noah
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Patent number: 7606961Abstract: A computer system according to an example of the invention comprises SPEs and a global memory. The SPEs include a running SPE and an idling SPE. The running SPE and the idling SPE each have a processor core, local memory and DMA module. The local memory of the idling SPE stores data stored in the global memory and used by the processor core of the running SPE, before the data is used by the processor core of the running SPE. The DMA module of the running SPE reads the data from the local memory of the idling SPE, and transfers the data to the processor core of the running SPE.Type: GrantFiled: June 28, 2006Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Hidenori Matsuzaki
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Publication number: 20090248972Abstract: Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.Type: ApplicationFiled: June 11, 2009Publication date: October 1, 2009Inventors: Frederick A. Ware, Richard E. Perego
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Publication number: 20090031081Abstract: A system for merging electronic and printed information is provided. The system includes a computing device having a visual display. Additionally, the system includes a handheld electronic memory device containing at least one information file with information corresponding to printed information that is presented on a separate physical medium. The memory device also includes a processing file comprising stored computer-readable instructions. The system further includes an electrical connector that is attached to the handheld electronic memory device. The electrical connector connects to the computing device having the visual display so that the at least one information file and the processing file are conveyed via the electrical connector to the computing device when the electrical connector is connected to the computing device.Type: ApplicationFiled: July 25, 2007Publication date: January 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor S. Moore, Susan Wallenborn, Neil A. Katz, Mark Pozefsky
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Publication number: 20090024804Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.Type: ApplicationFiled: September 9, 2008Publication date: January 22, 2009Inventors: William R. Wheeler, Bradley Burres, Matthew J. Adiletta, Gilbert Wolrich
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Publication number: 20080052460Abstract: A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a writing memory access unit writes the data to the destination memory array according to a destination access template.Type: ApplicationFiled: October 31, 2007Publication date: February 28, 2008Applicant: CEVA D.S.P. LTD.Inventors: Gil DRORI, Erez Bar Niv, David Dahan