Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: A method for providing a first processor access to a memory associated with a second processor. The method includes receiving a first address map from the first processor that includes an MMIO aperture for a NUMA device, receiving a second address map from a second processor that includes MMIO apertures for hardware devices that the second processor is configured to access, and generating a global address map by combining the first and second address maps. The method further includes receiving an access request transmitted from the first processor to the NUMA device, generating a memory access request based on the first access request and a translation table that maps a first address associated with the first access request into a second address associated with the memory associated with the second processor, and routing the memory access request to the memory based on the global address map.

Abstract: The disclosed embodiments provide a system that uses broadcast-based TLB-sharing techniques to reduce address-translation latency in a shared-memory multiprocessor system with two or more nodes that are connected by an electrical interconnect. During operation, a first node receives a memory operation that includes a virtual address. Upon determining that one or more TLB levels of the first node will miss for the virtual address, the first node uses the electrical interconnect to broadcast a TLB request to one or more additional nodes of the shared-memory multiprocessor in parallel with scheduling a speculative page-table walk for the virtual address. If the first node receives a TLB entry from another node of the shared-memory multiprocessor via the electrical interconnect in response to the TLB request, the first node cancels the speculative page-table walk. Otherwise, if no response is received, the first node instead waits for the completion of the page-table walk.

Abstract: According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address.

Abstract: A file system layout apportions an underlying physical volume into one or more virtual volumes (vvols) of a storage system. The underlying physical volume is an aggregate comprising one or more groups of disks, such as RAID groups, of the storage system. The aggregate has its own physical volume block number (pvbn) space and maintains metadata, such as block allocation structures, within that pvbn space. Each vvol has its own virtual volume block number (vvbn) space and maintains metadata, such as block allocation structures, within that vvbn space. Notably, the block allocation structures of a vvol are sized to the vvol, and not to the underlying aggregate, to thereby allow operations that manage data served by the storage system (e.g., snapshot operations) to efficiently work over the vvols. The file system layout extends the file system layout of a conventional write anywhere file layout system implementation, yet maintains performance properties of the conventional implementation.

Abstract: A computing system comprises at least a processing module, a main memory, a memory controller, and a plurality of memory components. A method begins by the memory controller receiving a memory access request regarding a data segment. The method continues with the memory controller interpreting the memory access request to determine whether an error encoding dispersal function of the data segment is applicable. The method continues with the memory controller identifying at least a threshold number of memories based on the memory access request, wherein the threshold number of memories includes at least one of the main memory and/or one or more of the plurality of memory components, when the error encoding dispersal function is applicable. The method continues with the memory controller addressing the at least a threshold number of memories to facilitate the memory access request.

Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.

Abstract: A method, computer program product and computer system for virtualizing an SAS storage adapter, so as to allow logical partitions of a computer system to share a storage device. The method, computer program product and computer system includes assigning a logical storage adapter to an operating system of each of the logical partitions; creating a mapping from each of the logical partitions to a set of logical blocks in the storage device; and configuring the logical storage adapter using a hypervisor, so that a select partition can access a select set of logical blocks that the select partition is allowed to access.

Abstract: A computer system, having a non-volatile storage unit (152), a main storage unit (151), and a data processor (102) including a memory management unit (102A) for managing a program stored in the non-volatile storage unit and the main storage unit to transfer a program stored in the non-volatile storage unit to the main storage unit, wherein the memory management unit (102A) includes a program storage control function of storing a program subjected to predetermined data conversion and a program yet to be subjected to predetermined data conversion in the non-volatile storage unit, and a function of combining programs subjected to predetermined data conversion so as not to bridge over a boundary between blocks at the execution of the program storage control function, as well as, at a first access to a certain block, expanding all the data included in the block to a corresponding block of the main storage unit.

Abstract: A data storage device includes a storage medium configured to store data; and a controller configured to control the storage medium, the controller including address mapping information. The controller is configured to divide the address mapping information into at least a first address mapping table and a second address mapping table based on information regarding temporary data received at the controller. The first address mapping table is configured to map one or more addresses of valid data and to be backed up to the storage medium. The second mapping address table being configured to map one or more addresses of the temporary data and to not be backed up to the storage medium.

Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.

Abstract: In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system further comprises a first address hashing unit configured to receive a request including at least one virtual memory address. Each virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to data in the memory ports within a subset indicated by the corresponding subset index.

Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.

Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.

Abstract: A memory storage device, a memory controller, and a method for identifying a valid data are provided. A rewritable non-volatile memory chip of the memory storage device includes physical blocks. Each of the physical blocks has physical pages. In the present method, logical blocks are configured and mapped to a portion of the physical blocks, wherein each of the logical blocks has logical pages. When a data to be written by a host system into a specific logical page is received, a substitute physical block is selected, the data is written into a specific physical page in the substitute physical block, and the address of a physical page in which a previous data corresponding to the specific logic page is written is recorded into the specific physical page. Thereby, a physical page containing the latest valid data can be identified among several physical pages corresponding to a same logical page.

Abstract: Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining, by an operating system, a watch list of ranges of currently registered virtual addresses; upon a change in physical to virtual address mappings of a particular range of virtual addresses falling within the ranges included in the watch list, notifying the system level message passing module by the operating system of the change; and updating, by the system level message passing module, a cache of ranges of currently registered virtual addresses to reflect the change in physical to virtual address mappings.

Abstract: A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining if the translation map extends another map or a referenced map and determining if the translation map includes at least one map fragment. The referenced map is loaded in response to a determination that the translation map includes an extension of the referenced map. The map fragment is loaded in response to a determination that the translation map comprises the map fragment. A new map is compiled based on at least the translation map, the referenced map and the at least one map fragment, in response to the translation map not including a new map reference or a modification to the translation map. The input data is processed based on the new map to produce translated data specific to the new map.

Abstract: A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage devices and hosts. The storage control layer includes: a first virtual layer interfacing with the hosts, operable to represent a logical address space characterized by logical block addresses and available to said hosts and characterized by an Internal Virtual Address Space (IVAS) and operable, responsive to a configuration or I/O request addressed to the logical block addresses, to translate said logical block addresses into IVAS addresses; and a second virtual layer interfacing with the physical storage devices, operable to represent an available physical space to said hosts and characterized by a Physical Virtual Address Space (PVAS), addresses in PVAS having corresponding address in IVAS. The second virtual layer is operable to translate said respective IVAS addresses into addresses in the physical address space.

Abstract: A cache layer leverages a logical address space and storage metadata of a storage layer (e.g., storage layer) to cache data of a backing store. The cache layer maintains access metadata to track data characteristics of logical identifiers in the logical address space, including accesses pertaining to data that is not in the cache. The access metadata may be separate and distinct from the storage metadata maintained by the storage layer. The cache layer determines whether to admit data into the cache using the access metadata. Data may be admitted into the cache when the data satisfies cache admission criteria, which may include an access threshold and/or a sequentiality metric. Time-ordered history of the access metadata is used to identify important/useful blocks in the logical address space of the backing store that would be beneficial to cache.

Abstract: A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining if the translation map extends another map or a referenced map and determining if the translation map includes at least one map fragment. The referenced map is loaded in response to a determination that the translation map includes an extension of the referenced map. The map fragment is loaded in response to a determination that the translation map comprises the map fragment. A new map is compiled based on at least the translation map, the referenced map and the at least one map fragment, in response to the translation map not including a new map reference or a modification to the translation map. The input data is processed based on the new map to produce translated data specific to the new map.

Abstract: An addressing device and method is provided to enable an electronic system having a less addressing capability to address a memory device having a larger storage space, thereby reducing the manufacture cost of the electronic system. The addressing device includes an address decoder and an address translator. The address decoder receives a first access address belonging to a smaller address space, and determines whether to map the first access address to the larger storage space of the memory device. The address translator is coupled to the address decoder. When the first access address is mapped to the storage space of the memory device, the address translator translates the first access address into a second access address of the larger storage space according to an adjustable base address.

Abstract: Some embodiments of the present invention include a memory management unit (MMU) configured to, in response to a write access targeting a guest page mapping of a guest virtual page number (GVPN) to a guest physical page number (GPPN) within a guest page table, identify a first page mapping that associates the GVPN with a physical page number (PPN). The MMU is also configured to determine whether a traced write indication is associated with the first page mapping and, if so, record update information identifying the targeted guest page mapping. The update information is used to reestablish coherence between the guest page mapping and the first page mapping. The MMU is further configured to perform the write access.

Abstract: A disk drive is disclosed comprising a head actuated over a rotatable disk. A write operation is processed to write data on the disk using the head, wherein prior to writing the data on the disk, logical-to-physical mapping information is stored in a circular buffer, wherein the logical-to-physical mapping information identifies locations on the disk to write the data. A plurality of metadata files are written on the disk using the head, wherein the plurality of metadata files are interspersed with the data on the disk and each of the metadata files includes contents of the circular buffer at a time the metadata file is written on the disk. When the write operation is aborted, the logical-to-physical mapping information in the circular buffer is modified to identify the locations on the disk actually written.

Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple key values from memory. Each key value is indicates a single RV to be output by the TM. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a key selector value. A key value is selected based upon the key selector value. A RV is selected based upon the key value. The key value is selected by a key selection circuit. The RV is selected by a result value selection circuit.

Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Abstract: A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (CPUs) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system.

Abstract: A system configuration is provided that includes multiple partitions that have differing translation mechanisms associated therewith. For instance, one partition has associated therewith a single level translation mechanism for translating guest virtual addresses to host physical addresses, and another partition has a nested level translation mechanism for translating guest virtual addresses to host physical addresses. The different translation mechanisms and partitions are supported by a single hypervisor. Although the hypervisor is a paravirtualized hypervisor, it provides full virtualization for those partitions using nested level translations.

Abstract: Mechanisms are provided, in a data processing system, for accessing a memory location in a physical memory of the data processing system. With these mechanisms, a request is received from an application to access a memory location specified by an effective address in an application address space. A translation is performed, at a user level of execution, of the effective address to a real address table index (RATI) value corresponding to the effective address. At a hardware level of execution, a lookup operation is performed that looks-up the RATI value in a real address table data structure maintained by trusted system level hardware of the data processing system, to identify a real address for accessing physical memory. A memory location in physical memory is thereafter accessed based on the identified real address.

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable.

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. For a system configuration that includes partitions, the translation mechanism to be used for a partition or a portion thereof is selectable and may be different for different partitions or even portions within a partition.

Abstract: A system configuration is provided with a paravirtualizing hypervisor that supports different types of guests, including those that use a single level of translation and those that use a nested level of translation. When an address translation fault occurs during a nested level of translation, an indication of the fault is received by an adjunct component. The adjunct component addresses the address translation fault, at least in part, on behalf of the guest.

Abstract: A system configuration is provided with multiple partitions that supports different types of address translation structure formats. The configuration may include partitions that use a single level of translation and those that use a nested level of translation. Further, differing types of translation structures may be used. The different partitions are supported by a single hypervisor.

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated.

Abstract: A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.

Abstract: A virtual input/output memory management unit (IOMMU) is configured to provide a firewall around memory requests associated with an input/output (I/O) device. The virtual IOMMU uses data structures including a guest page table, a host page table and a general control register (i.e., GCR3) table. The guest page table is implemented in hardware to support the speed requirements of the virtual IOMMU. The GCR3 table is indexed using a virtual DeviceID parameter stored in a device table.

Abstract: The subject disclosure is directed towards one or more parallel storage components for parallelizing block-level input/output associated with remote file data. Based upon a mapping scheme, the file data is partitioned into a plurality of blocks in which each may be equal in size. A translator component of the parallel storage may determine a mapping between the plurality of blocks and a plurality of storage nodes such that at least a portion of the plurality of blocks is accessible in parallel. Such a mapping, for example, may place each block in a different storage node allowing the plurality of blocks to be retrieved simultaneously and in its entirety.

Abstract: Provided are a computer program product, system, and method for converting a first address mapping function for mapping addresses to storage locations to a second address mapping function. For each of a plurality of addresses allocated in the storage using the first address mapping function, a node is generated in the second address mapping function. Each node in the second address mapping function associates a logical address with a physical location for the logical address. A determination is made of addresses having unused space and storage space is freed for the determined addresses having the unused space. Indication is made in the second address mapping function that the storage space for the determined addresses has been freed.

Abstract: Techniques are described for increasing data access performance for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. Read or write access is increased by partitioning a memory into a group of sub-blocks, associating a parity block with the sub-blocks, and accessing the sub-blocks to read data as needed. Write access is increased by including a latency cache that stores data associated with a read command. Once a read-modify write command is received, the data stored in the data cache is used to update the parity block. In a memory without a parity block, write access is increased by adding one or more spare memory blocks to provide additional memory locations for performing write operations to the same memory block in parallel.

Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. When two translation table entries reference identical fragments in a memory block, one of the translation table entries is changed to refer to the same memory block referenced in the other translation table entry, which frees up a memory block. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries. When a translation table has a private delta, its delta bit is set.

Abstract: According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address.

Abstract: Embodiments of archival storage system are disclosed. The archival storage system includes one or more removable disk drives that provide random access and are readily expandable. In embodiments, some or all of the data within the removable disk drive(s) is immutable. The archiving system creates a designation for the data representing the data as having Write Once Read Many (WORM) protection. Actions associated with the data may be received and determined to be read accesses. If the actions are something other than a read access, the archiving system, in embodiments, prevents the action on the data.

Abstract: A method and apparatus for mapping virtual drives is described. In one embodiment, the method for mapping virtual drives comprises processing first locations of a plurality of file system objects within a virtual volume and converting the first locations of the plurality of file system objects within the virtual volume into second locations of the plurality of file system objects relative to a virtual drive of at least one virtual drive, wherein the at least one virtual drive form a portion of the virtual volume.

Abstract: A mechanism is provided for managing memory of a virtual machine having a runtime environment executing therein. The runtime environment includes a balloon agent that allocates memory objects within heap memory of the runtime environment and hints to a hypervisor that machine memory pages backing the memory objects may be candidates for page sharing. At launch of the runtime environment, the balloon agent allocates memory objects in response to detecting a state of high machine memory consumption by the virtual machine. Further, while the runtime environment is running, the balloon agent allocates memory objects within heap memory when the runtime environment becomes idle.

Abstract: A system and method for implementation of MMU assisted data breakpoints for any number of data structures within a program application are provided. For each data structure for which a data breakpoint is desired, two distinct MMU entries are created. One MMU entry has access attributes. The other entry has an interrupt triggering sub-entry. According to the preferred embodiment, access to the second MMU entry causes a page fault.

Abstract: A method for address translation in a memory comprising a plurality of memory streaming units (MSUs), wherein n represents the number of MSUs and n is not a power of two, and wherein the memory further comprises a striped region, the method comprising determining an MSU from among the plurality of MSUs having a physical address (PA) in the striped region corresponding to a logical address (LA) comprising performing a modulo n operation on less than all the bits representing the LA; and transmitting the LA to the MSU.

Abstract: A method includes defining a first mapping, which translates between logical addresses and physical storage locations in a memory with a first mapping unit size, for accessing the memory by a first processing unit. A second mapping is defined, which translates between the logical addresses and the physical storage locations with a second mapping unit size that is different from the first mapping unit size, for accessing the memory by a second processing unit. Data is exchanged between the first and second processing units via the memory, while accessing the memory by the first processing unit using the first mapping and by the second processing unit using the second mapping.

Abstract: System for controlling data transfer between a host system and storage devices. A virtualization controller implements the data transfer and includes first ports for connection with the storage devices, a second port for connection with the host system, a processor, and a memory configured to store volume mapping information which correlates first identification information used by the host system to access a first storage area in one of the storage devices, with second identification information for identifying the first storage area, the correlation being used by the processor to access the first storage area. When data stored in the first storage area is transferred to a second storage area, the processor correlates the first identification information with a third identification information for identifying the second storage area and registers the first identification information and the third identification information in the volume mapping information.

Abstract: A memory management and writing method for managing a memory module is provided. The memory module has a plurality of memory units and a plurality of data input/output buses corresponding to the memory units. The method includes configuring a plurality of logical units, dividing each of the logical units as a plurality of logical parts, and mapping the logical parts of each of the logical units to physical blocks of the memory units. The method also includes respectively establishing mapping tables corresponding to the data input/output buses, and only using one of the data input/output buses to write data from a host system into the corresponding memory unit according to the mapping table corresponding to the data input/output bus. Accordingly, the method can effectively increase the speed of writing data into the memory module.

Abstract: A solid-state storage device with multi-level addressing is provided. The solid-state storage device includes a plurality of flash memory devices, a volatile memory, and a controller. The controller is configured to store data received from a host in the plurality of flash memory devices in response to a write command and to read the data stored in the plurality of flash memory devices in response to a read command. The controller is further configured to maintain a multi-level address table that maps logical addresses received from the host identifying the data stored in the plurality of flash memory devices to physical addresses in the plurality of flash memory devices containing the data. A first level of the multi-level address table is maintained by the controller in the volatile memory and second and third levels of the multi-level address table are maintained by the controller in the plurality of flash memory devices.