Abstract: A method and a device for managing a node includes: initiating, by an application program, a first request by calling an interface function, where the first request is used to perform an operation on a feature node in a kernel; searching, based on a keyword of the interface function, a table used for node management for an entry corresponding to the feature node, where the entry includes a node identifier of the feature node and a user handle identifier of the feature node; and performing, by the user program, the operation on the feature node based on the user handle identifier. A program running in user space can be prevented from directly accessing a feature node in kernel space, thereby improving system security.

Abstract: Disclosed are various embodiments for a data retrieval system comprising code that accesses a data retrieval platform according to a customer identifier, the customer identifier linked to a plurality of asset identifiers, and code that access a recent correspondence history of an asset identifier of the plurality identifiers. The data retrieval system further comprises code that compares the recent correspondence history to a previous correspondence history of the asset identifier, and code that identifies a recent correspondence associated with the asset identifier in response to a difference between the recent correspondence history and the previous correspondence history. Additionally, the data retrieval system comprises code that encodes a user interface for display to a client associated with the customer identifier, the user interface comprising a portal for retrieving the recent correspondence.

Abstract: A network storage system for a download intensive environment is provided. The network storage comprises at least a data storage server (DSS) that includes an interface enabling connection of the DSS to a network at a location that enables at least a view of network transactions performed by a plurality of clients; a storage unit; and a system adapted to monitor the network transactions occurring on the network and identification of the network transactions as belonging to a registered client of the DSS, and storing in the storage the transactions with an identification corresponding to the registered client.

Abstract: A method and a system have been disclosed for the preemptive detection of occurrence of one or more faulty conditions based on the usage of one or more resources. The faulty conditions are detected during an execution of a program; the program includes at least one function. The method includes initializing Application Program Interfaces (APIs) across the at least one function. After this, calls to the APIs used within a namespace of the program are intercepted. The interception is performed by the at least one function through extended method classes. Thereafter, the usage of the resources for the at least function intercepting the APIs is checked against a corresponding predetermined threshold limit. Once the usage of the resources is checked, context of the usage of the resources is identified based on a predefined knowledge. Subsequently, the occurrence of the faulty conditions is determined based on the identification.

Abstract: A method, system, and computer program product for improving memory utilization of sparse pages are provided in the illustrative embodiments. A set of virtual pages is identified. Each virtual page in the set of virtual pages is a sparse virtual page. The set of virtual pages includes a first sparse virtual page and a second sparse virtual page. At least a portion of data of the first sparse virtual page in the set of virtual pages is stored in a first physical page. The first physical page belongs to a set of consolidation physical pages, and the first physical page also stores at least a portion of the data of the second sparse virtual page. The first and the second sparse pages are mapped to the first physical page.

Abstract: A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, a value is set for a maximum number of allowable defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.

Abstract: In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system further comprises a first address hashing unit configured to receive a request including at least one virtual memory address. Each virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to data in the memory ports within a subset indicated by the corresponding subset index.

Abstract: A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a halt instruction is issued before the first number of bytes are copied. After copying is stopped, a second number of bytes is established, encompassing those bytes remaining to be copied. After the transfer is halted, a quantity of the second number of bytes is identified. Quantity information is then generated and stored. Second source memory locations are identified to indicate where the second number of bytes are stored. Second source memory location information is then generated and stored. Second destination memory locations are then identified to indicate where the second number of bytes are to be transferred. Second destination memory location information is then generated and stored.

Abstract: Systems and methods for dynamic storage tiering using snapshot functionality are disclosed. A point-in-time copy of a virtual volume including a storage hot-spot is created; write operations directed to the virtual volume may be redirected to a point-in-time temporary virtual volume. The virtual volume segment, including the hot-spot, is copied from a first storage pool to a second storage pool. Finally, a logical block address mapping of the virtual volume is reconfigured to reference the virtual volume segment copy in the second storage pool. Upon deletion of the point-in-time copy of the virtual volume, the virtual volume segment copy in the second storage pool may be updated with data from the point-in-time temporary virtual volume.

Abstract: A storage system according to one embodiment includes logic integrated with and/or executable by a hardware processor, the logic being configured to: determine an ownership status for each of a plurality of instances of a file in a first storage tier and in a second storage tier of the storage system; determine locations of the instances of the file in the storage system; determine whether the instances of the file in the first storage tier are being accessed or not being accessed; and assign each of the instances of the file to one of a plurality of indices using the determined ownership status, location, and whether the instances are being accessed.

Abstract: In one embodiment, a system includes memory ports distributed into subsets identified by a subset index, where each memory port has an individual wait time based on a respective workload. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address referring to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

Abstract: A storage system according to one embodiment includes a first storage tier; a second storage tier; logic for storing instances of a file in the first storage tier and the second storage tier; logic for determining an ownership status for each instance of the file in the storage system, wherein the ownership status includes owned and unowned; logic for determining a location of each instance of the file in the storage system; logic for determining whether each instance of the file in the first storage tier is being accessed or not being accessed; logic for assigning each instance of the file to one of a plurality of indices using the determined ownership status, location, and whether the instance is being accessed; logic for receiving a request to access the file or instance thereof from a user; logic for selecting an instance of the file based on an assignment of the instance of the file to one of the indices; and logic for providing the user with access to the selected instance of the file or copy thereof.

Abstract: A method of dynamically switching partitions for a memory card having a plurality of physical blocks is provided. The method includes configuring logical blocks for mapping to at least a portion of the physical blocks and dividing the logical blocks into first and second partitions; coupling the memory card to a host system and setting CSD corresponding to the memory card as a first default value corresponding to the first partition, wherein the host system requests the CSD to obtain the first default value and accesses the first partition according to the first default value; and setting the CSD corresponding to the memory card as a second default value corresponding to the second partition in response to a switch command from the host system, wherein the host system re-requests the CSD to obtain the second default value and accesses the second partition according to the second default value.

Abstract: A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.

Abstract: Memory management methods and computing apparatus with memory management capabilities are disclosed. One exemplary method includes mapping an address from an address space of a physically-mapped device to a first address of a common address space so as to create a first common mapping instance, and encapsulating an existing processor mapping that maps an address from an address space of a processor to a second address of the common address space to create a second common mapping instance. In addition, a third common mapping instance between an address from an address space of a memory-management-unit (MMU) device and a third address of the common address space is created, wherein the first, second, and third addresses of the common address space may be the same address or different addresses, and the first, second, and third common mapping instances may be manipulated using the same function calls.

Abstract: An I/O request to store a file in a file-system is received. A determination is made whether the size of the file does not exceed a threshold size. Exceeding the threshold results in storing at least a portion of the file in a block of the file-system devoid of sub-blocks. A determination is made whether the size of the file does not exceed a size of unallocated space within a single block in the file-system. The single block includes a set of sub-blocks. Responsive to the size of the file not exceeding the threshold size and the size of unallocated space within the single block, the file is stored, at an address, in a first subset of the set of the sub-blocks of the single block. The address identifies the single block and a position of a sub-block in the subset.

Abstract: In one embodiment, a system comprises multiple memory ports distributed into multiple subsets, each subset identified by a subset index and each memory port having an individual wait time. The system further comprises a first address hashing unit configured to receive a read request including a virtual memory address associated with a replication factor, and referring to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address that refers to graph data in the memory ports within a subset indicated by the corresponding subset index. The system further comprises a memory replication controller configured to direct read requests to the hardware based address to the one of the memory ports within the subset indicated by the corresponding subset index with a lowest individual wait time.

Abstract: One embodiment of the present invention provides a system that accesses memory locations in an object-addressed memory system. During a memory access in the object-addressed memory system, the system receives an object identifier and an address. The system then uses the object identifier to identify a paged memory object associated with the memory access. Next, the system uses the address and a page table associated with the paged memory object to identify a memory page associated with the memory access. After determining the memory page, the system uses the address to access a memory location in the memory page.

Abstract: Virtual stacking is utilized in a virtual machine environment by receiving a data element for storage to a shared memory location and writing to the shared memory location. Writing to the shared memory location may be implemented by reading the shared memory location contents, encoding the received data element with the shared memory location contents to derive an encoded representation and writing the encoded representation to the shared memory location so as to overwrite the previous shared memory location contents. The method may further comprise receiving a request for a desired data element encoded into the shared memory location, decoding the shared memory location contents until the desired data element is recovered and communicating the requested data element.

Abstract: A mechanism for simultaneous multiple host access to shared centralized memory space via a virtualization protocol utilizing a network transport. The invention combines local memory interfacing with the handling of multiple hosts implementing virtualized memory-mapped I/O systems, such that the memory becomes a global resource. The end result is a widely distributed memory-mapped computer cluster, sharing a 2^64 byte memory space.

Abstract: According to one embodiment, a switching apparatus includes a storage module, a setting module, a managing module and a reconstruction module. The storage module stores data pertaining to the switching function by dividing the data into a plurality of groups. The setting module sets, for each of the plurality of groups, a base address to be allocated by an operating system when the program is started up. The managing module records and manages the base address and data size information of each group when the program is terminated. The reconstruction module, when the program is started up, refers to the base address and the data size information recorded when the program is terminated last time, and reconstructs data in the virtual memory space for each of the plurality of groups based on a reference result.

Abstract: A electronic device includes a diagnosing system, a processor, a storage system, a memory, and one or more programs. The one or more programs includes a determining module, an obtaining module, a processing module, and a display module. The determining module determines whether there is a bad sector in the memory. If there is a bad sector in the memory, the determining module generates an obtaining signal. The obtaining module obtains the virtual address of the bad sector according to the obtaining signal. The processing module converts the virtual address into the corresponding physical address.

Abstract: A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices and each of the slices is capable of executing an instruction of an iteration of the program loop substantially in parallel. For each iteration of the program loop, the processor executes an instruction of the sequence block using one of the slices while executing instructions of the vector block using a remainder of the slices substantially in parallel. Other methods and apparatuses are also described.

Abstract: A method and system are provided for integrating partitions in a virtual machine environment. Specifically, a partition bus is provided, where the partition bus operatively connects partitions in such a way that it functions as a data transport mechanism allowing for data transfer and device sharing between partitions. The partition bus relies on virtualizing software in order to establish itself and to establish channels of communication between partitions and to inject interrupts to partitions where it is appropriate to do so. Furthermore, the partition bus employs such mechanisms ring buffers, transfer pages, and memory map changes to transfer information (requests and data). Furthermore, it uses policy agents to decide when information should be transferred or when devices should be shared among partitions. Lastly, it employs various mechanisms to ensure smooth integration between partitions, which includes remote services that have proxy devices and device versioning functionalities.

Abstract: A data storage device includes a storage unit, and a controller configured to control the storage unit, wherein the controller is configured to manage a mapping between a logical address space and a virtual address space of the storage unit, virtual address space of the storage unit being variable.

Abstract: A virtual address scheme for improving performance and efficiency of memory accesses of sparsely-stored data items in a cached memory system is disclosed. In a preferred embodiment of the present invention, a special address translation unit is used to translate sets of non-contiguous addresses in real memory into contiguous blocks of addresses in an “intermediate address space.” This intermediate address space is a fictitious or “virtual” address space, but is distinguishable from the virtual address space visible to application programs, and in user-level memory operations, effective addresses seen/manipulated by application programs are translated into intermediate addresses by an additional address translation unit for memory caching purposes. This scheme allows non-contiguous data items in memory to be assembled into contiguous cache lines for more efficient caching/access (due to the perceived spatial proximity of the data from the perspective of the processor).

Abstract: A method is provided for creating and maintaining the validity of a cache group including one or more cache elements. Each of the cache elements corresponds to a different address space in a virtual memory of a computer system. Each of the cache elements include one or more caches that store mappings from virtual addresses to data or values that are functions of or dependent upon physical addresses that correspond to the virtual addresses. When there is an address space switch from a first address space to a second address space, the cache group is searched to find the cache element corresponding to the second address space, and that found cache element is made the current cache element for virtual memory access through the cache element. Changes in the page tables are also detected and reflected in the caches of the cache group to maintain the caches up-to-date.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled to the chipset. The chipset translates partitioned virtual machine memory addresses received from the processor to page level addresses.

Abstract: Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.

Abstract: A storage system includes a storage medium configured to store data and a buffer memory configured to buffer data to be written to the storage medium. The storage system further includes a controller configured to selectively transfer the buffered data to the storage medium responsive to an invalidity indicator received from an external source. For example, the invalidity indicator may comprise unwrite information received from an external source, e.g., information that indicates that selected buffered data corresponds to deleted file data.

Abstract: Methods and systems to selectively map higher-usage addresses to higher-endurance memory cells of a flash memory, and lower-usage addresses to lower-endurance memory cells of the flash memory. Address usage may be determined with respect to the most recent write operation corresponding to an address and/or with respect to a frequency of write operations corresponding to the address. Higher-endurance memory cells may include single level cells (SLCs). Lower-endurance memory cells may include multi-level cells (MLCs). Improved endurance may be obtained with a relatively small percentage of higher-endurance memory cells, at a relatively low cost.

Abstract: A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configured to store a third value associated with a third address space. The processing device further includes a memory management unit, which includes a first input configured to receive a first address value associated with a data transfer operation, a second input configured to receive an identifier associated with the data transfer operation, and an address space select module configured to identify a select value from the first value, the second value and the third value based on the identifier. The memory management module further includes an address modification module configured to generate a second address value based on the first address value and the select value.

Abstract: A memory module that includes a first group of memory devices arranged in one or more ranks and a second group of memory devices arranged in one or more ranks. The memory module also includes a first and second port, wherein the first port is operable simultaneously with and independently of the second port. The memory module further includes a first memory device bus in communication with the first port and the first group of memory devices, and a second memory device bus in communication with the second port and the second group of memory devices. The memory module further includes a hub device configured to re-drive information in a cascade interconnect system. The hub device includes logic for reading data from and writing data to the ranks of memory devices via the first and second ports and the first and second memory device buses.

Abstract: A disk drive system and method capable of dynamically allocating data is provided. The disk drive system may include a RAID subsystem having a pool of storage, for example a page pool of storage that maintains a free list of RAIDs, or a matrix of disk storage blocks that maintain a null list of RAIDs, and a disk manager having at least one disk storage system controller. The RAID subsystem and disk manager dynamically allocate data across the pool of storage and a plurality of disk drives based on RAID-to-disk mapping. The RAID subsystem and disk manager determine whether additional disk drives are required, and a notification is sent if the additional disk drives are required. Dynamic data allocation and data progression allow a user to acquire a disk drive later in time when it is needed. Dynamic data allocation also allows efficient data storage of snapshots/point-in-time copies of virtual volume pool of storage, instant data replay and data instant fusion for data backup, recovery etc.

Abstract: Enabling virtualization in a SAS expander is disclosed. For each SAS address to be virtualized through one or more physical or virtual Phy, a reference Phy associated with each SAS address is created within the expander. Next, a route table is generated that includes an entry for each of the SAS addresses being virtualized, each entry associated with one or more of the physical or virtual Phy through which the SAS address is being virtualized. With the route table so established, requests for a virtualized SAS address are routed to a particular one of the one or more physical or virtual Phy associated with the virtualized SAS address in the route table.

Abstract: Embodiments described are generally directed to a system and method for providing virtualized hardware resources within a virtual execution environment. In one embodiment, it is determined whether an operating system (OS) is a guest OS running within a virtual execution environment of a host platform. If an OS is determined to be a guest OS within a virtual execution environment, a virtual driver is provided for the virtual execution to fetch host hardware initiator information from a host server via a virtualization layer. In one embodiment, no corresponding guest driver is available to the virtual execution environment. In one embodiment, the virtualization layer provides virtualized hardware resources, including the virtual driver, for a virtual execution environment. Using the host hardware initiator information, in one embodiment, one or more virtual storage devices may be created within the host attached storage of the host platform. Other embodiments are described and claimed.

Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.