Abstract: A system includes calling to a first function, determination, in response to the call, of whether to execute a first version of the first function or a second version of the first function, execution of the first version of the first function if it is determined to execute the first version of the first function, and execution of the second version of the second function if it is determined to execute the second version of the first function, wherein the second version of the first function comprises a security-related features and the first version of the first function does not comprise the security-related feature.

Abstract: A respective write cycle count for each of a plurality of data units of a memory device is obtained. Based on the respective write cycle count, whether a data unit of the plurality of data units satisfies a media management criterion is determined. Responsive to determining that the respective write cycle count satisfies the media management criterion, a media management operation every first constant cycle count on the data unit is performed. Responsive to determining that the respective write cycle count does not satisfy the media management criterion, a media management operation every second constant cycle count on the data unit is performed. The second constant cycle count is less than the first constant count.

Abstract: A recovery workflow is part of an automated management service for bare metal hosts allocated for single-tenant operation in a multi-tenant environment. The health of the hosts is monitored using a set of health criteria. If it is detected that one of the host machines fails a health check then a host recovery workflow can be initiated. As part of the workflow, the failed host can be repurposed or retired. A spare host class can be used to obtain a new host to take over for the failed host. Once deployed, the operation of the new host can be tested. Upon passing the test, the new host can take over for the failed host. A new host resource can be automatically requested to be added to the spare host class in order to ensure that there are sufficient resources available in case of an additional failure.

Abstract: This application provides a method for allocating a resource of a hard disk in a distributed storage system. The distributed storage system includes a plurality of hard disks. The method includes: selecting a hard disk set from the plurality of hard disks based on a bandwidth requirement and a storage specification of a first user; and creating first logical storage space for the first user from the hard disk set, where the first storage space of each hard disk in the hard disk set provides storage space for the first logical storage space. In the method, a bandwidth lower limit of the hard disk can be ensured.

Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.

Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Abstract: Described herein is a system and method for maintaining cache coherency. The system and method may maintain coherency for a cache memory that is coupled to a plurality of primary storage devices. The system and method may write data to the cache memory and associate the data with a cache generation identification (ID). A different cache generation ID may be associated with each new set of data that is written to the cache memory. The cache generation ID may be written to the primary storage devices. A backup restore operation may be performed on one of the primary storage devices and a backup restore notification may be received. In response to the notification, the system and method may compare the cache generation ID with the generation ID stored on the restored primary storage device and invalidate data stored on the cache memory for the restored primary storage device.

Abstract: A method is used in enhancing memory buffering by using secondary storage. A buffer cache pool is supplemented with a secondary storage. A portion of a volatile memory of a data storage system is reserved as the buffer cache pool. The buffer cache pool includes a set of buffer cache objects for storing file system data and metadata. The secondary storage includes a set of data blocks. A first buffer cache object of the set of buffer cache objects is aged out by copying contents of the buffer cache object to a data block of the secondary storage. Contents of the first buffer cache object are retrieved from the secondary storage by copying contents of the data block of the secondary storage to a second buffer cache object of the set of buffer cache objects of the buffer cache pool.

Abstract: The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.

Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Abstract: In one embodiment, batch entries include multiple content-addressable memory (CAM) entries, and CAM entries are allowed to be shared among different batch entries. For example, two or more batch entries might have a common set of bits (e.g., representing an address, an address prefix, etc.). Rather than consuming bits of multiple CAM entries, a single CAM entry can be programmed with this common information. Other CAM entries associated with different batch entries are programmed with the distinguishing/different values. A batch lookup operation on a batch entry of two or more CAM entries requires multiple lookup operations on the CAM entries. One embodiment uses a batch mask vector to provide information to decode what CAM entries are shared among which batch entries during a series of lookup operations, which can be performed in one or both directions through the CAM entries.

Abstract: A method used in an access module that uses a file system to manage a nonvolatile memory of an information recording module enables an available storage space to be calculated in a short time before file data is recorded, and shortens the time required from initialization of the file system to recording. An access module (1) manages information about area management of the file system configured in an information recording module in units of fixed-length blocks. A divisional available storage space calculation unit (103) performs an available storage space calculation process in units of the fixed-length blocks, and completes preparations for recording when detecting a minimum required storage space for recording file data and enables recording of the file data. This shortens the time required from initialization of the file system to recording.

Abstract: An information processing apparatus includes a first arithmetic processing unit, a second arithmetic processing unit that is connected to a main storage, and a third arithmetic processing unit. The first arithmetic processing unit includes a cache memory that retains therein data. The second arithmetic processing unit includes a processing unit that notifies, when a read request for the data from the third arithmetic processing unit is not being executed when the replacement request is received, the first arithmetic processing unit of a completion notification indicating that the data has been written back to the main storage and the replacement process is completed and that notifies, when the read request is being executed when the replacement request is received, the first arithmetic processing unit of the completion notification after the read request has ended.

Abstract: Computer system comprising a first primary storage apparatus and a first secondary storage apparatus and a second primary storage apparatus and a second secondary storage apparatus, a first virtual volume of the second primary storage apparatus is externally connected to a first primary volume of the first primary storage apparatus, a total cache-through mode is configured as a cache mode in a case where a read command is supplied by the first host apparatus, unique information for the first primary volume is configured for the first virtual volume, a path to the first primary volume is switched from the first host apparatus to a path via the first virtual volume, and a second primary volume in the second primary storage apparatus is configured to form a copy pair with a second secondary volume in the second secondary storage apparatus.

Abstract: A storage system including first storage devices constituting a first logical storage area, second storage devices constituting a second logical storage area; and a storage control apparatus. The storage control apparatus manages the first and second logical storage areas so that the data stored in the first and second logical storage areas have redundancy, and parity data for the data stored in the second logical storage area are stored in parity storage areas arranged in part of the second storage devices. When part of the first storage devices constituting part of the first logical storage area fail, the storage control apparatus generates part of the data stored, before the failure, in the part of the first storage devices, and stores the generated part of the data in at least part of the second parity storage areas in the second logical storage area.

Abstract: A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.

Abstract: Customers of shared resources in a multi-tenant environment can modify operational parameters of electronic resources. A customer can be provisioned a data volume of a specified size, storage type (e.g., hard disk drive or solid state device), committed rate of input/output operations per second, and/or geographical location, for example. The customer can subsequently modify any such operational parameters by submitting an appropriate request, or the operational parameters can be adjusted automatically based on any of a number of criteria. Data volumes for the customer can be migrated, split, or combined in order to provide the shared resources in accordance with the modified operational parameters.

Abstract: The present disclosure discloses a method, a system and a server of removing a distributed caching object. In one embodiment, the method receives a removal request, where the removal request includes an identifier of an object. The method may further apply consistent Hashing to the identifier of the object to obtain a Hash result value of the identifier, locates a corresponding cache server based on the Hash result value and renders the corresponding cache server to be a present cache server. In some embodiments, the method determines whether the present cache server is in an active status and has an active period greater than an expiration period associated with the object. Additionally, in response to determining that the present cache server is in an active status and has an active period greater than the expiration period associated with the object, the method removes the object from the present cache server.

Abstract: Various embodiments of the present invention are directed multi-core memory modules. In one embodiment, a memory module (500) includes memory chips, and a demultiplexer register (502) electronically connected to each of the memory chips and a memory controller. The memory controller groups one or more of the memory chips into at least one virtual memory device in accordance with changing performance and/or energy efficiency needs. The demultiplexer register (502) is configured to receive a command indentifying one of the virtual memory devices and send the command to the memory chips of the identified virtual memory device. In certain embodiments, the memory chips can be dynamic random access memory chips.

Abstract: In a multi-processor (e.g., multi-core) computer system, several processors can simultaneously access data without corruption thereof by: designating to each processor a portion of a hash table containing the data; by allowing each processor to access only those data elements belonging to the portion of the hash table designated to that processor; and by sending, via a network, other data elements to the processors that are designated the portions of the hash table to which the other data elements belong. The network avoids memory contention at each processor without requiring a memory-based lock. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: In one embodiment, multiple content-addressable memory entries are associated with each other to effectively form a batch content-addressable memory entry that spans multiple physical entries of the content-addressable memory device. To match against this content-addressable memory entry, multiple lookup operations are required—i.e., one lookup operation for each combined physical entry. Further, one embodiment provides that a batch content-addressable memory entry can span one, two, three, or more physical content-addressable memory entries, and batch content-addressable memory entries of varying sizes could be programmed into a single content-addressable memory device. Thus, a lookup operation might take two lookup iterations on the physical entries of the content-addressable memory device, with a next lookup operation taking a different number of lookup iterations (e.g., one, three or more).

Abstract: A workload-aware distributed data processing apparatus and method for processing large data based on hardware acceleration are provided. The data processing apparatus includes a memory buffer including partitions. The data processing apparatus further includes a partition unit configured to distribute a mapping result to the partitions based on a partition proportion scheme. The data processing apparatus further includes a reduce node configured to receive content of a corresponding one of the partitions, and perform a reduction operation on the content to generate a reduce result.

Abstract: A multi-core system includes processor cores having caches; an external input/output bus connected to the processor cores; memory accessed by the processor cores via the external input/output bus; profile information indicating the volume of a write access to the memory by tasks concurrently allocated to the processor cores and whether a cache miss will occur in a read access to the caches; and an operating system that controls clock frequency of the external input/output bus to be a first frequency, based on the volume of the write access to the memory by the tasks and the bus width of the external input/output bus when a cache miss in read access is judged to not occur in executing the tasks and that controls the clock frequency of the external input/output bus to be a second frequency higher than the first frequency when a cache miss in read access is judged.

Abstract: A memory system may include an optimized data compaction algorithm. The compaction may include transferring only valid data from a source block to a destination block. A compaction bitmap that is maintained in random access memory (“RAM”) may be populated during the compaction process. The populated bitmap may be used to copy valid fragments to the destination block.

Abstract: A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A memory control module may control operations of the memory array, and an encoder module may encode input data for storing to the memory array. The memory array may be an m×n memory array, and the memory control module may control operations of storing data to and retrieving data from the memory array.

Abstract: A controller is connectable to a host system and a plurality of storage devices. A monitor unit monitors operating status of a plurality of storage devices and sets the operating status of the storage devices in a status table. Upon receiving a write command from the host system, a command responding unit receives write data sent from the host system within a certain period of time after the write command, holds the write data received in a buffer memory, instructs a timer to start counting, sets a write destination for data in the status table, outputs a control signal that gives an instruction to write data to the storage device of the write destination, and returns a write completion response corresponding to the write command to the host system when receiving the deadline notification from the timer.

Abstract: A method, device, and system are disclosed. In one embodiment method begins by incrementing a count of a total number of write operations to a non-volatile memory storage for each write operation to the non-volatile memory storage. The method then receives a request for the total count of lifetime write operations from a requestor. Finally, the method sends the total count of lifetime write operations to the requestor.

Abstract: Disclosed is a host bus adapter (HBA) that to receives an input/output (I/O) command from an operating system I/O driver. Firmware stored on the host bus adapter includes primary firmware and secondary firmware to process the I/O command. The HBA is to respond to the I/O command under the control of one of the primary firmware or secondary firmware. The selected one of said primary firmware and secondary firmware may be used to certify a hardware driver for either the current generation (primary firmware) or a future generation (secondary firmware).

Abstract: A method for performing a write to a source volume in a multi-target architecture is described. The multi-target architecture includes a source volume and multiple target volumes mapped thereto. In one embodiment, such a method includes copying data in a track of the source volume to a corresponding track of a target volume (target x). The method enables one or more sibling target volumes (siblings) mapped to the source volume to inherit the data from the target x. When the data is successfully copied to the target x, the method performs a write to the track of the source volume. Other methods for reading and writing data to volumes in the multi-target architecture are also described.

Abstract: The present disclosure discloses a method, a system and a server of removing a distributed caching object. In one embodiment, the method receives a removal request, where the removal request includes an identifier of an object. The method may further apply consistent Hashing to the identifier of the object to obtain a Hash result value of the identifier, locates a corresponding cache server based on the Hash result value and renders the corresponding cache server to be a present cache server. In some embodiments, the method determines whether the present cache server is in an active status and has an active period greater than an expiration period associated with the object. Additionally, in response to determining that the present cache server is in an active status and has an active period greater than the expiration period associated with the object, the method removes the object from the present cache server.

Abstract: A management server and a data migration method enabling a storage apparatus to be replaced while retaining data consistency and without halting access by a host apparatus are proposed.

Abstract: Storage management technology, in which a system determines a first amount of storage space on a downloader device of a user that is available for download of new content made available on channels subscribed to by the user. The system also determines a second amount of storage space needed to download new content that has been made available on channels subscribed to by the user. The system further compares the second amount of storage space to the first amount of storage space and determines whether the second amount of storage space exceeds the first amount of storage space. Based on a determination that the second amount of storage space exceeds the first amount of storage space, the system controls downloading of the new content to the downloader device and deletion of previously-stored content on the downloader device based on a content allocation policy.

Abstract: A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

Abstract: A memory access device includes a second memory coupled between a processor and a first memory; a memory controller configured to transfer a data from the first memory to the second memory based on a transfer request; a read controller configured to read the data from the second memory, output the data to the processor, and control a read pointer indicating an address reading the data from the second memory; and a write controller configured to output the transfer request to the memory controller, wherein the write controller computes an available capacity of the second memory based on the read pointer, a size of the second memory and a cumulative addition value obtained by adding cumulatively a size of the data which is requested from the processor, and outputs the transfer request based on the available capacity.

Abstract: A storage system includes a first storage unit, a second storage unit and a controller to receive a write request for updated data to a first storage unit from the host and write the updated data into the first storage area, when the controller determines that there is not a free area in a storage area to be processed in the second storage unit, the controller changes the storage area to be processed to another storage area to be processed and instructs change of a storage area to be processed to another storage system to be connected to the host, and the controller reads the updated data from the first storage unit and transmits the updated data and writing destination information relating to the updated data to another storage system for backup.

Abstract: A method for programming data into a first plurality of rows within a second plurality of erase sectors of a flash memory device using a programming process having at least one selectable parameter, the method includes characterizing each of at least one row subsets, each row subset comprising at least one row from among said first plurality of rows, thereby to generate at least one row subset characteristic value; and programming data into at least a portion of at least one individual row belonging to at least one row subset, using a programming process having at least one selectable parameter, said at least one selectable parameter being set at least partly in accordance with the row subset characteristic value characterizing a row subset to which said individual row belongs; wherein at least two row subsets of an array of flash memory cells differ from each other by their row subset characteristic values.

Abstract: A storage apparatus includes a memory that stores data groups, a rearranging unit that rearranges a transmission group order of the data groups based on each of storage positions in a storage device provided in a copy destination storage apparatus in which the each of data groups is to be stored, and a transmitting unit that transmits the data groups rearranged by the rearranging unit to the copy destination storage apparatus.

Abstract: Remote memory can be used for a number idle pages located on a virtual machine. A number of idle pages can be sent to the remote memory according to a placement policy, where the placement policy can include a number of weighting factors. A hypervisor on a computing device can record a local size and a remote page fault frequency of the number of virtual machines. The hypervisor can scan local memory to determine the number of idle pages and a number of idle virtual machines. The number of idle pages, including a page map and a remote address destination for each idle page, can be sent to the remote memory by the hypervisor. The number of virtual machines can be analyzed to determine a per-virtual machine local memory allocation.

Abstract: According to one general aspect, a method is provided for managing memory when counting unique items, the method using a pattern of bits in a unique estimator mask. The method may create a unique estimator mask based on fingerprints calculated for previously encountered items, and determine a number with the highest probability for creating the pattern of bits in the mask. When the number with the highest probability is determined, it may be returned as the estimated count of unique items.

Abstract: Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module (500) includes at least one virtual memory device and a demultiplexer register (502) disposed between the at least one virtual memory device and a memory controller. The demultiplexer register receives a command identifying one of the at least one virtual memory devices from the memory controller and sends the command to the identified virtual memory device. In addition, the at least one virtual memory devices include at least one memory chip.

Abstract: The present disclosure discloses a method, a system and a server of removing a distributed caching object. In one embodiment, the method receives a removal request, where the removal request includes an identifier of an object. The method may further apply consistent Hashing to the identifier of the object to obtain a Hash result value of the identifier, locates a corresponding cache server based on the Hash result value and renders the corresponding cache server to be a present cache server. In some embodiments, the method determines whether the present cache server is in an active status and has an active period greater than an expiration period associated with the object. Additionally, in response to determining that the present cache server is in an active status and has an active period greater than the expiration period associated with the object, the method removes the object from the present cache server.

Abstract: Systems and methods for sharing a physical cache among one or more clients in a stream data processing pipeline are described. One embodiment is directed to a system for sharing caches between two or more clients. The system comprises a physical cache memory having a memory portion accessed through a cache index. The system further comprises at least two virtual cache spaces mapping to the memory portion, each of the virtual cache spaces has an active window which has a different size than the memory portion. Further, the system comprises at least one virtual cache controller configured to perform a hit-miss test on the active window of the virtual cache space in response to a request from one of the clients for accessing the physical cache memory. Furthermore, data is accessed from the corresponding location of the memory portion when the hit-miss test of the cache index returns a hit.

Abstract: A method and apparatus for mitigating the performance impact of background or idle time processing during interactive computing sessions. One embodiment of the present invention is a method for mitigating performance impact of background or idle time processing on interactive applications comprising identifying executable and data pages in physical memory that are associated with an interactive application that is temporarily unused and preventing any of the identified executable and data pages from paging out.

Abstract: A data processing system includes a first master having a cache, a second master, a memory operably coupled to the first master and the second master via a system interconnect. The cache includes a cache controller which implements a set of cache coherency states for data units of the cache. The cache coherency states include an invalid state; an unmodified non-coherent state indicating that data in a data unit of the cache has not been modified and is not guaranteed to be coherent with data in at least one other storage device of the data processing system, and an unmodified coherent state indicating that the data of the data unit has not been modified and is coherent with data in the at least one other storage device of the data processing system.

Abstract: A mechanism for random cache line selection in virtualization systems is disclosed. A method includes maintaining a secondary data structure representing a plurality of memory pages, the secondary data structure indexed by a subset of each memory page, determining an index of a received new memory page by utilizing a subset of the new memory page that is a same size and at a same offset as the subset of each memory page, comparing the index of the new memory page with the indices of the secondary data structure for a match, utilizing a main data structure to perform a full page memory comparison with the new memory page if a match is found in the secondary data structure, and updating at least one of the size of the subset, the number of subsets, and the offsets of the subsets used to index the memory page.

Abstract: A method and system are provided for determining a next available address for writing data to a cache memory. In one implementation, a method includes receiving a request for a candidate address in the cache memory, the cache memory divided into a plurality of banks. The method further includes determining a candidate address in each of the cache memory banks using an address determination algorithm, selecting one of the candidate addresses from among the determined candidate addresses using an address selection function different from the address determination algorithm, and returning the selected candidate address in response to the request.

Abstract: A remote copy system includes a first storage device performing data transmission/reception with a host computer, a second storage device receiving data from the first storage device, and a third storage device receiving data from the second storage device. The first storage device includes a logical volume, the second storage device includes a logical volume being a virtual volume, and the third storage device includes a logical volume. The first storage system changes the state of a first pair of the logical volumes based on the state of a second pair of the logical volumes. With such a remote copy system and a method for use therein, any data backup failure can be prevented.

Abstract: A main memory data rewriting device includes a rewrite condition analysis unit configured to analyze a rewrite condition for target data in main memory data stored in a main memory before deactivation of an information processing device, and create a first processing content to acquire environment data substituting the target data from outside of the information processing device and a second processing content to rewrite the target data to the environment data, an environment data processing unit configured to acquire the environment data according to the first processing content when the information processing device is temporarily activated at an activation time set to rewrite the target data during a deactivating period of the information processing device, and a rewrite processing unit configured to rewrite a region of a nonvolatile storage medium in which the target data is stored with the environment data according to the second processing content.

Abstract: A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) fetches first instructions for execution in a multi-processor system. The TCUEP associates a first instruction timestamp with each of the first instructions. The TCUEP receives a multi-processor coherency operation and increments the first timestamp value in a master-tag register to form a second timestamp value after receiving the multi-processor coherency operation. The TCUEP fetches, by an instruction fetch unit in the first microprocessor, second instructions for execution in the multiprocessor system. The TCUEP associates a second instruction timestamp with each of the second instructions. The TCUEP enables an emulated purge mechanism to suppress hits in the translation lookaside buffers for the second instructions. The TCUEP after determining the first instructions are complete, purges entries in the translation lookaside buffers and disables the emulated purge mechanism.

Abstract: A switch connects and disconnects an input and output control device to and from an input and output device. The switch includes a storage unit that stores therein a translation table for use in translating a physical address used on a virtual machine that a guest operating system specifies as a direct memory access transfer destination to the input and output device, into a physical address used on a real machine; and an address translating unit that translates an address contained in a direct memory access request issued by the input and output device into a physical address used on the real machine by referring to the translation table.