Abstract: An information handling system includes a hardware processor, a memory device operatively coupled to a serial peripheral interface (SPI) chip and the hardware processor. The SPI chip interfaces the hardware processor executing plural stages of boot modules during a boot process of the information handling system with allocated, reserved portions of the memory device for each stage of boot module executed in pre-boot, boot, and runtime via a virtual memory interface generated by execution of an original equipment manufacturer (OEM)-defined agnostic memory allocation module. The hardware processor executes the OEM defined agnostic memory allocation firmware to redefine the virtual memory interface for each allocated reserved portion of the memory device at each of the plural stages of the boot modules that are executed from pre-boot, through boot, and to runtime to provide adjustments to allocated, reserved portions of memory for later stages of executed plural stages of the boot modules.

Abstract: A monitoring device has an event monitor, an uplink interface to a chain controller device, and a downlink interface to a further monitoring device, and a daisy controller for coupling the uplink to the chain downlink. The event monitor, in response to detecting an event in sleep mode, generates a wake-up signal. The daisy controller sets the electronic monitoring device to a wake-up request mode and disables the bidirectional data communication via the downlink interface, and subsequently transmits a wake-up request to the chain controller device via the uplink interface. In response to receiving a wake-up command, the daisy controller re-enables the bidirectional data communication via the downlink interface and sets the electronic monitoring device to the operational mode. Thereby a wake-up sequence is performed while the wake-up request mode avoids bus conflicts.

Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.

Abstract: In one embodiment, batch entries include multiple content-addressable memory (CAM) entries, and CAM entries are allowed to be shared among different batch entries. For example, two or more batch entries might have a common set of bits (e.g., representing an address, an address prefix, etc.). Rather than consuming bits of multiple CAM entries, a single CAM entry can be programmed with this common information. Other CAM entries associated with different batch entries are programmed with the distinguishing/different values. A batch lookup operation on a batch entry of two or more CAM entries requires multiple lookup operations on the CAM entries. One embodiment uses a batch mask vector to provide information to decode what CAM entries are shared among which batch entries during a series of lookup operations, which can be performed in one or both directions through the CAM entries.

Abstract: Embodiments of the present invention provide a SSD-based high-speed cache storage system. Specifically, in a typical embodiment, a network cache component (NCC) is coupled to a high-speed cache storage pool (HCSP). The NCC generally comprises: a set of semiconductor storage device (SSD) memory disk units for storing data; a network cache controller coupled to the set of SSD memory units; a network traffic analysis component coupled to the network cache controller; a network interface coupled to the network traffic analysis component; a general storage controller coupled to the network cache controller; and a general storage interface coupled to the general storage controller. Moreover, the HCSP typically comprises a cache server, an internal interface, and a general storage system coupled to one another.

Abstract: A method can include receiving memory configuration information that specifies a memory configuration; receiving memory usage information for the memory configuration; analyzing the received memory usage information for a period of time; and, responsive to the analyzing, controlling notification circuitry configured to display a graphical user interface that presents information for physically altering a specified memory configuration. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.

Abstract: A method for transferring data in a memory system including at least first and second memories, includes activating the first memory to conduct a read operation, activating the second memory during the read operation of the first memory, and transferring data which is obtained from the read operation, directly to the second memory from the first memory.

Abstract: A volume migration method for causing to carry out a migration from a first volume manager to a second volume, includes: by causing the first volume manager to carry out actual accesses, obtaining information of correspondence, by the first volume manager, between logical volume offsets and physical blocks on a physical medium; judging, based on the obtained information of the correspondence, whether or not an exceptional data layout is carried out; and when it is judged that the exceptional data layout is not carried out, updating only a header area on the physical medium for the second volume manager. Incidentally, the aforementioned obtaining is carried out by using a program module for blocking access by the first volume manager to the physical medium. Thus, when only the header area is updated after it is confirmed the exceptional data layout is not made, the high-speed volume migration becomes possible.

Abstract: Logical-physical translation information comprises information denoting the corresponding relationships between multiple logical pages and multiple logical chunks forming a logical address space of a nonvolatile semiconductor storage medium, and information denoting the corresponding relationships between the multiple logical chunks and multiple physical storage areas. Each logical page is a logical storage area conforming to a logical address range. Each logical chunk is allocated to two or more logical pages of multiple logical pages. Two or more physical storage areas of multiple physical storage areas are allocated to each logical chunk. A controller adjusts the number of physical storage areas to be allocated to each logical chunk.

Abstract: Some embodiments of the invention pertain to a memory system containing multiple memory devices, in which one or multiple ones of the memory devices may flexibly be selected at one time for a common operation to be performed by all the selected devices concurrently.

Abstract: Methods, apparatus, and products for reliable memory mapping in a computing system, the computing system including a plurality of memory modules, including: determining, by a channel mapping module, a reliability rating for each of a plurality of memory controller address ranges; mapping, by the channel mapping module, critical system-level memory addresses to the most reliable memory controller address ranges; and directing, by the channel mapping module, memory accesses addressed to a critical system-level memory address to the most reliable memory controller address ranges.

Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.

Abstract: This invention provides, when optimizing a configuration of a storage system using a pool, an optimal configuration while ensuring a policy set by an administrator, the policy concerning a power saving performance, a response performance, or the like. The management computer sets, according to the set policy, priorities to volumes held by a storage subsystem, and reserves volumes satisfying the capacity of the pool, in descending order of the priority. Only some of the reserved volumes are registered for the pool in descending order of the priority. At this time, it can be guaranteed that a host computer makes no access to the volumes which have not been registered for the pool, and therefore the sleep state is set to physical drives forming the volumes or to a controller controlling the physical drives.

Abstract: A storage system 100, which has a plurality of flash packages 230, has a function for minimizing the imbalance of the number of deletions of each block inside the flash package 230 and a block-unit capacity virtualization function, and efficiently manifests lessening of the imbalance of the number of deletions and reduction in the data storage capacity for the entire storage system 100 by having functions for calculating the number of deletions and the data occupancy of each flash package 230, and for transferring data between the flash packages 230 on the basis of the values of these number of deletions and data occupancy.

Abstract: A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network (at least half, and barrel shifters in 8-tuple embodiments) is disposed between the memory bank and the forward unit and the backward unit. A set of control signals is generated which are applied to the half or more butterfly network (and to the barrel shifters where present) so as to access the memory bank with an n-tuple parallelism in a linear order in a first instance, and a quadratic polynomial order in a second instance, where n=2, 4, 8, 16, 32, . . . . This access is for any n-tuple of the logical addresses, and is without memory access conflict. In this manner memory access may be controlled data decoding.

Abstract: A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data and access to memory. The communications medium and memory access control logic are designed to accommodate a heterogenous collection of main memory configurations, in which at least one physical parameter is variable for different configurations. The bits of the memory address are mapped to actual memory locations by assigning fixed bit positions to the most critical physical parameters across multiple different module types, and assigning remaining non-contiguous bit positions to less critical physical parameters. In the preferred embodiment, the computer system employs a distributed memory architecture.

Abstract: A data storage device comprising: at least two flash devices for storing data; a circuit board, wherein each of the flash devices are integrated on the circuit board; a controller integrated on the circuit board for reading and writing to each flash devices, wherein the controller interfaces each flash devices; at least one NOR Flash device in communication with the controller through a host bus; at least one host bus memory device in communication with the controller and at least one NOR Flash device through the host bus; at least one interface in communication with the controller and adapted to physically and electrically couple to a system, receive and store data therefrom and retrieve and transmit data to the system.

Abstract: An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the same propagation time regardless of which device is involved. The hub receives memory signals from a controller over a high speed data link which the hub translates into electrical data, command and address signals. These signals are applied to the memory devices over busses having equivalent path lengths. The busses may also be used by the memory devices to apply data signals to the memory hub. Such data signals can be converted by the memory hub into memory signals and applied to the controller over the high speed data link. In one example, the memory hub is located in the center of the memory module.

Abstract: A data storage device comprising: at least two flash devices for storing data; a circuit board, wherein each of the flash devices are integrated on the circuit board; a controller integrated on the circuit board for reading and writing to each flash devices, wherein the controller interfaces each flash devices; at least one NOR Flash device in communication with the controller through a host bus; at least one host bus memory device in communication with the controller and at least one NOR Flash device through the host bus; at least one interface in communication with the controller and adapted to physically and electrically couple to a system, receive and store data therefrom and retrieve and transmit data to the system.

Abstract: A scheme is provided that guarantees the completion of cache invalidation processing in an information processing apparatus that performs directory-based coherence control. Each processor includes a cache and a Fence control unit that transmits an identifier to be returned to its own processor toward each bank through a network at timing when guarantee of completion of consistency processing of data stored in shared memory and the cache is requested and confirms that the identifier is returned from each bank. Each bank includes a memory main body, a directory that issues an invalidation request for invalidating the data stored in the cache according to an area where the data is written to the memory main body, and an invalidation request queue that queues the invalidation request and the identifier and transmits one of the invalidation request and the identifier through the network in a sequence of queuing.

Abstract: In one embodiment, a method is disclosed for timing responses to a plurality of memory requests. The method can include sending a plurality of memory requests to a plurality of in-line memory modules. The requests can be sent over a channel from a plurality of channels, where each channel can have a plurality of lanes. The method can receive responses to the plurality of memory requests over the channel and monitor the response to detect a timing relationship between at least two lanes from the plurality of lanes. In addition, the method can adjust a timing of a register loading and unloading sequence in response to the monitoring of multiple lanes and channels. Other embodiments are also disclosed.

Abstract: A timing device, that may be used in connection with food preparation, holding or service equipment, is programmable via a portable, replaceable media. In particularly, the timing device may be adapted to receive or associate with a media containing a set of instructions to affect operation of the timing device. Upon association with the timing device, transfer of the programming instructions from the media to the timing device occurs affecting programming of the timing device.

Abstract: There is provided techniques for automating attachment of a server to a storage area network (SAN). In accordance with one embodiment, a method is provided which includes storing identifiers in a memory associated with an enclosure adapted to house one or more servers. The identifiers are correlated to a particular location of the enclosure. Additionally, the method includes providing the identifiers from the memory to host bus adapters (HBAs) associated with a particular location when a server is placed in the particular location.

Abstract: A storage controller that can control memory addresses even when a memory module having a different device configuration than an already mounted memory module is added as an expansion module. More specifically, a storage controller for controlling a storage unit that can be constructed using a plurality of memory modules is configured so as to include: a register which stores memory module configuration information for a basic memory module and an expansion memory module independently of each other; and an address conversion unit which, based on the memory module configuration information stored in the register, generates an address that can access the storage unit even when the memory address space of the expansion memory module is different from the memory address space of the basic memory module.

Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.

Abstract: In a RAID management apparatus, a disk determination unit accesses each of RAID devices, determines a copy source disk, and sets a pointer of the determined copy source disk into a disk management table stored in a storage unit. When an input-output (I/O) processing unit accesses a disk, if an I/O error occurs on the disk, as a result a copy source disk and a copy destination disk are switched; the I/O processing unit renews a pointer associated with the copy source disk in the disk management table stored in the storage unit, and a disk notification unit notifies that the copy source disk and the copy destination disk are switched.

Abstract: The present invention relates to a method for addressing the memory locations of a memory card. There are several memory locations in a memory card for storing data, in which case in order to address a specific memory location an address is formed. At least one parameter is stored in the memory card, on the basis of which parameter the number of memory locations of a memory card can be calculated, and a specific number of bits is reserved for said at least one parameter. In the method, two or more memory locations are addressed with one address, and/or the number of bits that can be used in an address is increased. The invention also relates to a system and a memory card in which the method is applied.