Abstract: Systems, apparatuses, and methods related to a memory device and an associated host device are described. The memory device and the host device can include control logic that allow the memory device and host device to share refresh-timing information, which may allow either the memory device or the host, or both, to manage operations during time that is dedicated to, but unused for, refresh or self-refresh operations. Refresh-timing information shared from the host device may indicate elapsed time since the host device issued a refresh command to the memory device and/or how much time remains before the host device is scheduled to issue another refresh command. Refresh-timing information shared from the memory device may indicate elapsed time since the memory device performed a self-refresh operation and/or how much time remains before the memory device is scheduled to initiate or undergo another self-refresh operation.

Abstract: An apparatus comprising an array controller and a cache. The array controller may be configured to read/write data to a first array of drives of a first drive type in response to one or more input/output requests. The cache may be configured to (i) receive said input/output requests from the array controller, (ii) temporarily store the input/output requests, and (iii) read/write data to a second array of drives of a second drive type in response to the input/output requests. The first array of drives may be configured to copy the data directly to/from the second array of drives during a cache miss condition such that the array controller retrieves the data stored in the first array of drives through the second array of drives without writing the data to the cache.

Abstract: A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.

Abstract: A method can include receiving memory configuration information that specifies a memory configuration; receiving memory usage information for the memory configuration; analyzing the received memory usage information for a period of time; and, responsive to the analyzing, controlling notification circuitry configured to display a graphical user interface that presents information for physically altering a specified memory configuration. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.

Abstract: A method, system and computer-program product for re-initializing a storage volume with an previously created volume map being preserved to allow access to previously stored data sets. The invention includes creating a new volume map in an unused volume area where the new volume map has pointers to new data sets. One of the new data sets contains the previously created volume map that points to previously created data sets. Each volume map is referenced by a volume label and includes a VTOC and an optional VTOC index. The pointers in the VTOC are data set control block (DSCB) records.

Abstract: An unmount state storing unit configured to store a state of unmount processing to end access processing to a memory card attached to a device from a host computer is provided. During a period from immediately after a host computer executes the unmount processing until detaching of the memory card is detected, a value of the host computer unmount state storing unit is stored as “true”. During the period in which this value is “true”, a host computer mount request from another host computer is denied. Consequently, after the access processing to the memory card attached to a device by the host computer has ended, contents of the memory card cannot be read from the other host computer while the memory card is still attached.

Abstract: A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.

Abstract: A method and apparatus for a virtual storage device is provided. In one example, data to be stored at a removable storage device is received. A virtual storage agent is executed on the removable storage device. An interlace is established with at least one remote storage location. The data is stored at the at least one remote storage location. In another example, a request to access data associated with a removable storage device is received. A virtual storage agent on the removable storage device is executed. An interface is established with at least one remote storage location. The data is fetched from the at least one remote storage location.

Abstract: A memory system includes a nonvolatile memory, and a memory controller for performing control to extend the maximum value of a logical address by erasing data of the nonvolatile memory which has become unnecessary in accordance with a command from the outside, and reassigning the data which has become unnecessary to a memory area assigned to a part of the logical address.

Abstract: Non-volatile storage devices and methods capable of achieving large capacity solid state drives containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and a memory controller. The bank switching circuitry is integrated onto the memory controller and functionally interposed between the banks of memory devices and the front end of the memory controller. The bank switching circuitry operates to switch accesses by the memory controller among the at least two banks.

Abstract: Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter.

Abstract: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.

Abstract: A prefetch device and method are disclosed that determines from which addresses to speculatively fetch data based on information collected regarding previous cache-miss addresses. A historical record showing a propensity to experience cache-misses at a particular address-offset from a prior cache-miss address within a region of memory provides an indication that data needed by future instructions has an increased likelihood to be located at a similar offset from a current cache-miss address. The prefetch device disclosed herein maintains a record of the relationship between a cache-miss address and subsequent cache-miss addresses for the most recent sixty-four unique data manipulation instructions that resulted in a cache-miss. The record includes a weighted confidence value indicative of how many cache-misses previously occurred at each of a selection of offsets from a particular cache-miss address.

Abstract: Disclosed are a redundant data storage system (e.g., a RAID system) and a method of operating such a redundant data storage system that provides significant power savings with minimal reduction in reliability. The system and method allow up to half of the memory devices in any of the memory arrays in the system to be placed in standby without significantly impacting the read accesses. The system and method further designate reserved areas in the active memory devices as write-journals, which have at least the same level of protection as the main arrays. The write-journals allow data to be written without powering up a standby memory device. Thus, power consumption is minimized without impacting reliability.

Abstract: Apparatus and method of managing a nonvolatile memory are disclosed where the nonvolatile-memory-managing apparatus includes a nonvolatile memory that has a first block and a second block having one or more physical pages, and an operation unit that determines the type of merge operation to perform for the first block and second block according to whether logical page offsets recorded in consecutive physical pages of the first block increases in steps and in repeating order.

Abstract: A dynamic random access memory may include at least one group of memory cells, and a respective auxiliary memory for each group of memory cells. The respective auxiliary memory is for storing refresh information specific to each respective group of memory cells. The refresh information may include a current refresh period and a time remaining before refresh.