For I/o Modules, E.g., Memory Mapped I/o, Etc. (epo) Patents (Class 711/E12.082)
  • Patent number: 9026767
    Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: May 5, 2015
    Assignee: Intel Corporation
    Inventors: Andre Schaefer, Matthias Gries
  • Patent number: 9015399
    Abstract: The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: April 21, 2015
    Assignee: Convey Computer
    Inventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
  • Patent number: 8984243
    Abstract: Customers of shared resources in a multi-tenant environment can modify operational parameters of electronic resources. A customer can be provisioned a data volume of a specified size, storage type (e.g., hard disk drive or solid state device), committed rate of input/output operations per second, and/or geographical location, for example. The customer can subsequently modify any such operational parameters by submitting an appropriate request, or the operational parameters can be adjusted automatically based on any of a number of criteria. Data volumes for the customer can be migrated, split, or combined in order to provide the shared resources in accordance with the modified operational parameters.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 17, 2015
    Assignee: Amazon Technologies, Inc.
    Inventors: Tao Chen, Marc John Brooker, Haijun Zhu
  • Patent number: 8904087
    Abstract: The invention provides a portable memory medium with a memory area and a memory management system for managing the memory area, wherein different options for access to the memory area are provided. The memory management system comprises a configuration command, the execution of which causes an activation of one of at least two different activatable memory configurations.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: December 2, 2014
    Assignee: Giesecke & Devrient GmbH
    Inventor: Armin Bartsch
  • Patent number: 8892832
    Abstract: Provided are a storage apparatus, a storage management method, and a storage management program capable of performing a backing-up operation under the condition that a host computer is in operation. A storage apparatus 1 according to the present invention includes a cache memory 20, a storage device 30 that stores data, a data copy unit 12 that copies the data to be stored in the storage device 30 in a storage device for duplication 40, and a control unit 11 in which, when writing data in the storage device 30, if the data copy unit 12 is executing a separation copy which does not allow data rewriting during copying, the data to be written in the storage device 30 is stored in the cache memory 20, and after completing the separation copy, the data stored in the cache memory 20 is written in the storage device 30.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: November 18, 2014
    Assignee: NEC Corporation
    Inventor: Takashi Fuju
  • Patent number: 8849647
    Abstract: Disclosed is a host bus adapter (HBA) that to receives an input/output (I/O) command from an operating system I/O driver. Firmware stored on the host bus adapter includes primary firmware and secondary firmware to process the I/O command. The HBA is to respond to the I/O command under the control of one of the primary firmware or secondary firmware. The selected one of said primary firmware and secondary firmware may be used to certify a hardware driver for either the current generation (primary firmware) or a future generation (secondary firmware).
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: September 30, 2014
    Assignee: LSI Corporation
    Inventors: Rajiv Bhatia, Ankit Sihare
  • Patent number: 8832350
    Abstract: A method and apparatus for efficient memory bank utilization in multi-threaded packet processors is presented. A plurality of memory access requests, are received and are buffered by a plurality of memory First In First Out (FIFO) buffers, each of the memory FIFO buffers in communication with a memory controller. The memory access requests are distributed evenly across said memory banks by way of the memory controller. This reduces and/or eliminates memory latency which can occur when sequential memory operations are performed on the same memory bank.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: September 9, 2014
    Assignee: Avaya Inc.
    Inventors: Hamid Assarpour, Mike Craren, Rich Modelski
  • Patent number: 8737156
    Abstract: A solution is provided to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices, while satisfying the capacity requirements for the flash memory devices in a system design, wherein a decoding unit is used for determining which flash memory devices will be accessed and re-mapping incoming serial addressing bits, for accessing one flash memory device, into an outgoing serial addressing bits for accessing another flash memory device.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: May 27, 2014
    Assignee: ITE Tech. Inc.
    Inventor: Ching-Min Hou
  • Publication number: 20140089632
    Abstract: Divisions by numbers that are not divisible by two (2) can be performed in a computing system based on a summation that estimates and/or approximates the reciprocal of the dividing number or denominator value. By way of example, dividing by three (3) can be calculated based on a summation that approximates or estimates one third (?) represented as the sum of a selected group of the inverses of the powers of two (2) in a pattern, namely the sum of: ¼, 1/16, 1/64, 1/256, . . . ). Applications of the division techniques are virtually unlimited and include memory mapping of global memory addresses to memory channel addresses by dividing a global memory address into the number of memory channels, allowing memory mapping to be performed in an efficient manner even for large memory spaces using a number of memory channels that are not divisible by two, including prime numbers.
    Type: Application
    Filed: September 25, 2012
    Publication date: March 27, 2014
    Inventor: Jeremy Branscome
  • Patent number: 8631187
    Abstract: A device, system, and method are disclosed. In one embodiment the device includes a non-volatile memory (NVM) storage array to store a plurality of storage elements. The device also includes a dual-scope directory structure having a background space and a foreground space. The structure is capable of storing several entries that each correspond to a location in the NVM storage array storing a storage element. The background space includes entries for storage elements written into the array without any partial overwrites of a previously stored storage element in the background space. The foreground space includes entries for storage elements written into the array with at least one partial overwrite of one or more previously stored storage elements in the background space.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: January 14, 2014
    Assignee: Intel Corporation
    Inventor: Andrew Vogan
  • Publication number: 20130254454
    Abstract: According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions. The memory controller is configured to execute memory accesses to the banks based on the instructions. Each memory access comprises a first command sequence and a second command sequence. The first command sequence causes in-bank processing shortly subsequent to the first command. The second command sequence is executed subsequent to the in-bank processing. The memory controller executes successively a second command sequence to a first bank based on a first instruction and a first command sequence to the first bank based on a second instruction subsequent to the first instruction, and then starts a memory access to a second bank based on a third instruction while the first bank is executing the in-bank processing caused by the first command sequence.
    Type: Application
    Filed: August 31, 2012
    Publication date: September 26, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi IDE, Kiyotaka IWASAKI, Kouji WATANABE, Hiroyuki NANJOU, Makoto MORIYA
  • Publication number: 20130111101
    Abstract: A semiconductor memory device includes a path control unit configured to activate an address transmission path corresponding to a bank address, an address providing unit configured to provide a memory address to the path control unit in response to an active signal, and a plurality of memory banks each configured to receive the memory address provided through the corresponding address transmission path of the path control unit, wherein the bank address corresponds to a memory bank of the plurality of memory banks.
    Type: Application
    Filed: December 21, 2011
    Publication date: May 2, 2013
    Inventor: Seok-Cheol YOON
  • Publication number: 20130013843
    Abstract: Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Either the processor or an operating system (OS) determines a first version number corresponding to the first data structure. During initialization of the first data structure, the first version number may be stored in a first location in the spare bank. The processor receives from the OS a pointer holding the first version number. When the processor executes memory access operations targeting the first data structure, the processor compares the first version number with a third version number stored in a location in the physical memory indicated by the memory access address. The processor may set a trap in response to determining a mismatch.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Inventors: Zoran Radovic, Graham Ricketson Murphy, Bharat K. Daga
  • Publication number: 20120278524
    Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.
    Type: Application
    Filed: June 11, 2012
    Publication date: November 1, 2012
    Applicant: Round Rock Research, LLC
    Inventors: Terry R. Lee, Joseph M. Jeddeloh
  • Publication number: 20120246380
    Abstract: A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element.
    Type: Application
    Filed: October 6, 2010
    Publication date: September 27, 2012
    Inventors: Avidan Akerib, Eli Ehrman, Oren Agam, Moshe Meyassed, Yehoshua Meir, Yukio Fukuzo
  • Publication number: 20120215960
    Abstract: A device for increasing chip testing efficiency includes a pattern generator, a reading unit, a logic operation circuit, and a judgment unit. The pattern generator is used for writing a logic voltage to each bank of a memory chip. The reading unit is used for reading logic voltages stored in all memory cells of each bank. The logic operation circuit is used for executing a first logic operation on the logic voltages stored in all memory cells of each bank to generate a plurality of first logic operation results corresponding to each bank, and executing a second logic operation on the plurality of first logic operation results to generate a second logic operation result corresponding to the memory chip. The judgment unit determines whether the memory chip passes the test according to the second logic operation result.
    Type: Application
    Filed: January 5, 2012
    Publication date: August 23, 2012
    Inventors: Shi-Huei Liu, Sen-Fu Hong, Ho-Yin Chen
  • Publication number: 20120159038
    Abstract: Systems and methods for re-mapping memory transactions are described. In an embodiment, a method includes receiving a memory request from a hardware subsystem to a memory, replacing a first identifier with a modified identifier in the memory request, and transmitting the memory request to the memory through a processor complex. The method further includes receiving a response from the memory, determining that the response corresponds to the memory request, replacing the modified identifier with the first identifier in the response, and transmitting the response to the hardware subsystem. In some embodiments, a system may be implemented as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Inventors: Deniz Balkan, Gurjeet S. Saund
  • Patent number: 8190809
    Abstract: A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable locations and each addressable location is correlated to one storage location. Each storage location contains a respective bank select. The addressable locations and storage locations are grouped into interleave patterns such that, for each pattern, there are Q storage locations and 2A addressable locations arranged in L sequential loops each containing Q sequentially addressable locations and a remainder loop containing R sequentially addressable locations, where L·Q+R=2A. A shunt defines a non-zero offset for each interleave so that each interleave commences with a different bank select and a complete rotation of all of the interleaves addresses each of the memory banks an equal number of times. The shunt (S) may be selected as mod(2A,Q), ?Q+mod(2A,Q), ±1 or ±prime to , where ?<S<+.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: May 29, 2012
    Assignee: Efficient Memory Technology
    Inventor: Maurice L. Hutson
  • Patent number: 8171239
    Abstract: A storage management system and a storage management method are provided. The storage management system includes a host, a memory buffer, a plurality of storage blocks, and an input/output bus to perform an interface function among the host, the memory buffer, and the plurality of storage blocks, wherein each of the plurality of storage blocks is connected with the input/output bus via a corresponding channel, and the plurality of storage blocks is managed for each channel group generated by grouping at least one channel.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: May 1, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keun Soo Yim, Gyu Sang Choi
  • Patent number: 8135936
    Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 13, 2012
    Assignee: Intel Corporation
    Inventors: Andre Schaefer, Matthias Gries
  • Publication number: 20120005400
    Abstract: A memory module such as a DIMM includes two separate memories with corresponding data, address and control interfaces. Each separate memory core includes plural memory banks for corresponding portions of the data interface. The separate interfaces include separate byte strobes and control signals. The two memories may be separately powered or share power connection. The two memories may be disposed on a single semiconductor integrated circuit or separate semiconductor integrated circuit. The two memories may be connected to two external memory interfaces of a single data processor or to separate data processors.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 5, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: William Hinson Winderweedle
  • Publication number: 20110320680
    Abstract: A method and apparatus for efficient memory bank utilization in multi-threaded packet processors is presented. A plurality of memory access requests, are received and are buffered by a plurality of memory First In First Out (FIFO) buffers, each of the memory FIFO buffers in communication with a memory controller. The memory access requests are distributed evenly across said memory banks by way of the memory controller. This reduces and/or eliminates memory latency which can occur when sequential memory operations are performed on the same memory bank.
    Type: Application
    Filed: November 24, 2010
    Publication date: December 29, 2011
    Applicant: AVAYA INC.
    Inventors: Hamid Assarpour, Mike Craren, Rich Modelski
  • Publication number: 20110307643
    Abstract: Memory management process for optimizing the access to a central memory located within a processing system comprising a set of specific units communicating with each other through said memory, said process involving the steps of: a) arranging in a local memory at least a first and a second bank of storage (A, B) for the purpose of temporary object exchanged between a first data object producer (400) and a second data object consumer (410); b) arranging a address translation process for mapping the real address of an object to be stored within said banks into the address of the bank; b) receiving one object produced by said producer and dividing it into stripes of reduced size; c) storing the first stripe into said first bank; d) storing the next stripe into said second bank while the preceding stripe is read by said object consumer (410); e) storing the next stripe into said first bank again while the preceding stripe is read by said object consumer (410).
    Type: Application
    Filed: December 29, 2009
    Publication date: December 15, 2011
    Applicant: ST-ERICSSON SA
    Inventor: David Coupe
  • Publication number: 20110296078
    Abstract: Techniques are provided which may be implemented in various methods and/or apparatuses that to provide a memory pool interface capability to interface with a plurality of shared processes/engines and/or a virtual buffer interface associated there with.
    Type: Application
    Filed: October 1, 2010
    Publication date: December 1, 2011
    Applicant: QUALCOMM Incorporated
    Inventors: Raheel Khan, Min Wu
  • Publication number: 20110289258
    Abstract: Embodiments of a memory system that communicates bidirectional data between a memory controller and a memory IC via bidirectional links using half-duplex communication are described. Each of the bidirectional links conveys write data or read data, but not both. States of routing circuits in the memory controller and the memory IC are selected for a current command being processed so that data can be selectively routed from a queue in the memory controller to a corresponding bank set in the memory IC via one of the bidirectional links, or to another queue in the memory controller from a corresponding bank set in the memory IC via another of the bidirectional links. This communication technique reduces or eliminates the turnaround delay that occurs when the memory controller transitions from receiving the read data to providing the write data, thereby eliminating gaps in the data streams on the bidirectional links.
    Type: Application
    Filed: February 2, 2010
    Publication date: November 24, 2011
    Applicant: RAMBUS INC.
    Inventor: Frederick A. Ware
  • Publication number: 20110283043
    Abstract: Non-volatile storage devices and methods capable of achieving large capacity solid state drives containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and a memory controller. The bank switching circuitry is integrated onto the memory controller and functionally interposed between the banks of memory devices and the front end of the memory controller. The bank switching circuitry operates to switch accesses by the memory controller among the at least two banks.
    Type: Application
    Filed: July 13, 2011
    Publication date: November 17, 2011
    Applicant: OCZ TECHNOLOGY GROUP INC.
    Inventor: Franz Michael Schuette
  • Publication number: 20110283042
    Abstract: A transaction splitting apparatus and method are provided in which neighboring sub-transactions accessing a predetermined bank in each memory may access different banks. The transaction splitting apparatus includes a first processing unit to split a transaction into at least one sub-transaction, the transaction accessing a first bank among a plurality of banks comprised in a memory, and a second processing unit to translate an address of the at least one sub-transaction, to interleave the at least one sub-transaction using the plurality of banks.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 17, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Sun Jeon, Ho Jin Lee, Joon Hyuk Cha, Shi Hwa Lee, Young Su Moon, Hyun Sang Park
  • Publication number: 20110276740
    Abstract: A controller for a solid state disk is provided. The controller includes a storage module to store an index of at least one idle bank among a plurality of memory banks, and a control module to control an access to the at least one idle bank using the stored index. Here, the access to the at least one idle bank may be controlled based on a state of a channel corresponding to each of the at least one idle bank.
    Type: Application
    Filed: October 30, 2009
    Publication date: November 10, 2011
    Applicant: INDILINX CO., LTD.
    Inventors: Yongsik Joo, Hyunmo Chung
  • Publication number: 20110264930
    Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.
    Type: Application
    Filed: April 26, 2010
    Publication date: October 27, 2011
    Applicant: BROADCOM CORPORATION
    Inventors: Lawrence J. Madar, III, Mark N. Fullerton, Bhupesh Kharwa
  • Publication number: 20110258362
    Abstract: A memory apparatus (100, 200, 300, 500, 600, 700) has a plurality of memory banks (d0 to d7, m0 to m3, p, p0, p1), wherein a write or erase operation to the memory banks (d0 to d7, m0 to m3, p, p0, p1) is substantially slower than a read operation to the banks (d0 to d7, m0 to m3, p, p0, p1). The memory apparatus (100, 200, 300, 500, 600, 700) is configured to read a redundant storage of data instead of a primary storage location in the memory banks (d0 to d7, m0 to m3, p, p0, p1) for the data or reconstruct requested data in response to a query for the data when the primary storage location is undergoing at least one of a write operation and an erase operation.
    Type: Application
    Filed: December 19, 2008
    Publication date: October 20, 2011
    Inventors: Moray McLaren, Jr. Eduardo Argollo de Oliveira Dias, Paolo Faraboschi
  • Patent number: 8019927
    Abstract: An electronic tag system, an electronic tag, and a controlling method thereof according to the present invention include an electronic tag that includes a memory having a divided band and a bank status that stores a status of data stored in the divided bank, a controlling circuit that reads and writes the data from and to the bank and changes the status and a controlling device that allows the controlling circuit connected through the electronic tag and an electronic tag reader/writer to transmit and receive the read and written data from and to the bank and issue an instruction to change the status.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: September 13, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Osamu Ishihara
  • Publication number: 20110179213
    Abstract: A memory module and a memory module system are provided. The memory module system includes a plurality of memory modules each module comprising a plurality of memory blocks and a plurality of corresponding routers each storing a channel identification (ID) and a module ID corresponding to one or more memory blocks; and a controller configured to access the memory modules. During initialization, the controller reads and stores the channel ID and the module ID from each of the routers. The controller outputs a channel ID and a module ID that correspond to one or more memory blocks to be accessed.
    Type: Application
    Filed: March 29, 2011
    Publication date: July 21, 2011
    Inventor: Jeon Taek IM
  • Publication number: 20110167193
    Abstract: A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 7, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sujeet Ayyapureddi
  • Publication number: 20110153908
    Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: Intel Corporation
    Inventors: Andre Schaefer, Matthias Gries
  • Publication number: 20110138101
    Abstract: A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 9, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kattamuri Ekanadham, Il Park, Pratap Pattnaik
  • Publication number: 20110138100
    Abstract: A method and system for permitting host write operations in one part of a flash memory concurrently with another operation in a second part of the flash memory is disclosed. The method includes receiving data at a front end of a memory system, selecting at least one of a plurality of subarrays in the memory system for executing a host write operation, and selecting at least one other subarray in which to execute a second operation. The write operation and second operation are then executed substantially concurrently. The memory system includes a plurality of subarrays, each associated with a separate subarray controller, and a front end controller adapted to select and initiate concurrent operations in the subarrays.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 9, 2011
    Inventor: Alan Sinclair
  • Patent number: 7958303
    Abstract: Methods and systems for managing and locating available storage space in a system comprising data files stored in a plurality of storage devices and configured in accordance with various data storage schemes (mirroring, striping and parity-striping). A mapping table associated with each of the plurality of storage devices is used to determine the available locations and amount of available space in the storage devices. The data storage schemes for one or more of the stored data files are changed to a basic storage mode when the size of a new data file configured in accordance with an assigned data storage scheme exceeds the amount of available space. The configured new data file is stored in accordance with the assigned data storage scheme in one or more of the available locations and the locations of the new data file are recorded.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: June 7, 2011
    Inventor: Gary Stephen Shuster
  • Publication number: 20110078360
    Abstract: It is an object of the invention to provide a memory architecture that can handle data interleaving efficiently. This and other objects are achieved by the system according to the invention. The data handling system, is configured for receiving at an input a plurality of commands. The system comprises: a plurality of memory banks; a distributor connected to the input and having a plurality of distributor outputs. Each specific one of the plurality of memory banks (106) is connected to a specific one of the plurality of distributor outputs. The distributor comprises a permutator for designating for each specific command a specific distributor output. The distributor distributes the specific command to the specific designated distributor output. The permutator has a control input and the designating is reconfigurable under the control of reconfiguration data received at the control input.
    Type: Application
    Filed: May 19, 2009
    Publication date: March 31, 2011
    Applicant: NXP B.V.
    Inventors: Erik Rijshouwer, Cornelis Hermanus van Berkel
  • Publication number: 20110040923
    Abstract: A data packet access control apparatus and a data packet access control method are disclosed. RAM resources in a data packet processing chip are used to implement a Bypass FIFO. The Bypass FIFO is used as a first-level cache for small amount of data, and an external RAM of the data packet processing chip is used as a second-level cache for large amount of data. In this way, some data packets are read and written within the chip and not all data packets have to be read and written through the external RAM. A data packet reading/writing operation may be performed to the external RAM by a BANK interleave mode.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 17, 2011
    Applicant: Hangzhou H3C Technologies Co., Ltd.
    Inventor: Kai REN
  • Patent number: 7870349
    Abstract: A method for accessing a memory is provided. The method includes entering a memory accessing mode for updating a top of low memory (TOLM) value stored in a TOLM register in a chipset of a system with a highest memory address when a memory accessing command is received. The memory accessing command requests the utilization of a memory block in a memory of the system corresponding to an address space occupied by a memory-mapped input output (MMIO) function. The system then accesses the corresponding memory block in the memory according to the address space recorded in the memory accessing command. After the access is completed, the memory accessing mode is closed and the original TOLM value is written back to the TOLM register. Therefore, the present invention can access the “MMIO memory block” to prevent a waste of the memory.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: January 11, 2011
    Assignee: Inventec Corporation
    Inventor: Ying-Chih Lu
  • Publication number: 20100332895
    Abstract: Subject matter disclosed herein relates to remapping memory devices.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 30, 2010
    Inventors: Gurkirat Billing, Stephen Bowers, Mark Leinwander, Samuel David Post
  • Publication number: 20100312990
    Abstract: Systems, methods of operating a memory device, and methods of arbitrating access to a memory array in a memory device having an internal processor are provided. In one or more embodiments, conflicts in accessing the memory array are reduced by interfacing an external processor, such as a memory controller, with the internal processor, which could be an embedded ALU, through a control interface. The external processor can control access to the memory array, and the internal processor can send signals to the external processor to request access to the memory array. The signals may also request a particular bank in the memory array. In different embodiments, the external processor and the internal processor communicate via the control interface or a standard memory interface to grant access to the memory array, or to a particular bank in the memory array, for example.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 9, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Robert Walker
  • Publication number: 20100312944
    Abstract: The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.
    Type: Application
    Filed: June 4, 2009
    Publication date: December 9, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Robert Walker
  • Patent number: 7844787
    Abstract: Techniques for data replication are presented. A snap shot request is processed within an environment associated with a local volume by flushing pending Input/Output (I/O) operations into an event packet. The event packet is sent to a replicated volume and processed against the replicated volume to create a snap shot version of the local volume.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: November 30, 2010
    Assignee: Novell, Inc.
    Inventors: Shyamsundar Ranganathan, Kalidas Balakrishnan
  • Publication number: 20100241782
    Abstract: A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times.
    Type: Application
    Filed: March 20, 2009
    Publication date: September 23, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventors: Srinivas Maddali, Deepti Vijayalakshmi Sriramagiri
  • Publication number: 20100241783
    Abstract: A memory node for use within a data storage system having a plurality of interconnected memory nodes is provided. The memory node comprises three data input interfaces, three data output interfaces, a memory module for storing data, and a controller coupled to the three data output interfaces, the three data input interfaces, and the memory module. The controller is configured to receive data via one of the three input interfaces, the data having a predetermined destination, read a first portion of the data to determine if the memory node is the predetermined destination, store a second portion of the data on the memory module, if the memory node is the predetermined destination, and transmit the received data via at least one of the three data output interfaces, if the memory node is not the predetermined destination.
    Type: Application
    Filed: March 23, 2009
    Publication date: September 23, 2010
    Applicant: Honeywell International Inc.
    Inventors: Fernando Garcia, David Christopher Hearn
  • Publication number: 20100217915
    Abstract: A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks.
    Type: Application
    Filed: February 23, 2009
    Publication date: August 26, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James A. O'Connor, Kevin C. Gower, Luis A. Lastras-Montano, Warren E. Maule
  • Publication number: 20100205346
    Abstract: An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.
    Type: Application
    Filed: February 8, 2010
    Publication date: August 12, 2010
    Inventors: Zeke R. Lundstrum, Vivien Delport, Sean Steedman, Joseph Julicher
  • Publication number: 20100199062
    Abstract: A coordinator in a computer system receives a request from one of a plurality of operating systems (that coexist in the computer system) to invoke a service of a management routine in the computer system. The plurality of operating systems execute in respective virtual machines of the computer system. The coordinator processes the received request to invoke the service of the management routine to prevent a conflict from occurring with respect to at least another one of the plurality of operating systems.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Inventors: Jose A. Sancho-Dominguez, Louis B. Hobson
  • Publication number: 20100191894
    Abstract: A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips.
    Type: Application
    Filed: January 29, 2009
    Publication date: July 29, 2010
    Applicant: International Business Machines Corporation
    Inventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Philip Raymond Germann, William Paul Hovis, Mark Owen Maxson