Abstract: Memory augmented neural networks may use one or more neural encoders to transform input data into distributed representations and a memory module to store the representations with individual addresses. Memory augmented neural networks allow for few-shot learning capabilities because latent representations are persistent between training examples and gradient-based updates affect only certain memory locations via content-based lookups. When a query vector is not found in memory and the memory is full, existing memories that are positively associated with a particular representation may be identified, redundant memories may be aged, and updated memories may be generated. These updated memories retain relevant information acquired during training and reduce redundancy in the memories stored using the memory module, thereby improving the efficiency of data storage and reducing overfitting of data typically encountered with existing neural networks using memory modules.

Abstract: A transaction accelerator may be connected between at least one host device and a bus, and a method of operating the transaction accelerator may include receiving a first transaction request from the at least one host device, transmitting the first transaction request to the bus, and transmitting a first transaction response corresponding to the first transaction request to the at least one host device, in response to the transmitting the first transaction request to the bus.

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

Abstract: A system and method for providing dynamic device virtualization is herein disclosed. According to one embodiment, the computer-implemented method includes providing a hypervisor and one or more guest virtual machines (VMs). Each guest VM is disposed to run a guest user process and the hypervisor is split into a device hypervisor and a compute hypervisor. The computer-implemented method further includes providing an interface between the device hypervisor and the compute hypervisor. The compute hypervisor manages an efficient use of CPU and memory of a host and the device hypervisor manages a device connected to the host by exploiting hardware acceleration of the device.

Abstract: A memory card includes first and second interface units connected to a system host, a memory unit, and an additional information registration unit. The memory unit includes a first identifier storage unit that stores an identifier of the memory unit, a flash memory, and a memory controller that controls the first identifier storage unit and the flash memory via the first interface unit. The additional information registration unit includes a second identifier storage unit that stores an identifier same as the identifier of the memory unit, and an additional information notification unit that notifies the system host of the identifier in the second identifier storage unit and additional information via the second interface unit. When the memory card is connected to the system host, the memory unit and the additional information registration unit are associated with each other by the identifiers stored in the first and second identifier storage units.

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Abstract: Example systems and related methods may relate to compressing a plurality of data channels. An example embodiment may include a controller determining a plurality of interleave allocations within a memory allocation. The interleave allocations correspond to a plurality of planes, which may represent color information planes. The plurality of data channels may be compressed into a plurality of compressed data channels. Subsequently, each of the plurality of compressed data channels may be stored at respective interleave allocations. A full interleave allocation condition may be determined based on a capacity of a respective interleave allocation being less than a predetermined threshold. In response to determining the full interleave allocation condition, a new interleave allocation may be requested from the controller. In response, the controller may determine a new interleave allocation.

Abstract: A method can include receiving memory configuration information that specifies a memory configuration; receiving memory usage information for the memory configuration; analyzing the received memory usage information for a period of time; and, responsive to the analyzing, controlling notification circuitry configured to display a graphical user interface that presents information for physically altering a specified memory configuration. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.

Abstract: A method and system are provided for programming a plurality of memory devices arranged in parallel. In one embodiment of the present invention, the plurality of memory devices comprises first and second memory devices, and the method comprises providing successively the first address to the first memory device and the second address to the second memory device. The first address refers to a first group of storage locations in the first memory device and the second address refers to a second group of storage locations in the second memory device. The method then proceeds to load in parallel a string of data to the first and second memory devices so that the string of data is written simultaneously to the first group of storage locations in the first memory device and to the second group of storage locations in the second memory device.

Abstract: A method for operating a data storage system that includes a plurality of mass storage devices, which are configured to store data redundantly, the method including determining a characteristic service level of one or more of the mass storage devices and defining a reduced service level, which is less than the characteristic service level. The method further includes performing the following steps automatically: detecting the reduced service level on a first mass storage device in the data storage system; determining that data on the first mass storage device is stored redundantly on a second mass storage device in the data storage system; and in response to detecting the reduced service level, diverting an input/output (IO) request for the data directed to the first mass storage device to the second mass storage device, while operating the first mass storage device at the reduced service level.