Abstract: In programming environments, an object can be extended by adding a new property (subroutine) to the collection of the object properties. The properties of the object can be accessed using property access syntax. Extension property call is an innovation which allows the use of an object together with property access expression to access the properties (subroutines) that are not contained in the object itself, but which are contained in another object and are visible in the scope where the property access expression is used. The extension properties do not have special extension property definition syntax. Any regular property (subroutine) can be used as the extension property of the object if the property is visible in the scope where the property access expression is used. Extension property calls makes programming language code concise, improving code readability.

Abstract: A computing device determines a node traversal order for computing a computational parameter value for each node of a data model of a system that includes a plurality of disconnected graphs. The data model represents a flow of a computational parameter value through the nodes from a source module to an end module. A flow list defines an order for selecting and iteratively processing each node to compute the computational parameter value in a single iteration through the flow list. Each node from the flow list is selected to compute a driver quantity for each node. Each node is selected from the flow list in a reverse order to compute a driver rate and the computational parameter value for each node. The driver quantity or the computational parameter value is output for each node to predict a performance of the system.

Abstract: Systems, methods, and computer-readable media are provided for determining a packet's round trip time (RTT) in a network. A system can receive information of a packet sent by a component of the network and further determine an expected acknowledgement (ACK) sequence number associated with the packet based upon received information of the packet. The system can receive information of a subsequent packet received by the component and determine an ACK sequence number and a receiving time of the subsequent packet. In response to determining that the ACK sequence number of the subsequent TCP packet matches the expected ACK sequence number, the system can determine a round trip time (RTT) of the packet based upon the received information of the packet and the received information of the subsequent packet.

Abstract: The disclosed embodiments relate to implementation of a trading system or trading system architecture having multiple transaction processors that execute financial transactions as well as scheduled tasks. The multiple transaction processors perform all actions independently of each other, but can be configured to execute the financial transactions or scheduled tasks in a controlled, coordinated, and/or synchronized manner based on time signal data augmented to the financial transactions or scheduled tasks by a transaction receiver/orderer.

Abstract: The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, the operating parameters of the GPU may be changed.

Abstract: Specifications are input, comprising: a plurality of lanes in an environment for a controlled system; a plurality of lane maneuvers associated with the plurality of lanes; a plurality of lane subconditions associated with the controlled system; and a rule set comprising a plurality of rules, wherein a rule in the rule set specifies a rule condition and a rule action to take when the rule condition is satisfied, wherein the rule condition comprises a corresponding set of lane subconditions, and wherein the rule action comprises a corresponding lane maneuver. The controlled system is automatically navigated dynamically, at least in part by: monitoring the plurality of lane subconditions; evaluating rule conditions associated with the plurality of rules in the rule set to determine one or more rules whose corresponding rule conditions has been met; and executing one or more lane maneuvers that correspond to the one or more determined rules.

Abstract: Techniques in advanced deep learning provide improvements in one or more of accuracy, performance, and energy efficiency. An array of processing elements performs flow-based computations on wavelets of data. Each processing element has a compute element and a routing element. Each router enables communication via wavelets with at least nearest neighbors in a 2D mesh. Routing is controlled by virtual channel specifiers in each wavelet and routing configuration information in each router. Execution of an activate instruction or completion of a fabric vector operation activates one of the virtual channels. A virtual channel is selected from a pool comprising previously activated virtual channels and virtual channels associated with previously received wavelets. A task corresponding to the selected virtual channel is activated by executing instructions corresponding to the selected virtual channel.

Abstract: The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, context switching may or may not be triggered.

Abstract: A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.

Abstract: The disclosed embodiments relate to implementation of a trading system or trading system architecture having multiple transaction processors that process or execute instructions. The instructions are sent to the transaction processors before they are to be executed, so that when an instruction identifier corresponding to a pre-sent or pre-loaded instruction is sent to a transaction processor, the transaction processor can retrieve and execute the corresponding instruction without unnecessary delay, thus reducing transaction processing latency and improving computing efficiency.

Abstract: A generating unit 30 which is included in a cooperative planning system 10: generates a plurality of partial procedures by dividing the generated change procedure for each procedure which relates to an element of each of the system configurations; with respect to a first partial procedure which includes a first step after which, when execution is completed, execution is commenced of a second step which is included in a second partial procedure, adds, after the first step, a step in which information is inputted to the planning system which executes the second partial procedure, said information indicating the completion of the procedure; and with respect to the second partial procedure, adds, prior to the second step, a step in which information is inputted from the planning system which executes the first partial procedure, said information indicating the completion of the procedure.

Abstract: A system in accordance with present embodiments includes an amusement park system having one or more hardware components and a controller. The controller includes a memory device having a game layer and a software layer stored thereon. The game layer includes game logic, and the software layer includes a game API communicatively coupled to the game layer, a wrapper API communicatively coupled to the game API, and multiple wrappers communicatively coupled to the wrapper API. The controller further includes a processor configured to execute instructions to cause the processor to receive a signal indicative of a change in the hardware components, and, based on the signal indicative of the change in the hardware components, communicate with the hardware components via a wrapper to receive an input from the hardware components, or drive operation of the hardware components.

Abstract: Embodiments of the present disclosure relate to an accelerator circuit with a dynamic immediate values table (IVT). The accelerator circuit includes an instruction memory, a data memory, and a vector circuit with the IVT storing multiple immediate values at multiple entries. The vector circuit reads a subset of instructions from the instruction memory, each instruction including at least one corresponding pointer to at least one corresponding entry in the IVT. The vector circuit further receives a subset of input data from the data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction from the subset of instructions using a corresponding data vector of the received subset of input data identified in each instruction and at least one corresponding immediate value from the IVT pointed by the at least one corresponding pointer to generate corresponding output data.

Abstract: An associative-memory-storage unit, and to an associative-memory-storage method are provided. The associative-memory-storage unit includes a first subset of at least memory sub-units over w bits, and a second memory sub-unit over v bits. The associative-memory-storage sub-unit may be used to associate messages with labels, and vice versa.

Abstract: A method of rotating assigned credentials for client devices registering with servers may include determining that assigned credentials for a client device are expired; in response to determining that the assigned credentials have expired, generating new credentials for the client device; sending the new credentials to the client device; generating an encrypted version of the new credentials and storing the encrypted version of the new credentials at the server during a grace period, where during the grace period the client device can be authenticated using the assigned credentials or the new credentials; and deleting the encrypted version of the new credentials at an expiration of the grace period.

Abstract: There is provided input circuitry to receive input data. Output circuitry outputs a sequence of instructions to be executed by data processing circuitry. Generation circuitry performs a generation process to generate the sequence of instructions using the input data with at least some of the instructions being grouped into functions. The sequence of instructions comprises an indirect control flow instruction comprising a field that indicates where a target of the indirect control flow instruction is stored. The target is an entry point to one of the functions and the generation process causes at least one of the instructions in the sequence of instructions to store a state of control flow speculation after execution of the indirect control flow instruction.

Abstract: A computing system can be configured to perform operations in a define phase including receiving a component specification including a transformation function; inputting the component specification into a define function; receiving, as an output of the define function, the factory function; and receive data describing a second software component that satisfies the component specification of the first software component. In an assembly phase after the define phase, the computing system can input, into the factory function, the first software component and the second software component; and receiving, as an output of the factory function, the assembled software system including the first software component connected with the second software component according to the component specification of the first software component.

Abstract: A control panel may include a control surface and a plurality of user control areas at fixed locations along the control surface, a sealing layer extending continuously over the user control areas, wherein the sealing layer includes at least one topographical feature associated with at least one of the user control areas, and a pressure-sensitive capacitive touch layer provided at the at least one user control area, the a pressure-sensitive capacitive touch layer configured to detect a touch associated with an amount of pressure applied to the control surface at the at least one user control area and invoke a user control function associated with the at least one user control area responsive to the touch only if the amount of pressure exceeds a threshold amount.

Abstract: The disclosed embodiments relate to implementation of a trading system or trading system architecture having multiple transaction processors that execute financial transactions as well as scheduled tasks. The multiple transaction processors perform all actions independently of each other, but can be configured to execute the financial transactions or scheduled tasks in a controlled, coordinated, and/or synchronized manner based on time signal data augmented to the financial transactions or scheduled tasks by a transaction receiver/orderer.

Abstract: Technologies for distribution of a shared image include determining results of a first hash operation applied to a plurality of elements of an image of a software installation, determining results of the first hash operation applied to the plurality of contents of a client, comparing results of the first hash operation applied to the plurality of elements of the image with the results of the first hash operation applied to the plurality of contents of the client, determining that one or more of the plurality of elements of the image are unavailable on the client based on the comparison of the results of the first hash operation applied to the plurality of elements of the image with the results of the first hash operation applied to the plurality of contents of the client, and causing the transmission of the elements to the client.

Abstract: A method for data flow analysis, comprising: obtaining, by a processing circuitry, an execution trace of a software program; dividing, by the processing circuitry, the execution trace into a plurality of sections; generating a plurality of definition-and-usage chains, at least some of the definition-and-usage chains being generated by different processors, at least some of the definition-and-usage chains being generated based on different sections of the execution trace, at least two of the definition-and-usage chains being generated in parallel with one another; combining, by the processing circuitry, the plurality of definition-and-usage chains to produce a data flow graph, the definition-and-usage chains being combined based on information provided by at least one of the processors that are used to generate the definition-and-usage chains, the information indicating one or more unresolved memory locations that are accessed by respective operations corresponding to one or more incomplete usage nodes in the

Abstract: Methods, apparatus, and system to optimize compilation of source code into vectorized compiled code, notwithstanding the presence of output dependencies which might otherwise preclude vectorization.

Abstract: The disclosed embodiments relate to implementation of a trading system or trading system architecture having multiple transaction processors that execute financial transactions as well as scheduled tasks. The multiple transaction processors perform all actions independently of each other, but can be configured to execute the financial transactions or scheduled tasks in a controlled, coordinated, and/or synchronized manner based on time signal data augmented to the financial transactions or scheduled tasks by a transaction receiver/orderer.

Abstract: Systems, methods, and apparatuses relating to conditional queues in a configurable spatial accelerator are described.

Abstract: A trace data capture device has trace storage circuitry for storing trace data captured from a data processing apparatus. Detection circuitry detects source identifiers identifying which trace source generated the trace data. Output circuitry outputs to a diagnostic apparatus, independently from the trace data, source identifying data which indicates which source identifiers were detected for the trace data stored in at least a portion of the trace storage circuitry. By allowing the diagnostic apparatus to determine which source identifiers have been detected for which region of the memory, this can allow more targeted uploads of trace data, to reduce the time required for uploading the trace data and reduce the time to determine if data is not present for a particular source.

Abstract: User devices are used to access data ranging from calendar items to Internet searches. An instant unified search interface provided by a unified search helper module enables a user of the user device to search data associated with one or more applications across applications on the user device as well as data in remote locations, such as on a server via a network connection. The unified search helper module may be provided as part of the operating system module. In some implementations, entry of particular keys using a keyboard coupled to the user device may initiate the instant unified search. The keyboard may be a physical keyboard or a virtual keyboard.

Abstract: Providing dataflow analysis by selecting a plurality of sampling points from a program under examination. A set of respective values is recorded from a corresponding set of memory registers at each of the plurality of sampling points. The set of respective values comprises at least a first set of values stored in a first set of memory registers for a first sampling point of the plurality of sampling points, and a second set of values stored in a second set of memory registers for a second sampling point of the plurality of sampling points. A correlation is performed between the first set of values and the second set of values to retrieve dataflow information from the program under examination.

Abstract: Injury to the digits, hand and wrist are associated with the frequent usage of portable hand-held electronic devices (“PEDs”), including but not limited to smartphones. This is true as well for injury to the neck and shoulder areas. The potential for injury to the digits, hand and wrist in particular is anticipated to be exacerbated by the larger smartphones, and especially the tablet-like smartphones. The ergonomic accessory of the invention has several embodiments whose design is intended to ameliorate if not prevent such injuries. Certain embodiments are partially or fully case-like in form so that they envelope to a greater or lesser degree, such hand-held electronic devices. Another embodiment attaches to a PED through an element of the PED such as the charging socket. The accessory also removably attaches the hand of the user or provides a secure holding surface for the user.

Abstract: In one example in accordance with the present disclosure, a system may include a processor and a memory comprising instructions executable by the processor to generate a plurality of visual indicators on a flow graph. Each of the visual indicators may correspond to one of a plurality of functions performed during execution of software code. The memory may comprise instructions executable by the processor to generate, a connector to visually link a first visual indicator, corresponding to a first function, to a second visual indicator, corresponding to a second function. The memory may comprise instructions executable by the processor to generate a tail attached to the first visual indicator, a dimension of the tail corresponding to a duration of the first function before the first function call.

Abstract: A control graph representing a model of data flow of a computer program can be generated during a static analysis. Respective edge weights can be assigned to edges of a plurality of paths in the control flow graph. A size of the uniform-cost search method can be dynamically configured based on a size of the control flow graph. A total edge weight for the considered paths can be determined based the edge weights assigned to the respective edges of the considered path. At least one path of the considered paths in the control flow graph whose total edge weight satisfies a particular total edge weight criteria can be identified. The control flow graph can be updated to indicate to a user the at least one path in the control flow graph whose total edge weight satisfies the particular total edge weight criteria.

Abstract: An execution trace of an application program comprises a sequence of ordered programming instructions generated during execution of the application program indicating an execution flow of the application program. The sequence of ordered programming instructions is partitioned into a plurality of linked code segments comprising first and second code segments. The first code segment comprises a terminating programming instruction that terminates the first code segment and links the first code segment to an initial programming instruction of the second code segment. A directed graph representing the execution flow of the application program between the plurality of linked code segments is generated. The directed graph comprises a plurality of linked nodes representing the plurality of linked code segments. The directed graph is output to a graphical user interface (GUI) for display.

Abstract: Examples may include techniques to a schedule a workload to one or more computing resources of a data center. A class is determined for the workload based on a workload type or profile for the workload. Predicted operating values for at least one of the one or more computing resources is determined based on the class and the predicted operating values are used as inputs in at least one scoring model to evaluate the workload being supported by the at least one of the one or more computing resources. The workload is then scheduled to the at least one or more computing resources based on the evaluation.

Abstract: The invention discloses an analysis system and method for reducing control flow divergence in the Graphics Processing Units (GPUs). A computing unit is used to count the number of branch, number of cycle, and to calculate at least one direction ratio. A profiler is used to determine whether the code having the optimized control flow structure and the specialized branch or not. The optimization decision unit can determine which transform pattern can be used to transform the sub-control flow structure.

Abstract: Inventive aspects include a key value store engine including non-volatile memory configured to store key-value inode descriptors each including a key and an associated value. The key value store engine can include a volatile memory to store a key hash tree and a collision hash tree. The key hash tree can include nodes each having a hash of one of the keys. The collision hash tree can include nodes each having a collided hash associated with two or more different keys. Each of the nodes of the key hash tree can include a collision flag indicating whether two or more different hashes correspond to a collided hash. The volatile memory can store a collision linked list including linked list nodes each having a key-value inode number indicating a location of a corresponding key-value inode descriptor stored in the non-volatile memory. The key value store engine can include a key value logic section.

Abstract: A network device and method for packet processing are provided. A packet processing accelerator is configured to receive packets from a network and define for ones of the packets a data unit corresponding to the packet. The packet processing accelerator is configured to perform a first set of packet processing operations on the data unit. A central processing unit (CPU) is configured to perform a second set of packet processing operations on the data unit. A buffer is configured to pass data units from the packet processing accelerator to the CPU, and vice versa, where the buffer is configured to store data units in one or more lines of the buffer. Dummy data units fill a space in a buffer line that is not occupied by a data unit, and the dummy data units include an indication that the space occupied by the dummy data units is an empty space.

Abstract: A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted in the global memory device. Memory access traces relating to executed tasks are accessed from the signal list. Memory locations accessed in the global memory device from the access traces are identified. A correlation value for each pair of memory locations accessed in the global memory device is determined. Correlation values of the pairs of memory locations are determined, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations. Accessed memory locations within the global memory device are reordered as a function of the determined correlation values. An executable file accessing the global memory device is modified.

Abstract: Embodiments relate to program structure-based blocking. An aspect includes receiving source code corresponding to a computer program by a compiler of a computer system. Another aspect includes determining a prefetching section in the source code by a marking module of the compiler. Yet another aspect includes performing, by a blocking module of the compiler, blocking of instructions located in the prefetching section into instruction blocks, such that the instruction blocks of the prefetching section only contain instructions that are located in the prefetching section.

Abstract: A processor of an aspect includes a plurality of processor elements, and a first processor element. The first processor element may perform a user-level fork instruction of a software thread. The first processor element may include a decoder to decode the user-level fork instruction. The user-level fork instruction is to indicate at least one instruction address. The first processor element may also include a user-level thread fork module. The user-level fork module, in response to the user-level fork instruction being decoded, may configure each of the plurality of processor elements to perform instructions in parallel. Other processors, methods, systems, and instructions are disclosed.

Abstract: The software development tool (701) forms part of a software development kit (700). The software development tool (701) receives as input object files (606) and library files (607) and subjects the object file instructions and data definitions of the object files and the library files to re-sequencing to generate new object files and the links between them which are semantically equivalent to the input object files and library files and which are used to generate an optimized executable. The software development tool (701) is capable of automatically generating an executable, without requiring any modification of the source code, which is optimized to execute more deterministically and with respect to execution time; reduced processor and memory requirements; reduced off-chip memory accesses; reduced memory latency.

Abstract: A method and apparatus for automatic generation of a device program including determining a controller from among a plurality of controllers displayed in a graphical user interface (GUI) on a user device communicatively coupled to a corresponding external controller, generating a user interactive pin layout in the GUI for the controller, displaying in the GUI, a plurality of operations for execution by the controller, determining an operation from among the plurality of operations for the controller, associating pins selected to parameters of the operation, receiving parameter data for the operation from at least one data entry field in the GUI, generating a program for the controller based on the user interactive pin layout, the received parameter data, the operation, and sending the program for storage in a memory on the controller, wherein at least one determined operation comprises communicating data with an external data service.

Abstract: Systems and methods may provide refactoring data flow applications without source code changes or recompilation. An apparatus may create a map file that describes how an original graph structure and node properties are mapped to a new structure and set of properties. A runtime system aware of the mapping may transform a graph that is constructed by the data flow application into the new structure at runtime.

Abstract: A computer processor including a plurality of storage elements logically organized as a fixed length queue referenced by logical temporal addresses. The fixed length queue operates over multiple cycles to temporarily store operands referenced by at least one instruction utilizing the logical temporal addresses. A plurality of functional units performs operations over the multiple cycles, wherein the operations produce and access operands stored in the logical fixed length queue. Operands can be added to the front of the logical fixed length queue according to the temporal order that operands are produced by the functional units, and operands can drop from the end of the logical fixed length queue as operands are added to the front of the fixed length queue. A plurality of operands produced by the plurality of functional units (possibly with different latencies in producing such operands) can be added to the logical fixed length queue in a single cycle.

Abstract: A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. The processor allocates a memory region for the purpose of creating “random branches” in the computer code utilizing existing memory access instructions. When the processor processes a given instruction, the processor both accesses a first location in the memory region and may determine a condition is satisfied. In response, the processor generates an interrupt. The corresponding interrupt handler may transfer control flow from the computer program to instrumentation code. The condition may include a pointer storing an address pointing to locations within the memory region equals a given address after the point is updated. Alternatively, the condition may include an updated data value stored in a location pointed to by the given address equals a threshold value.

Abstract: A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. When the processor processes a given instruction of a given instruction type, the processor updates a corresponding performance counter. When the performance counter reaches a threshold, the processor generates an interrupt and compares a location of the given instruction with stored locations in a given list. If a match is not found, then the processor processes an instruction following the given instruction in the computer program without processing intermediate instrumentation code. If a match is found, then the processor processes instrumentation code. Regardless of whether or not the instrumentation code is processed, when control flow returns to the computer program, the corresponding performance counter is initialized with a random value.

Abstract: An electronic device includes a semiconductor memory unit that includes a vertical electrode formed over a substrate and receiving a voltage through one end of the vertical electrode, a resistance variable layer formed along a side of the vertical electrode to be thinner going from one end to the other end, and a plurality of horizontal electrodes formed adjacent to the vertical electrode with the resistance variable layer disposed between the horizontal electrodes and the vertical electrode, and stacked over the substrate with a space from each other.

Abstract: An apparatus includes a plurality of processing modules which are connected to each other by corresponding communication unit and the modules transfer packets in a predetermined direction to execute a plurality of operations of pipeline processing. The module includes a storage unit for storing a first identification and a second identification for each of the plurality of operations, a reception unit for extracting data from a packet which has the first identification, a processing unit for processing the data extracted by the reception unit, and a transmission unit for storing the second identification corresponding to the first identification of the packet a packet and transmitting the packet to the module arranged in the predetermined direction.

Abstract: According to one embodiment of the present invention, a system selectively compresses data fields in a parallel data flow. The system identifies within an execution plan for the parallel data flow a first instance of a data field within a stage of the parallel data flow. The system traces the identified data field through stages of the parallel data flow and determines a score value for the identified data field based on operations performed on the identified data field during traversal of the stages. The system compresses the identified data field based on the score value indicating a performance gain with respect to the compressed data field. Embodiments of the present invention further include a method and computer program product for selectively compressing data fields in a parallel data flow in substantially the same manners described above.

Abstract: A method includes supplying a video stream to a primary display device, detecting an information request associated with the video stream, identifying a portion of the video stream corresponding to the time of detecting, supplying to a secondary display device choices corresponding to the information request, receiving selected choices and supplying to the secondary display device information corresponding to the selected choices.

Abstract: A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when executed by the processor, is configured to receive source code and translate the source code to a low-level language. The source code is restricted to a subset of a high-level language and the low-level language is a specialized instruction set. Each statement of the subset of the high-level language directly maps to an instruction of the low-level language.

Abstract: An Asset Health Management system monitors and analyzes the health of a component of an asset. A sensor network, with one or more sensors operably coupled to an asset component, collects sensor data associated with operating characteristics of the asset component. A processing node (a System Health Node) includes one or more modules, i.e., software functions, and one or more configuration files. The processing node processes the sensor data with the one or more modules according to the one or more configuration files and determines health information corresponding to the asset component. The one or more modules receive and transmit input and output data, respectively, via data streams that organize the input and output data, e.g., according to time stamps and that may be cached. The health information may be displayed on user interfaces and/or may be transmitted over an information network to external systems.