Data Flow Based System Patents (Class 712/201)
  • Patent number: 11126418
    Abstract: Technologies for distribution of a shared image include determining results of a first hash operation applied to a plurality of elements of an image of a software installation, determining results of the first hash operation applied to the plurality of contents of a client, comparing results of the first hash operation applied to the plurality of elements of the image with the results of the first hash operation applied to the plurality of contents of the client, determining that one or more of the plurality of elements of the image are unavailable on the client based on the comparison of the results of the first hash operation applied to the plurality of elements of the image with the results of the first hash operation applied to the plurality of contents of the client, and causing the transmission of the elements to the client.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 21, 2021
    Assignee: McAfee, LLC
    Inventor: Simon Hunt
  • Patent number: 10891216
    Abstract: A method for data flow analysis, comprising: obtaining, by a processing circuitry, an execution trace of a software program; dividing, by the processing circuitry, the execution trace into a plurality of sections; generating a plurality of definition-and-usage chains, at least some of the definition-and-usage chains being generated by different processors, at least some of the definition-and-usage chains being generated based on different sections of the execution trace, at least two of the definition-and-usage chains being generated in parallel with one another; combining, by the processing circuitry, the plurality of definition-and-usage chains to produce a data flow graph, the definition-and-usage chains being combined based on information provided by at least one of the processors that are used to generate the definition-and-usage chains, the information indicating one or more unresolved memory locations that are accessed by respective operations corresponding to one or more incomplete usage nodes in the
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 12, 2021
    Assignee: Raytheon Company
    Inventor: Andrew Calvano
  • Patent number: 10776093
    Abstract: Methods, apparatus, and system to optimize compilation of source code into vectorized compiled code, notwithstanding the presence of output dependencies which might otherwise preclude vectorization.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Mikhail Plotnikov, Hideki Ido, Xinmin Tian, Sergey Preis, Milind B. Girkar, Maxim Shutov
  • Patent number: 10748210
    Abstract: The disclosed embodiments relate to implementation of a trading system or trading system architecture having multiple transaction processors that execute financial transactions as well as scheduled tasks. The multiple transaction processors perform all actions independently of each other, but can be configured to execute the financial transactions or scheduled tasks in a controlled, coordinated, and/or synchronized manner based on time signal data augmented to the financial transactions or scheduled tasks by a transaction receiver/orderer.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: August 18, 2020
    Assignee: Chicago Mercantile Exchange Inc.
    Inventors: Zachary Bonig, Eric Thill, Pearce Peck-Walden, José Antonio Acuña-Rohter, Barry Galster, Neil Steuber, James Bailey, Jake Siddall
  • Patent number: 10564980
    Abstract: Systems, methods, and apparatuses relating to conditional queues in a configurable spatial accelerator are described.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: February 18, 2020
    Assignee: INTEL CORPORATION
    Inventors: Kermin E. Fleming, Jr., Ping Zou, Mitchell Diamond, Benjamin Keen
  • Patent number: 10452513
    Abstract: A trace data capture device has trace storage circuitry for storing trace data captured from a data processing apparatus. Detection circuitry detects source identifiers identifying which trace source generated the trace data. Output circuitry outputs to a diagnostic apparatus, independently from the trace data, source identifying data which indicates which source identifiers were detected for the trace data stored in at least a portion of the trace storage circuitry. By allowing the diagnostic apparatus to determine which source identifiers have been detected for which region of the memory, this can allow more targeted uploads of trace data, to reduce the time required for uploading the trace data and reduce the time to determine if data is not present for a particular source.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 22, 2019
    Assignee: ARM Limited
    Inventors: Dennis Stephen Cook, Anthony Russell Armitstead, Michael Paul Darling
  • Patent number: 10445314
    Abstract: User devices are used to access data ranging from calendar items to Internet searches. An instant unified search interface provided by a unified search helper module enables a user of the user device to search data associated with one or more applications across applications on the user device as well as data in remote locations, such as on a server via a network connection. The unified search helper module may be provided as part of the operating system module. In some implementations, entry of particular keys using a keyboard coupled to the user device may initiate the instant unified search. The keyboard may be a physical keyboard or a virtual keyboard.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: October 15, 2019
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Arunachalam Sundararaman, Babu Durairaj, Nakul Srivathsa, Rinosh Sasidharan, Kevin Terry Burkhart, Peter John Thomas Johnson
  • Patent number: 10289540
    Abstract: Providing dataflow analysis by selecting a plurality of sampling points from a program under examination. A set of respective values is recorded from a corresponding set of memory registers at each of the plurality of sampling points. The set of respective values comprises at least a first set of values stored in a first set of memory registers for a first sampling point of the plurality of sampling points, and a second set of values stored in a second set of memory registers for a second sampling point of the plurality of sampling points. A correlation is performed between the first set of values and the second set of values to retrieve dataflow information from the program under examination.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Pietro Ferrara, Marco Pistoia, Omer Tripp
  • Patent number: 10277724
    Abstract: Injury to the digits, hand and wrist are associated with the frequent usage of portable hand-held electronic devices (“PEDs”), including but not limited to smartphones. This is true as well for injury to the neck and shoulder areas. The potential for injury to the digits, hand and wrist in particular is anticipated to be exacerbated by the larger smartphones, and especially the tablet-like smartphones. The ergonomic accessory of the invention has several embodiments whose design is intended to ameliorate if not prevent such injuries. Certain embodiments are partially or fully case-like in form so that they envelope to a greater or lesser degree, such hand-held electronic devices. Another embodiment attaches to a PED through an element of the PED such as the charging socket. The accessory also removably attaches the hand of the user or provides a secure holding surface for the user.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: April 30, 2019
    Inventors: Peter M. Roncetti, Robert S. Gluck
  • Patent number: 10261886
    Abstract: In one example in accordance with the present disclosure, a system may include a processor and a memory comprising instructions executable by the processor to generate a plurality of visual indicators on a flow graph. Each of the visual indicators may correspond to one of a plurality of functions performed during execution of software code. The memory may comprise instructions executable by the processor to generate, a connector to visually link a first visual indicator, corresponding to a first function, to a second visual indicator, corresponding to a second function. The memory may comprise instructions executable by the processor to generate a tail attached to the first visual indicator, a dimension of the tail corresponding to a duration of the first function before the first function call.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: April 16, 2019
    Assignee: ENTIT SOFTWARE LLC
    Inventor: Jonatan Amir
  • Patent number: 10133870
    Abstract: A control graph representing a model of data flow of a computer program can be generated during a static analysis. Respective edge weights can be assigned to edges of a plurality of paths in the control flow graph. A size of the uniform-cost search method can be dynamically configured based on a size of the control flow graph. A total edge weight for the considered paths can be determined based the edge weights assigned to the respective edges of the considered path. At least one path of the considered paths in the control flow graph whose total edge weight satisfies a particular total edge weight criteria can be identified. The control flow graph can be updated to indicate to a user the at least one path in the control flow graph whose total edge weight satisfies the particular total edge weight criteria.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Omer Tripp
  • Patent number: 10067853
    Abstract: An execution trace of an application program comprises a sequence of ordered programming instructions generated during execution of the application program indicating an execution flow of the application program. The sequence of ordered programming instructions is partitioned into a plurality of linked code segments comprising first and second code segments. The first code segment comprises a terminating programming instruction that terminates the first code segment and links the first code segment to an initial programming instruction of the second code segment. A directed graph representing the execution flow of the application program between the plurality of linked code segments is generated. The directed graph comprises a plurality of linked nodes representing the plurality of linked code segments. The directed graph is output to a graphical user interface (GUI) for display.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: September 4, 2018
    Assignee: CA, Inc.
    Inventor: Munish Kumar
  • Patent number: 9959146
    Abstract: Examples may include techniques to a schedule a workload to one or more computing resources of a data center. A class is determined for the workload based on a workload type or profile for the workload. Predicted operating values for at least one of the one or more computing resources is determined based on the class and the predicted operating values are used as inputs in at least one scoring model to evaluate the workload being supported by the at least one of the one or more computing resources. The workload is then scheduled to the at least one or more computing resources based on the evaluation.
    Type: Grant
    Filed: April 2, 2016
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventors: Nishi Ahuja, Rahul Khanna, Abishai Daniel, Diyong Fu
  • Patent number: 9870599
    Abstract: The invention discloses an analysis system and method for reducing control flow divergence in the Graphics Processing Units (GPUs). A computing unit is used to count the number of branch, number of cycle, and to calculate at least one direction ratio. A profiler is used to determine whether the code having the optimized control flow structure and the specialized branch or not. The optimization decision unit can determine which transform pattern can be used to transform the sub-control flow structure.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: January 16, 2018
    Assignees: NATIONAL TAIWAN UNIVERSITY, MEDIATEK INC.
    Inventors: Che-Yang Wu, Wei-Chung Hsu
  • Patent number: 9846642
    Abstract: Inventive aspects include a key value store engine including non-volatile memory configured to store key-value inode descriptors each including a key and an associated value. The key value store engine can include a volatile memory to store a key hash tree and a collision hash tree. The key hash tree can include nodes each having a hash of one of the keys. The collision hash tree can include nodes each having a collided hash associated with two or more different keys. Each of the nodes of the key hash tree can include a collision flag indicating whether two or more different hashes correspond to a collided hash. The volatile memory can store a collision linked list including linked list nodes each having a key-value inode number indicating a location of a corresponding key-value inode descriptor stored in the non-volatile memory. The key value store engine can include a key value logic section.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: December 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changho Choi, Taeil Um
  • Patent number: 9838500
    Abstract: A network device and method for packet processing are provided. A packet processing accelerator is configured to receive packets from a network and define for ones of the packets a data unit corresponding to the packet. The packet processing accelerator is configured to perform a first set of packet processing operations on the data unit. A central processing unit (CPU) is configured to perform a second set of packet processing operations on the data unit. A buffer is configured to pass data units from the packet processing accelerator to the CPU, and vice versa, where the buffer is configured to store data units in one or more lines of the buffer. Dummy data units fill a space in a buffer line that is not occupied by a data unit, and the dummy data units include an indication that the space occupied by the dummy data units is an empty space.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: December 5, 2017
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Dan Ilan, Uri Dayan
  • Patent number: 9830270
    Abstract: A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted in the global memory device. Memory access traces relating to executed tasks are accessed from the signal list. Memory locations accessed in the global memory device from the access traces are identified. A correlation value for each pair of memory locations accessed in the global memory device is determined. Correlation values of the pairs of memory locations are determined, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations. Accessed memory locations within the global memory device are reordered as a function of the determined correlation values. An executable file accessing the global memory device is modified.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: November 28, 2017
    Assignee: GM Global Technology Operations LLC
    Inventors: Shuqing Zeng, Shige Wang, Stephen G. Lusko
  • Patent number: 9772825
    Abstract: Embodiments relate to program structure-based blocking. An aspect includes receiving source code corresponding to a computer program by a compiler of a computer system. Another aspect includes determining a prefetching section in the source code by a marking module of the compiler. Yet another aspect includes performing, by a blocking module of the compiler, blocking of instructions located in the prefetching section into instruction blocks, such that the instruction blocks of the prefetching section only contain instructions that are located in the prefetching section.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Carlo Bertolli, Alexandre E. Eichenberger, John K. O'Brien, Zehra N. Sura
  • Patent number: 9747108
    Abstract: A processor of an aspect includes a plurality of processor elements, and a first processor element. The first processor element may perform a user-level fork instruction of a software thread. The first processor element may include a decoder to decode the user-level fork instruction. The user-level fork instruction is to indicate at least one instruction address. The first processor element may also include a user-level thread fork module. The user-level fork module, in response to the user-level fork instruction being decoded, may configure each of the plurality of processor elements to perform instructions in parallel. Other processors, methods, systems, and instructions are disclosed.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: August 29, 2017
    Assignee: Intel Corporation
    Inventors: Oren Ben-Kiki, Ilan Pardo, Arch D. Robison, James H. Cownie
  • Patent number: 9696966
    Abstract: The software development tool (701) forms part of a software development kit (700). The software development tool (701) receives as input object files (606) and library files (607) and subjects the object file instructions and data definitions of the object files and the library files to re-sequencing to generate new object files and the links between them which are semantically equivalent to the input object files and library files and which are used to generate an optimized executable. The software development tool (701) is capable of automatically generating an executable, without requiring any modification of the source code, which is optimized to execute more deterministically and with respect to execution time; reduced processor and memory requirements; reduced off-chip memory accesses; reduced memory latency.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: July 4, 2017
    Assignee: Somnium Technologies Limited
    Inventors: David Alan Edwards, Martin Charles Young
  • Patent number: 9619122
    Abstract: A method and apparatus for automatic generation of a device program including determining a controller from among a plurality of controllers displayed in a graphical user interface (GUI) on a user device communicatively coupled to a corresponding external controller, generating a user interactive pin layout in the GUI for the controller, displaying in the GUI, a plurality of operations for execution by the controller, determining an operation from among the plurality of operations for the controller, associating pins selected to parameters of the operation, receiving parameter data for the operation from at least one data entry field in the GUI, generating a program for the controller based on the user interactive pin layout, the received parameter data, the operation, and sending the program for storage in a memory on the controller, wherein at least one determined operation comprises communicating data with an external data service.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: April 11, 2017
    Assignee: Ciambella Ltd.
    Inventors: Trisala Chandaria, Jean-Baptiste Leonelli
  • Patent number: 9529587
    Abstract: Systems and methods may provide refactoring data flow applications without source code changes or recompilation. An apparatus may create a map file that describes how an original graph structure and node properties are mapped to a new structure and set of properties. A runtime system aware of the mapping may transform a graph that is constructed by the data flow application into the new structure at runtime.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Michael J. Voss, Vasanth R. Tovinkere, Jaime Arteaga, Sergey Vinogradov
  • Patent number: 9513921
    Abstract: A computer processor including a plurality of storage elements logically organized as a fixed length queue referenced by logical temporal addresses. The fixed length queue operates over multiple cycles to temporarily store operands referenced by at least one instruction utilizing the logical temporal addresses. A plurality of functional units performs operations over the multiple cycles, wherein the operations produce and access operands stored in the logical fixed length queue. Operands can be added to the front of the logical fixed length queue according to the temporal order that operands are produced by the functional units, and operands can drop from the end of the logical fixed length queue as operands are added to the front of the fixed length queue. A plurality of operands produced by the plurality of functional units (possibly with different latencies in producing such operands) can be added to the logical fixed length queue in a single cycle.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: December 6, 2016
    Assignee: Mill Computing, Inc.
    Inventors: Roger Rawson Godard, Arthur David Kahlich, Sebastien Paul Maurice Mirolo, David Arthur Yost
  • Patent number: 9483379
    Abstract: A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. The processor allocates a memory region for the purpose of creating “random branches” in the computer code utilizing existing memory access instructions. When the processor processes a given instruction, the processor both accesses a first location in the memory region and may determine a condition is satisfied. In response, the processor generates an interrupt. The corresponding interrupt handler may transfer control flow from the computer program to instrumentation code. The condition may include a pointer storing an address pointing to locations within the memory region equals a given address after the point is updated. Alternatively, the condition may include an updated data value stored in a location pointed to by the given address equals a threshold value.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: November 1, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph L. Greathouse, David S. Christie
  • Patent number: 9448909
    Abstract: A system and method for efficiently performing program instrumentation. A processor processes instructions stored in a memory. When the processor processes a given instruction of a given instruction type, the processor updates a corresponding performance counter. When the performance counter reaches a threshold, the processor generates an interrupt and compares a location of the given instruction with stored locations in a given list. If a match is not found, then the processor processes an instruction following the given instruction in the computer program without processing intermediate instrumentation code. If a match is found, then the processor processes instrumentation code. Regardless of whether or not the instrumentation code is processed, when control flow returns to the computer program, the corresponding performance counter is initialized with a random value.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: September 20, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph L. Greathouse, David S. Christie
  • Patent number: 9246095
    Abstract: An electronic device includes a semiconductor memory unit that includes a vertical electrode formed over a substrate and receiving a voltage through one end of the vertical electrode, a resistance variable layer formed along a side of the vertical electrode to be thinner going from one end to the other end, and a plurality of horizontal electrodes formed adjacent to the vertical electrode with the resistance variable layer disposed between the horizontal electrodes and the vertical electrode, and stacked over the substrate with a space from each other.
    Type: Grant
    Filed: May 17, 2014
    Date of Patent: January 26, 2016
    Assignee: SK HYNIX INC.
    Inventor: Kwang-Hee Cho
  • Patent number: 9152605
    Abstract: An apparatus includes a plurality of processing modules which are connected to each other by corresponding communication unit and the modules transfer packets in a predetermined direction to execute a plurality of operations of pipeline processing. The module includes a storage unit for storing a first identification and a second identification for each of the plurality of operations, a reception unit for extracting data from a packet which has the first identification, a processing unit for processing the data extracted by the reception unit, and a transmission unit for storing the second identification corresponding to the first identification of the packet a packet and transmitting the packet to the module arranged in the predetermined direction.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: October 6, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hisashi Ishikawa
  • Patent number: 9143161
    Abstract: According to one embodiment of the present invention, a system selectively compresses data fields in a parallel data flow. The system identifies within an execution plan for the parallel data flow a first instance of a data field within a stage of the parallel data flow. The system traces the identified data field through stages of the parallel data flow and determines a score value for the identified data field based on operations performed on the identified data field during traversal of the stages. The system compresses the identified data field based on the score value indicating a performance gain with respect to the compressed data field. Embodiments of the present invention further include a method and computer program product for selectively compressing data fields in a parallel data flow in substantially the same manners described above.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: September 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Greene, Eric A. Jacobson, Yong Li, Xiaoyan Pu
  • Patent number: 9137578
    Abstract: A method includes supplying a video stream to a primary display device, detecting an information request associated with the video stream, identifying a portion of the video stream corresponding to the time of detecting, supplying to a secondary display device choices corresponding to the information request, receiving selected choices and supplying to the secondary display device information corresponding to the selected choices.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 15, 2015
    Assignee: Roku, Inc.
    Inventor: Greg Garner
  • Patent number: 9092228
    Abstract: A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when executed by the processor, is configured to receive source code and translate the source code to a low-level language. The source code is restricted to a subset of a high-level language and the low-level language is a specialized instruction set. Each statement of the subset of the high-level language directly maps to an instruction of the low-level language.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: July 28, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alan L. Davis, Ching-Yu Hung, Jadadeesh Sankaran, James Nagurne, Mel Alan Phipps, Ajay Jayaraj
  • Patent number: 9043380
    Abstract: A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: May 26, 2015
    Assignee: Solarflare Communications, Inc.
    Inventors: Steven Leslie Pope, Derek Edward Roberts, David James Riddoch, Greg Law, Steve Grantham, Matthew Slattery
  • Patent number: 9026768
    Abstract: A computing machine is disclosed having a memory system for storing a collection of execution nodes, a head for reading a sequence of symbols in the execution nodes in the memory system, and writing a sequence of symbols in the memory system. The machine is configured to execute a computation with a collection of pairs of execution nodes. Each pair of execution nodes represents a machine instruction. One execution node in the pair represents input of the machine instruction represented by the execution nodes. Another execution node in the pair represents output of the machine instruction represented by the execution nodes. Each execution node has a state of the machine, a sequence of symbols and a number.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: May 5, 2015
    Assignee: Aemea Inc.
    Inventor: Michael Stephen Fiske
  • Patent number: 9015352
    Abstract: The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 21, 2015
    Assignee: Altera Corporation
    Inventor: Amit Ramchandran
  • Patent number: 9015622
    Abstract: Some embodiments of a system and a method to tune a computing system based on a profile have been presented. A profile as used herein broadly refers to a file containing various parameters of a computing system, such as kernel parameters (e.g., buffer size, network setup, etc.), usable to configure the computing system. For instance, a set of profiles are stored in a computer-readable storage device in a computing system, such as a server, a personal computer, a laptop computer, etc. A processing device miming on the computing system may receive a user selection of one of the set of profiles. In response to the user selection, the processing device may load the selected profile onto the computing system in order to tune the computing system according to the selected profile.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: April 21, 2015
    Assignee: Red Hat, Inc.
    Inventors: Thomas K. Wörner, Christopher Haughey Snook
  • Publication number: 20150074376
    Abstract: Embodiments are provided for an asynchronous processor using master and assisted tokens. In an embodiment, an apparatus for an asynchronous processor comprises a memory to cache a plurality of instructions, a feedback engine to decode the instructions from the memory, and a plurality of XUs coupled to the feedback engine and arranged in a token ring architecture. Each one of the XUs is configured to receive an instruction of the instructions form the feedback engine, and receive a master token associated with a resource and further receive an assisted token for the master token. Upon determining that the assisted token and the master token are received in an abnormal order, the XU is configured to detect an operation status for the instruction in association with the assisted token, and upon determining a needed action in accordance with the operation status and the assisted token, perform the needed action.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 12, 2015
    Inventors: Yiqun Ge, Wuxian Shi, Qifan Zhang, Tao Huang, Wen Tong
  • Patent number: 8972769
    Abstract: A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the plurality of processing units when the operation clocks of a common frequency are supplied to the plurality of processing units, and to control a frequency of the operation clocks to be supplied to at least one of the plurality of processing units so that a plurality of measured response times become closer to each other.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: March 3, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akio Nakagawa, Hisashi Ishikawa
  • Patent number: 8959304
    Abstract: A data processing apparatus comprises a primary processor, a secondary processor configured to perform secure data processing operations and non-secure data processing operations and a memory configured to store secure data used by the secondary processor when performing the secure data processing operations and configured to store non-secure data used by the secondary processor when performing the non-secure data processing operations, wherein the secure data cannot be accessed by the non-secure data processing operations, wherein the secondary processor comprises a memory management unit configured to administer accesses to the memory from the secondary processor, the memory management unit configured to perform translations between virtual memory addresses used by the secondary processor and physical memory addresses used by the memory, wherein the translations are configured in dependence on a page table base address, the page table base address identifying a storage location in the memory of a set of des
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: February 17, 2015
    Assignee: ARM Limited
    Inventors: Dominic Hugo Symes, Ola Hugosson, Donald Felton, Sean Tristram Ellis
  • Patent number: 8843928
    Abstract: A method and system of efficient use and programming of a multi-processing core device. The system includes a programming construct that is based on stream-domain code. A programmable core based computing device is disclosed. The computing device includes a plurality of processing cores coupled to each other. A memory stores stream-domain code including a stream defining a stream destination module and a stream source module. The stream source module places data values in the stream and the stream conveys data values from the stream source module to the stream destination module. A runtime system detects when the data values are available to the stream destination module and schedules the stream destination module for execution on one of the plurality of processing cores.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: September 23, 2014
    Assignee: QST Holdings, LLC
    Inventors: Paul Master, Frederick Furtek
  • Patent number: 8826286
    Abstract: The present invention relates to the field of enterprise network computing. In particular, it relates to monitoring workload of a workload scheduler. Information defining a plurality of test jobs of low priority is received. The test jobs have respective launch times, and are launched for execution in a data processing system in accordance with said launch times and said low execution priority. The number of test jobs executed within a pre-defined analysis time range is determined A performance decrease warning is issued if the number of executed test jobs is lower than a predetermined threshold number. A workload scheduler discards launching of jobs having a low priority when estimating that a volume of jobs submitted with higher priority is sufficient to keep said scheduling system busy.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventor: Sergej Boris
  • Publication number: 20140181472
    Abstract: A method and apparatus for providing a scalable compute fabricare provided herein. The method includes determining a workflow for processing by the scalable compute fabric, wherein the workflow is based on an instruction set. A pipeline in configured dynamically for processing the workflow, and the workflow is executed using the pipeline.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Scott Krig, Teresa Morrison
  • Patent number: 8706916
    Abstract: The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: April 22, 2014
    Assignee: Altera Corporation
    Inventor: Amit Ramchandran
  • Patent number: 8638805
    Abstract: Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules packets for transmission. The network processor generates tasks corresponding to each received packet associated with a data flow. A traffic manager receives tasks provided by one of the processing modules and determines a queue of the scheduling hierarchy corresponding to the task. The queue has a parent scheduler at each of one or more next levels of the scheduling hierarchy up to a root scheduler, forming a branch of the hierarchy. The traffic manager determines if the queue and one or more of the parent schedulers of the branch should be restructured. If so, the traffic manager drops subsequently received tasks for the branch, drains all tasks of the branch, and removes the corresponding nodes of the branch from the scheduling hierarchy.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: January 28, 2014
    Assignee: LSI Corporation
    Inventors: Balakrishnan Sundararaman, Shashank Nemawarkar, David Sonnier, Shailendra Aulakh, Allen Vestal
  • Publication number: 20140013080
    Abstract: A method and system are provided for deriving a resultant software code from an originating ordered list of instructions that does not include overlapping branch logic. The method may include deriving a plurality of unordered software constructs from a sequence of processor instructions; associating software constructs in accordance with an original logic of the sequence of processor instructions; determining and resolving memory precedence conflicts within the associated plurality of software constructs; resolving forward branch logic structures into conditional logic constructs; resolving back branch logic structures into loop logic constructs; and/or applying the plurality of unordered software constructs in a programming operation by a parallel execution logic circuitry. The resultant plurality of unordered software constructs may be converted into programming reconfigurable logic, computers or processors, and also by means of a computer network or an electronics communications network.
    Type: Application
    Filed: December 20, 2012
    Publication date: January 9, 2014
    Inventor: ROBERT KEITH MYKLAND
  • Publication number: 20140013081
    Abstract: An approach for processing data by a pipeline of a single hardware-implemented virtual multiple instance finite state machine (VMI FSM) is presented. Based on a current state and context of an FSM instance, an input token selected from multiple input tokens to enter a pipeline of the VMI FSM, and a status of an environment, a new state of the FSM instance is determined and an output token is determined. The input token includes a reference to the FSM instance. In one embodiment, the reference is an InfiniBand QP number. After a receipt by the pipeline of the first input token and prior to determining the new state of the FSM instance and determining the output token, a logic circuit selects a second input token to enter the pipeline. The second input token includes a reference to a second FSM instance.
    Type: Application
    Filed: September 9, 2013
    Publication date: January 9, 2014
    Applicant: International Business Machines Corporation
    Inventors: Rolf K. Fritz, Andreas Muller, Thomas Schlipf, Daniel Thiele
  • Patent number: 8612955
    Abstract: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: December 17, 2013
    Assignee: University of Washington
    Inventors: Mark H. Oskin, Steven J. Swanson, Susan J. Eggers
  • Publication number: 20130290674
    Abstract: Constructs may express SIMD control flow that can be efficiently implemented on a SIMD machine with support for SIMD control flow. The execution semantics of constructs serve as a functional specification for an emulation implementation in the central processing unit (CPU), a non-SIMD machine, using conventional C++ compiler such as GCC or Microsoft Visual C++ without any modification to the conventional compiler in some embodiments.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Inventors: Biju George, Guei-Yuan Luch
  • Publication number: 20130246737
    Abstract: Mechanisms, in a data processing system comprising a single instruction multiple data (SIMD) processor, for performing a data dependency check operation on vector element values of at least two input vector registers are provided. Two calls to a simd-check instruction are performed, one with input vector registers having a first order and one with the input vector registers having a different order. The simd-check instruction performs comparisons to determine if any data dependencies are present. Results of the two calls to the simd-check instruction are obtained and used to determine if any data dependencies are present in the at least two input vector registers. Based on the results, the SIMD processor may perform various operations.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: International Business Machines Corporation
    Inventors: Alexandre E. Eichenberger, Bruce M. Fleischer
  • Publication number: 20130080737
    Abstract: A vector data access unit includes data access ordering circuitry, for issuing data access requests indicated by the elements to the data store, and configured in response to receipt of at least two decoded vector data access instructions, and one of the instructions being a write instruction. Data accesses are performed in the instructed order to determine an element indicating the next data access for each of said vector data access instructions. One of the next data accesses is selected to be issued to the data store in dependence upon an order in which the at least two vector data instructions were received. The position of the elements indicates the next data accesses relative to each other within their respective plurality of elements. A numerical position of the element indicating the next data access within the plurality of elements of an earlier instruction is less than a predetermined value.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Applicant: ARM Limited
    Inventor: Alastair David Reid
  • Patent number: 8397186
    Abstract: A technique for reliably replaying operations in electronic-design-automation (EDA) software is described. In this technique, the EDA software stores operations performed by a user during a design session, as well as any replay look-ahead instructions, in a log file. When repeating the first operation, the replay look-ahead instruction ensures that the same state is obtained in the EDA environment as was previously obtained. For example, if an interrupt occurred when the first operation was previously performed, the replay look-ahead instruction may specify when the interrupt occurred during the performance of the operation so that the effect of the interrupt may be simulated when replaying the first operation.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: March 12, 2013
    Assignee: Synopsys, Inc.
    Inventor: Jeffrey T. Brubaker
  • Patent number: RE46993
    Abstract: An Asset Health Management system monitors and analyzes the health of a component of an asset. A sensor network, with one or more sensors operably coupled to an asset component, collects sensor data associated with operating characteristics of the asset component. A processing node (a System Health Node) includes one or more modules, i.e., software functions, and one or more configuration files. The processing node processes the sensor data with the one or more modules according to the one or more configuration files and determines health information corresponding to the asset component. The one or more modules receive and transmit input and output data, respectively, via data streams that organize the input and output data, e.g., according to time stamps and that may be cached. The health information may be displayed on user interfaces and/or may be transmitted over an information network to external systems.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: August 14, 2018
    Assignee: Vnomics Corp.
    Inventors: Jason Winnebeck, Michael G. Thurston, Christopher E. Piggott