Abstract: A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest ordered bit numbers having higher noise content and the highest ordered bit numbers having higher harmonic content. The system also comprises an encoder configured to arrange the plurality of digital data bits as serialized data sets to be transmitted over each of the plurality of data lines by the data transmitter with consecutive data bits of at least one serialized data set being matched such that bits with the higher harmonic content are matched with bits of the higher noise content to substantially mitigate of at least one of the noise content and the harmonic content of the data word.

Abstract: A system and method for retrieving information from a frame. A plurality of entries is initialized in a translation table. The translation table has a plurality of rows. Each of the plurality of rows represents a state. The rows have a plurality of entries. Each of the entries corresponds to a character. An indication of a current state is maintained and a frame is received. The frame includes a plurality of characters. A selected character from the frame is chosen. A translation row is selected in the translation table corresponding to the indication of the current state. An entry is located in the selected translation row in the translation table. The entry corresponds to the selected character. The character is translated. The translated character is stored in an output buffer.

Abstract: A system and method for parsing a data stream comprises a production rule table populated with production rules, a parser table populated with production rule codes that correspond to production rules within the production rule table, and a direct execution parser to identify production rule codes in the parser table and to retrieve production rules from the production rule table according to the identified production rule codes, the direct execution parser is operable to parse a data stream according to the retrieved production rules.

Abstract: A method, an apparatus, and computer instructions are provided for extending operations of an application in a data processing system. A primary operation is executed. All extended operations of the primary operation are cached and pre and post operation identifiers are identified. For each pre operation identifier, a pre operation instance is created and executed. For each post operation identifier, a post operation instance is created and executed.

Abstract: Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and receiving nodes each coupled by a communication channel. Individual communication channels operate at individually controllable clock speeds. Data messages sent between nodes pass at the speed of the communication channels. These data messages are sent by a sending port that includes registers for storing data and registers for protocol signals that control the timing and movement of the data. Data crosses clock boundaries without data loss. At least some of the microprocessors include fork functions that output a data stream to more than one output port. Similarly, at least some of the microprocessors include join functions that can create a single data stream from inputs from more than one input port.

Abstract: In a device and method for programming an industrial robot using a simulation program, control commands are issued by a handheld programming device and these commands are visualized on an image surface as movement and/or processing operations by the robot on the basis of data of the robot. An object to be processed is also displayed on the image surface and a three-dimensional image of the robot and the object is presented.

Abstract: Compression and decompression of data such as a sequential list of executable instructions (e.g., program binaries) by uniformly applying a predictive model generated from one segment of the executable list as a common predictive starting point for the other segments of the executable list. This permits random access and decompression of any segment of the executable list once a first segment (or another reference segment) of the executable list has been decompressed. This means that when executing an executable list (e.g., an executable file), a particular segment(s) of the executable list may not need to be accessed and decompressed at all if there are no instructions in that particular segment(s) that are executed.

Abstract: Methods and apparatus provide for performing pre-execution processes to prepare instructions of an instruction set for further processing; executing the instructions in a pipeline of execution stages using digital logic for processing data in accordance with the instructions within one clock cycle per stage; latching the data each clock cycle for delivery to a next execution stage using one or more of a plurality of latch point circuits; and controlling each of the latch point circuits to operate as a buffer or as a latch.

Abstract: Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI wireless framework. An identity of the acquired MMI event may be determined and the acquired MMI event may be dispatched to an event handler based on the determined identity of the acquired event. If the acquired MMI event comprises a timing event, the acquired MMI event may be dispatched to an MMI event owner within the MMI wireless framework. If the acquired MMI event comprises a keypad event, the acquired MMI event may be dispatched to a currently active MMI view within the MMI wireless framework. If the acquired MMI event comprises an addressed event, the acquired MMI event may be dispatched to a destination handler within the MMI wireless framework.

Abstract: A data-processing system and method include a processor core associated with a cache controller. A plurality of cached memory components is associated with the processor core and the cache controller. A cached processor is provided, which supports a plurality of varying sizes of instruction and data cache, wherein the cached processor comprises a processor core separated from the cache controller and the plurality of cached memory components, thereby permitted the cached processor to support varying sizes of cache memory in a flexible memory arrangement thereof.

Abstract: A method, system, and computer program product for providing a response to a user instruction in accordance with a process specified in a high level service description language. A method in accordance with an embodiment of the present invention includes: receiving at a multimodal engine a user instruction using one of at least two available modalities; transmitting the user instruction from the multimodal engine to a high level service description execution engine; executing the high level service description language with the high level service description execution engine to determine a response to the user instruction; and providing the response to the user through the multimodal engine.

Abstract: This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video source without an operating system. The method relates to operation of a microprocessor which is suitably arranged to carry out the steps of the method. The method includes details of operation of the specialized microprocessor.

Abstract: A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus includes a narrow cluster, a wide cluster, a steering logic utilizing a cluster predictor for providing a decoded instruction to either the narrow cluster or the wide cluster; address registers which are not part of the ISA, and a translation look-aside buffer for translating the virtual address of a load/store instruction in parallel with an execute stage. The method includes the steps of: predictably steering the instruction to either a W-bit Wide integer cluster or an N-bit Narrow integer cluster, managing the Address register file, and processing any instruction in the Wide integer cluster but processing only N-bit instructions in the Narrow integer cluster.

Abstract: In a data processing system a processor including processing logic performs data processing. An address translator that is coupled to the processing logic performs address translation and a method thereof. The address translator receives a logical address and converts the logical address to both a physical address and one or more address attributes. Bypass circuitry that is coupled to the address translator selectively provides the logical address as a translated address of the logical address which was received. In order to speed up the memory address translation, the logical address is selectively provided as the translated address prior to providing the one or more address attributes associated with the logical address.

Abstract: The present invention is directed to an RF communications system that includes a first radio processor module having a first receiver portion programmed to convert a first analog receive signal into a first digital audio receive signal. The first analog receive signal conforms to a first set of radio signal parameters. A digital interconnection system is coupled to the first radio processor module. At least one second radio processor module is coupled to the digital interconnection system. The at least one second radio processor module includes at least one second transmission portion programmed to obtain the first digital audio receive signal via the digital interconnection system and convert the first digital audio receive signal into at least one second analog transmit signal conforming to at least one set of second radio signal parameters.

Abstract: The present invention concerns data flow control in adaptive integrated circuitry which utilizes a data flow model for data processing. The present invention controls task initiation and execution based upon data consumption measured in data buffer units. In the various embodiments, when a first task of a plurality of tasks is initiated, buffer parameter is determined and a buffer count is initialized for the first task. For each iteration of the first task using a data buffer unit of input data, the buffer count is correspondingly adjusted, such as incremented or decremented. When the buffer count meets the buffer parameter requirements, the state of the first task is changed, which may including stopping the first task, and a next action is determined, such as initiating a second task. The various apparatus embodiments include a hardware task manager, a node sequencer, a programmable node, and use of a monitoring task within an adaptive execution unit.

Abstract: Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream they interrupt; it is known as “instruction cache washing,” since the instructions contained in the instruction cache prior to execution of the ISR are overwritten by the ISRs instructions. To reduce trashing of the instruction cache memory, the instruction cache is dynamically partitioned into a first memory portion and a second memory portion during execution. The first memory portion is for storing instructions of the current instruction stream, and the second memory portion is for storing instructions of the ISR. Thus, the ISR only affects the second memory portion and leaves instruction data stored within the first memory portion intact. This partitioning of the instruction cache reduces processor fetch operations as well as reduces power consumption of the instruction cache memory.

Abstract: An image transmission device and method, a transmitting device and method, a receiving device and method, and robot apparatus are capable of effectively transmitting the image data of multiple channels by using the existing systems which are formed on the premise of transmitting and receiving of the image data through single transmission line. At a transmitting side, the image data of multiple channels to be input is multiplexed with switching the channels by frame, and prescribed image information is added to each of the multiplexed image data of each frame. At a receiving side, the image information added to each of the image data for each frame respectively transmitted from the transmitting device are analyzed, and dividing device for dividing for each frame and outputting the multiplexed image data transmitted from the transmitting device to the corresponding channels is provided based on the analysis result.

Abstract: The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexer or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.

Abstract: A number of architectural and implementation approaches are described for using extra path (Epath) storage that operate in conjunction with a compute register file to obtain increased instruction level parallelism that more flexibly addresses the requirements of high performance algorithms. A processor that supports a single load data to a register file operation can be doubled in load capability through the use of an extra path storage, an additional independently addressable data memory path, and instruction decode information that specifies two independently load data operations. By allowing the extra path storage to be accessible by arithmetic facilities, the increased data bandwidth can be fully utilized.

Abstract: An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch it to the first fetch cue or the second fetch cue, and outputs a first fetch cue or a second fetch cue instruction to a decode circuit, a decode circuit which receives and decode an instruction code fetched to the first fetch cue or the second fetch cue, and an execution circuit performing execution of an instruction based on a decoding result, wherein the above-mentioned fetch circuit includes a selective circuit which selects which instruction of the first fetch cue or the second fetch cue to send to the decode circuit based on the execution result of a comparison instruction.

Abstract: The data processing device and electronic equipment of the present invention perform pipeline control and include a fetch circuit which fetches instruction codes of a plurality of instructions in instruction queues. A prefix instruction decoder circuit performs a decode processing only on a prefix instruction. The prefix instruction decoder circuit receives the instruction code before decoding, judges whether or not the instruction is a given prefix instruction, and causes a target instruction to modify an information register to store information necessary for decoding a target instruction when the instruction is the given prefix instruction. A decoder circuit receives each of the instruction codes of the instructions other than the prefix instruction as a decode instruction and decodes the decode instruction. When the decode instruction is a target instruction, the target instruction modified by the prefix instruction is decoded based on the target instruction modifying information.

Abstract: A receiver having an apparatus having a processor for processing interleaved data; and an independent memory coupled to the processor for processing the interleaved data is provided.

Abstract: A programmable sequencer for a solid-state image sensor provides hard/soft configurable control of imaging operations in an imaging core.

Abstract: A computerized device has dynamically modifiable hardware, such as an ASIC, that performs queue-scheduling operations. The hardware incorporates a generic sorting processor (GSP) that is dynamically configurable to implement various sorting algorithms to meet specific queue scheduling requirements for the computerized device. The computerized device extracts a first time stamp value and a second time stamp value associated with a first queue and a second queue, respectively. The computerized device receives instructions to configure a table of the GSP with scheduling entries. The computerized device compares the first time stamp value with the second time stamp value to form a comparison result. The computerized device then selects a decision instruction from the table, based upon the comparison result, and identifies a preferred queue of the first queue and the second queue, based upon the decision instruction.

Abstract: A graphical user interface for a concurrent computing environment that conveys the concurrent nature of a computing environment and allows a user to monitor the status of a concurrent process being executed on multiple concurrent computing units is discussed. The graphical user interface allows the user to target specific concurrent computer units to receive commands. The graphical user interface also alters the command prompt to reflect the currently targeted concurrent computing units.

Abstract: An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication protocols of the initiator module and of the target module. The interface and control module is constructed to set a composite instruction detection signal in response to the detection of a composite instruction executed by the initiator module, which composite instruction detection signal is used for the interfacing. The interface and control module is constructed to detect a composite instruction executed by the initiator module when, at a determined clock cycle of the initiator module, a change of the elementary operation executed by the initiator module is detected with respect to the previous clock cycle of the initiator module, while, at the same time, a signal for selecting the target module which was active is kept active.

Abstract: Disclosed is an IP module for an SOC which brings easiness in designing system architecture and integration. The IP module of the invention includes a controller for generating a control signal for IP module with reference to a handshake signal and sending a control signal which leads the IP module to process input data in response to handshake signal; and a data processor generating output data and a modified handshake signal after processing a handshake signal and input data under the control of the controller. The present invention makes it possible to design an IP module that is easily reusable and optimized in architecture, lightening effort and time for designing and verifying an SOC by means of the proposed IP module.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: A fast and scalable pattern making engine is presented. The engine represents variations on a Shift-And method capable of matching patterns in data streams having high speed data rates. In one aspect of the invention high speed is achieved by accessing the pattern RAM in parallel. In another aspect, the input is likened to TDM and individual slots or channels are accessed separately. The two aspects can also be combined to provide a scalable and high speed pattern matching engine. The engine is adaptable to streams of known length or more complex expressions such as regular expressions with arbitrary length.

Abstract: Compressing program binaries with reduced compression ratios. One or several pre-processing acts are performed before performing compression using a local sequential correlation oriented compression technology such as PPM, or one of its variants or improvements. One pre-processing act splits the binaries into several substreams that have high local sequential correlation. Such splitting takes into consideration the correlation between common fields in different instructions as well as the correlation between different fields in the same instruction. Another pre-processing reschedules binary instructions to improve the degree of local sequential correlation without affecting dependencies between instructions. Yet another pre-processing act replaces common operation codes in the instruction with a symbols from a second alphabet, thereby distinguishing between operation codes that have a particular value, and other portions of the instruction that just happen to have the same value.

Abstract: An operand stack (10) permits optimization of memory space and a continuous check of operand type by creating a type memory (20) which stores type information for each operand, said information comprising information about the length of the operand. This length information available for each single operand permits the operands to be stored extremely densely, while the prior art uses uniform length stack elements for each operand, their length depending on the longest operand.

Abstract: In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates an access request for the memory device, the predicted one of the instructions stored in the instruction buffer is provided to the system bus for receipt by the processor upon determining that the predicted one of the instructions stored in the instruction buffer hits the access request from the processor. An embedded system with an instruction prefetching device is also disclosed.

Abstract: A method of preventing an electronic file containing a computer virus from infecting a computer system using the Symbian™ operating system, the method comprising the steps of scanning files using an anti-virus application, and if an infected file is identified, maintaining the file in an open non-sharing state, whereby other applications running on the computer system may not operate on an infected file.

Abstract: A video processing system with reconfigurable instructions includes a processor, a first register file in the processor, an extension adapter, programmable logic, a second register file coupled to the programmable logic, and a load/store module. The processor executes a video application that contains an instruction extension not native to the instruction set of the processor. The extension adapter detects the instruction extension in the video application. The programmable logic device is configured to execute the instruction extension. The programmable logic device then executes the instruction extension. The load/store module transfers data between the first register file and the second register file, and transfers data directly between the second register file and a system memory for use by the processor in processing the video application.

Abstract: An image transmission device and methods a transmitting device and method, a receiving device and method, and robot apparatus are capable of effectively transmitting the image data of multiple channels by using the existing systems which are formed on the premise of transmitting and receiving of the image data through single transmission line. At a transmitting side, the image data of multiple channels to be input is multiplexed with switching the channels by frame, and prescribed image information is added to each of the multiplexed image data of each frame. At a receiving side, the image information added to each of the image data for each frame respectively transmitted from the transmitting device are analyzed, and dividing device for dividing for each frame and outputting the multiplexed image data transmitted from the transmitting device to the corresponding channels is provided based on the analysis result.

Abstract: An image transmission device and method, a transmitting device and method, a receiving device and method, and robot apparatus are capable of effectively transmitting the image data of multiple channels by using the existing systems which are formed on the premise of transmitting and receiving of the image data through single transmission line. At a transmitting side, the image data of multiple channels to be input is multiplexed with switching the channels by frame, and prescribed image information is added to each of the multiplexed image data of each frame. At a receiving side, the image information added to each of the image data for each frame respectively transmitted from the transmitting are analyzed, and dividing for dividing for each frame and outputting the multiplexed image data transmitted from the transmitting to the corresponding channels is provided based on the analysis result.

Abstract: A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations therein to read data; a pointer memory; and control logic coupled to the pointer memory. The pointer memory saves prior pop pointer values of the pop pointer. The control logic may restore prior pop pointer values from the pointer memory into the pop pointer in response to receiving program branching information.

Abstract: A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

Abstract: In one embodiment of the invention, a register format of a source register operated on by a source instruction in a source block of code is determined. The register format includes an input instruction format and an output block format of the source block of code. The source block of code runs in a source architecture. The source register has multiple formats and is used as an input of the source instruction. The input instruction format contains format of the source register expected by the source instruction. The output block format contains format of the source register after the source block of code is executed. An instruction format inconsistency is detected between the source register and a target register of a target architecture during a translation phase of a binary translation that translates the source block of code into a target block of code running in the target architecture.

Abstract: In some embodiments, a method and apparatus for an energy efficient clustered micro-architecture are disclosed. In one embodiment, the method includes the computation of an energy delay2 product for each active instruction scheduler and one or more associated function blocks of a current architecture configuration over a predetermined period. Once the energy delay2 product is computed, the computed product is compared against an energy delay2 product calculated for a prior architecture configuration to determine an effectiveness of the current architecture configuration. Based on the effectiveness of the current architecture configuration, a number of active instruction schedulers and one or more associated functional blocks within the current architecture configuration is adjusted. In one embodiment, the number of active instruction schedulers and one or more associated functional blocks may be increased or decreased to improve power efficiency of the cluster micro-architecture.

Abstract: A method, an apparatus, and a computer program are provided for managing commands in a multi-queue system. Depending on the types of queues that are utilizes, there can be difficulties in managing the order of execution of commands. To alleviate this problem, dependencies and identifiers are associated with each command that allow command queues in the entire multi-queue system to monitor the status of all commands.

Abstract: A software program extension for a dynamic multi-streaming processor is disclosed. The extension comprising an instruction set enabling coordinated interaction between a packet management component and a core processing component of the processor. The software program comprises, a portion thereof for managing packet uploads and downloads into and out of memory, a portion thereof for managing specific memory allocations and de-allocations associated with enqueueing and dequeuing data packets, a portion thereof for managing the use of multiple contexts dedicated to the processing of a single data packet; and a portion thereof for managing selection and utilization of arithmetic and other context memory functions associated with data packet processing. The extension complements standard data packet processing program architecture for specific use for processors having a packet management unit that functions independently from a streaming processor unit.

Abstract: A method and apparatus for storing and using “register use” information to determine when a register is being used for the last time so that power savings may be achieved is disclosed. The register use information may take the form of “last read” information for a particular register. The last read information may be used to force the value of the register, after being read, to zero or to clock only that register while masking off the other registers. Several methods and hardware variations are disclosed for using the register use information to achieve power savings.

Abstract: Data processors and methods for their configuration and use are disclosed. As opposed to traditional von Neumann microprocessors, the disclosed processors are semantic processors—they parse an input stream and direct one or more semantic execution engines to execute code segments, depending on what is being parsed. For defined-structure input streams such as packet data streams, these semantic processors can be both economical and fast as compared to a von Neumann system. Several optional components can augment device operation. For instance, a machine context data interface relieves the semantic execution engines from managing physical memory, allows the orderly access to memory by multiple engines, and implements common access operations. Further, a simple von Neumann exception-processing unit can be attached to a semantic execution engine to execute more complicated, but infrequent or non-time-critical operations.

Abstract: A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated with an instruction buffer is monitored to determine whether power consumption modes can be initiated within a system. If a number of pending instructions within an instruction buffer is greater than a particular threshold value, a normal mode of operation is initiated. If the number of pending instructions is less than the threshold value, the system is put in a reduced mode of operation. In the reduced mode of operation, processing is reduced to lower power consumption within the system. Accordingly, power consumption is altered to match a level of activity within the instruction buffer.

Abstract: An image transmission device and method, a transmitting device and method, a receiving device and method, and robot apparatus are capable effectively transmitting the image data of multiple channels by using the existing systems which are formed on the premise of transmitting and receiving of the image data through single transmission line. At a transmitting side, the image data of multiple channels to be input is multiplexed with switching the channels by frame, and prescribed image information is added to each of the multiplexed image data of each frame. At a receiving side, the image information added to each of the image data for each frame respectively transmitted from the transmitting device are analyzed, and dividing device for dividing for each frame and outputting the multiplexed image data transmitted from the transmitting device to the corresponding channels is provided based on the analysis result.

Abstract: This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms. The method includes decomposing the matched instruction set processor system into interconnected design vectors, each of the interconnected design vectors including a binding header method, a run method, a conjugate virtual machine (CVM), a binding trailer method, and an invocation method. The method also includes analyzing and mapping the interconnected design vectors into a re-configurable platform.

Abstract: A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads (load counter) and for counting the number of cycles (cycle counter). The method begins with a processor determining which load to select for measurement. In response to the determination, the cycle counter value is stored in a rewind register. The processor issues the load and begins counting cycles. In response to the load completing, the level of memory for the load is determined. If the load was executed from the desired memory level, the load counter is incremented. Otherwise, the cycle counter is rewound to its previous value.

Abstract: A transmission/reception device for mobile radio applications has a microprocessor (DSP), at least one task-specific processor (P1, P2, P3) and a processor interface (2). The task-specific processor (P1, P2, P3) can be configured, by transmitting suitable configuration instructions from the microprocessor via the processor interface (2), such that a basic function performed by the task-specific processor (P1, P2, P3) can be controlled by changing configuration parameters.