Abstract: The use of a configuration-based execution model in conjunction with a content addressable memory (CAM) architecture provides a mechanism that enables performance of a number of computing concepts, including conditional execution, (e.g., If-Then statements and while loops), function calls and recursion. If-then and while loops are implemented by using a CAM feature that emits only complete operand sets from the CAM for processing; different seed operands are generated for different conditional evaluation results, and that seed operand is matched with computed data to for an if-then branch or upon exiting a while loop. As a result, downstream operators retrieve only completed operands. Function calls and recursion are handled by using a return tag as an operand along with function parameter data into the input tag space of a function. A recursive function is split into two halves, a pre-recursive half and a post-recursive half that executes after pre-recursive calls.

Abstract: A method and apparatus for the computerized management of a digital ecosystems through the creation and management of intelligent information packets that enable computerized management of the creation, flow, and use of electronic and optically scanned paper documents. An XML packet is structured to combine document data, comprising electronic or optically scanned documents, with rules, work-flow controls, audit capability, and signature controls. Tamper proofing ensures validity of information, such as legal documents, that requires proof and tracking of official origin, approval, or status.

Abstract: Optimizing pipeline handler execution. A method may be practiced in a computing environment including an execution pipeline. The method includes acts to optimize execution of handlers in the pipeline. The method includes receiving a payload object. Policy information about the payload object is referenced. The policy information includes at least one property value. Based on the policy information about the payload object, handlers are selected from among the pipeline to execute on the payload object. The policy information may be referenced by strategies. Handlers may be registered with the strategies to facilitate the strategies being used to select handlers.

Abstract: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

Abstract: A signal processing network and method for generating code for such a signal processing network are described. Pipeline blocks are each coupled to receive control signaling and associated information signaling from a scheduler. Each of the pipeline blocks respectively includes an allocation unit, a pipeline, and section controllers. The allocation unit is configured to provide a lock signal and sequence information to the section controllers in each of the pipeline blocks. The section controllers are configured to maintain in order inter-pipeline execution of the sequence responsive to the sequence information and the lock signal.

Abstract: An approach to performing graph-based computation uses one or both of an efficient startup approach and efficient control using process pools. Efficient startup of a graph-based computation involves precomputing data representing a runtime structure of a computation graph such that an instance of the computation graph is formed using the precomputed data for the required type of graph to form the runtime data structure for the instance of the computation graph. Pools of processes that are each suitable for performing computations associated with one or more vertices of the computation graphs are formed such that at runtime, members of these pools of processes are dynamically assigned to particular vertices of instances of computation graphs when inputs are available for processing at those vertices.

Abstract: A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput.

Abstract: A power-efficient, distributed reconfigurable computing system and method are provided. A reconfigurable computing system may include an embedded controller for performing real-time control and initialization and circuitry that supports data-flow driven execution of processing phases. The circuitry may include processing elements such as RAM-based field programmable gate array devices and direct memory access engines. The processing elements can be configured for one or more functions or operations of a program and then reconfigured for other functions or operations of the program. The processing elements can be configured or reconfigured to construct a desired sequence of operations in real-time. A processing element may be divided into slots, each of which includes a substantially similar amount of resources. A processing element includes one or more wrappers, and a wrapper may occupy a slot or a group of slots. Layered software architecture separates control software from implementation software.

Abstract: The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., discrete cosine transform (DCT), fast-Fourier transform (FFT) and other operations. Other features are provided.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: A method of generating digital control parameters for implementing digital logic circuitry comprising functional nodes with at least one input or at least one output and connections indicating interconnections between said functional nodes, wherein said digital logic circuitry comprises a first path streamed by successive tokens, and a second path streamed by said tokens is disclosed. The method comprises determining a necessary relative throughput for data flow to said paths; assigning buffers to one of said paths to balance throughput of said paths; removing assigned buffers until said necessary relative throughput is obtained with minimized number of buffers; and generating digital control parameters for implementing said digital logic circuitry comprising said minimized number of buffers. An apparatus, a computer implemented digital logic circuitry, a Data Flow Machine, methods and computer program products are also disclosed.

Abstract: A data distribution system is provided which generates outputs attribute data about multimedia data in advance and broadcasts the output attribute data together with the multimedia data so that the receiving terminal can grasp the outlines of the entire multimedia data and improve the visibility. A data broadcasting device (1) generates output attribute data about multimedia data in a data analyzing portion (13). The output attribute data exists alone or is embedded in the multimedia data. The multimedia data and the output attribute data are encoded in a protocol encoder (14) and broadcast from a transmitter (15). A receiving terminal device (2) receives the broadcast data in a tuner (21) and obtains the multimedia data and output attribute data in a tuner (21). When a data display portion (26) displays the obtained multimedia data, the output attribute data is referred to and information related to the multimedia data is displayed together with the multimedia data.

Abstract: From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the packet rates of the input arc and the output arc are lower than an upper-limit value of a pipeline transfer rate of a processor element. Based on the determination result, it is determined whether it is possible to execute the described flow graph program in the processor element. Performance evaluation of a program to be executed by a data driven processor based on an asynchronous pipeline transfer control can be carried out with ease and in a short time.

Abstract: A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between the memory units, the accelerator units, and the processor core. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core may include an execution unit that may be configured to execute instructions that are associated with datapath flow control. The programmable network may be configured to selectively provide the connectivity in response to execution of particular instructions.

Abstract: Embodiments of the invention are directed to an integrated circuit including a communication network that interconnects individual object nodes. The nodes include a receiving port and a sending port, each structured to send messages along communication pathways, which are connected between a sending and a receiving port. Individual communication pathways may operate at different clock frequencies from one another and messages sent along them may be asynchronous from one node to another. Sending ports are structured to stall until the sending port receives notice that the receiving port is able to accept a message. Additionally, sending ports include protocol information that eliminates the necessity for message timing oversight, and instead, the delivery of each message is made on the local level independent of the operating speed of the port's attached processor or of the communication network itself. Messages may be sent across clock boundaries without data loss.

Abstract: Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and receiving nodes each coupled by a communication channel. Individual communication channels operate at individually controllable clock speeds. Data messages sent between nodes pass at the speed of the communication channels. These data messages are sent by a sending port that includes registers for storing data and registers for protocol signals that control the timing and movement of the data. Data crosses clock boundaries without data loss. At least some of the microprocessors include fork functions that output a data stream to more than one output port. Similarly, at least some of the microprocessors include join functions that can create a single data stream from inputs from more than one input port.

Abstract: A method for pipelining execution input/output (I/O) includes obtaining a first I/O operation, determining a first plurality of stages of a pipeline needed to execute the first I/O operation, and executing each of the first plurality of stages to complete the I/O operation, wherein the first plurality of stages is a subset of a plurality of stages associated with pipeline, and wherein each of the first plurality of stages of the pipeline is executed in sequence.

Abstract: A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: The present invention concerns data flow control in adaptive integrated circuitry which utilizes a data flow model for data processing. The present invention controls task initiation and execution based upon data consumption measured in data buffer units. In the various embodiments, when a first task of a plurality of tasks is initiated, buffer parameter is determined and a buffer count is initialized for the first task. For each iteration of the first task using a data buffer unit of input data, the buffer count is correspondingly adjusted, such as incremented or decremented. When the buffer count meets the buffer parameter requirements, the state of the first task is changed, which may including stopping the first task, and a next action is determined, such as initiating a second task. The various apparatus embodiments include a hardware task manager, a node sequencer, a programmable node, and use of a monitoring task within an adaptive execution unit.

Abstract: For use in a wide-issue processor, a mechanism for, and method of, conditionally executing instructions and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a conditional execution block state machine that tags and generates link pointers for instructions located in a conditional execution block and (2) conditional link pointer registers, associated with stages in a pipeline of the processor, that contain and cause the link pointers to move therethrough as the instructions located in the conditional execution block move through the stages.

Abstract: A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.

Abstract: A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel comprising a reconfigurable function unit based on a pipelined array of configurable look-up table based cells controlled by a special purpose control unit, thus easing the elaboration of critical kernels algorithms.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: An efficient coding scheme is disclosed. The coding provides for the separation of immediate data from the instruction stream. A static flow analysis determines the immediate data in the program and assigns it a location for storage in a data table. The flow analysis also generates information directing the processor to the location of the immediate data in the data-order table. When an immediate instruction is encountered during execution, the processor retrieves the immediate data from the data-order table.

Abstract: An architecture for intercepting and processing packets from a network is disclosed. The architecture provides both stateful and stateless processing of packets in the bi-directional network flow. Further, stateless processing is provided by a parallel arrangement of network processors while stateful processing is provided by a serial arrangement of network processors. The architecture permits leveraging existing bi-directional devices to process packets in a uni-directional flow, thereby increasing the throughput of the device. The ability to share state among the stateless processor, among the stateful processors of each packet flow direction and between the stateless and stateful processors provides for dynamic adaptability and analysis of both historical and bi-directional packet activity.

Abstract: A stateless message-passing scheme for interactions between a network processor and a coprocessor is provided. The network processor, when receiving data frames for transmission from a network element to another network element encapsulates the entire packet that it receives within a frame. In this frame, there is provided a header field and a data field. The data field contains the data that needs to be transferred, and the header field contains all of the information regarding the deep-processing that the coprocessor is to perform so that no information of any type need be stored either by the network processor or separately regarding the processing of the data in the data packet. The coprocessor performs the operation designated by the header and returns the altered packet and header to the network processor.

Abstract: The present invention provides methods specifically geared to finding natural splits in wide, nearly symmetric dependence graphs and assigning the components of the split to clusters in a VLIW processor. The basic approach of these methods is to assign a node n of the dependence graph to the cluster to which it has the strongest affinity. A node n has the strongest affinity to the cluster containing its closest common ancestor node. Then, the mirror image node or nodes of the node n are located if they are present in the graph and are assigned to other clusters in the processor to which they have the strongest affinity.

Abstract: A multi-port register file may be selectively bypassed such that any element in a result vector is bypassed to the same index of an input vector of a succeeding operation when the element is requested in the succeeding operation in the same index as it was generated. Alternatively, the results to be placed in a register file may be bypassed to a succeeding operation when the N elements that dynamically compose a vector are requested as inputs to the next operation exactly in the same order as they were generated. That is, for the purposes of bypassing, the N vector elements are treated as a single entity. Similar rules apply for the write-through path.

Abstract: A stream computer comprises a plurality of interconnected functional units. The functional units are responsive to a data- stream containing data and tokens. The data is to be operated on by one or more of the plurality of interconnected functional units. Digital logic cooperatively associated with one of the functional units adds one or more tokens to the data stream presented to one of the functional units. The tokens are representative of the type of data being generated or received by the functional units. The digital logic also reports the occurrence of said one or more tokens within said data stream without interrupting the data stream. The digital logic reports one or more tokens arriving at one of the functional units as part of the data stream to a graphical programming environment. The graphical programming environment is compatible with human perception.

Abstract: In one embodiment, a method is provided. The method of this embodiment includes generating, by a processor that includes a plurality of processing engines capable of executing program instructions, a packet. The method of this embodiment also includes transmitting the packet to at least one of the processing engines. Additionally, the method of this embodiment also includes, in response, at least in part to receipt of the packet by the at least one of the processing engines, modifying at least in part, by the at least one of the processing engines, a set of program instructions that the at least one processing engine is capable of executing. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: Embodiments of the invention relate to a processing cell for use in computing systems. Generally, a processing cell generates remote instructions to be received and processed by at least one other processing cell. A processing cell may include a program counter, an instruction memory, and appropriate elements such as a branch lookup, a branch unit, etc. Alternatively, the processing cell may include a state machine that replaces the program counter and the instruction memory. Embodiments of the invention are able to support the VLIW mode, the MIMD) mode, a mixture of both modes of execution, etc.

Abstract: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to recieve executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.

Abstract: A floating point unit includes floating point processing units for executing floating point instructions that write operands to an external memory and for executing floating point instructions that read operands from the external memory. The floating point also includes an operand queue for storing a plurality of operands associated with one or more operations being processed in the floating point unit. The operand queue stores a first operand written by a floating point write instruction executed by a first one of the plurality of floating point processing units and supplies the first operand to a floating point read instruction executed by a second one of the plurality of floating point processing units when the first operand is committed or virtually committed.

Abstract: General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions.

Abstract: A packet generation unit divides a plurality of generated clocks to generate clocks with different frequencies, selects any of the frequencies, sets destination information and data depending on a selected clock rate and generates a data packet that stores the setting result. An input/output control unit taken the data packet generated by the packet generation unit and sends it to a program storage unit or a data memory interface unit according to the destination information. As a result, information can be internally processed in a predetermined frequency without depending on an outside clock. When the outside clock is slow, information can be internally processed in a higher-rate frequency. On the contrary, when the outside clock is too fast to internally process information, information can be internally processed in a lower-rate frequency to secure a processing time.

Abstract: When a prescribed operation is performed on 1024-bit multiple-precision data in a data-driven processor, the multiple-precision data is treated as a plurality of single-precision data obtained by dividing the multiple-precision data by every 32 bits in accordance with the memory word length of an accumulation memory, and a group of 32 memory words each having 32 bits of the accumulation memory is treated as the multiple-precision data. Accordingly, in the data-driven processor, a usual memory region can serve as an accumulator for multiple-precision data without having to provide any accumulator dedicated to multiple-precision data in the data-driven processor. In addition, since the multiple-precision data is divided into independent single-precision data each having 32 bits, operations for all data can be performed concurrently. Thus, a parallel processing capability of the data-driven processor can be maximized.

Abstract: A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input of the data-flow graph, a computational instruction is generated for each node of the data-flow graph, and a sink instruction is generated for each output of the data-flow graph. The computational instruction for a node includes a descriptor of an operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier. The computer is directed by a program of instructions to implement a computation representable by a data-flow graph.

Abstract: A data flow processor includes a number of hardware units each having more than one mode. A plurality of hardware units may be connected together to implement a flow made up of a series of processes. The flows, initiated by a central processing unit, may proceed independently and substantially at their own pace. Thus, the flows may operate in parallel, independently with respect to one another. Each of the hardware units may be configured differently to operate with each of the different flows.

Abstract: Multithreaded data- and context-flow processing is achieved by flowing data and context (thread) identification tokens through specialized cores (functional blocks, intellectual property). Each context identification token defines the identity of a context and associated context parameters affecting the processing of the data tokens. Parameter values for different contexts are stored in a distributed manner throughout the cores. Upon a context switch, only the identity of the new context is propagated. The parameter values for the new context are retrieved from the distributed storage locations. Different cores of the system and different pipestages within a core can work simultaneously in different contexts. The described architecture does not require long propagation distances for parameters upon context switches, or that an entire pipeline finish processing in one context before starting processing in another.

Abstract: Aspects of a method and system for digital signal processing within an adaptive computing engine are described. These aspects include a mini-matrix, the mini-matrix comprising a set of composite blocks, each composite block capable of executing a predetermined set of instructions. A sequencer is included for controlling the set of composite blocks and directing instructions among the set of composite blocks based on a data-flow graph. Further, a data network is included and transmits data to and from the set of composite blocks and to the sequencer, while a status network routes status word data resulting from instruction execution in the set of composite blocks. With the present invention, an effective combination of hardware resources is provided in a manner that provides multi-bit digital signal processing capabilities for an embedded system environment, particularly in an implementation of an adaptive computing engine.

Abstract: A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs acheivable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field.

Abstract: A first set of instructions and incoming data are provided to a first processing unit of a data driven processor, to operate upon the incoming data. The first processing unit, in response to recognizing that the first set of instructions will require either reading from or writing to external memory, sets up a logical channel between a second processing unit of the processor and the external memory, to transfer additional data between the external memory and the second processing unit. This capability may be implemented by the addition of a control port, separate from data ports, to the first processing unit, where the control port allows the first processing unit to write addressing information and mode information (including the location of the additional data) for reading or writing the additional data via a memory access unit data channel of the processor.

Abstract: A router is formed by an M-input, 1-output junction unit and a 1-input, N-output branching unit. Where M and N satisfy the relation of (M>N), the transfer rate of a path between the junction unit and the branching unit is made the total sum of the transfer rates of inputs of IN1 to INM, whereby N times faster transfer becomes possible.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: There is provided a data processing apparatus capable of increasing a number of general purpose registers while maintaining upper compatibility. Register designating information for designating a register is divided in two portions. The two portions are arranged in separate basic units on the basic units of an instruction code. When one instruction code is made ignorable and the ignorable instruction code is ignored, a control unit (CONT) executes register selecting operation by implicitly assuming predetermined register designating information. Thereby, when only a general purpose register (existing general purpose register) capable of being designated implicitly is used, the ignorable instruction code can be ignored and accordingly, the instruction codes are not increased. When an at least conventionally equivalent general purpose register is used, a conventionally equivalent instruction code may be used. By preventing the instruction codes from increasing, processing speed is not reduced.

Abstract: A table storing a state transition rule is arranged in a memory. By referencing the table based on input data, the process to be performed for the input data is determined and executed. Additionally, a process capability can be changed by altering a setting in this table. As a result, a data processing device that can perform the processes for general-purpose data, such as a stream data process, etc., at high speed, and can flexibly change a capability according to the circumstances.

Abstract: An array of processor elements has multiple instruction streams and multiple data streams broadcast to all of the processor elements. The processor elements are each connected to multiple neighbouring processor elements within a cruciate neighbourhood. The architecture is suitable for use in fine-grained applications. The array may have a processor element for each pixel of an image. The array is preferably provided on a single integrated circuit having 10,000 or more processor elements.

Abstract: A Storage Reference Buffer (SRB) designed as an autonomous unit for all Store operations that transfer data from the execution unit of a processor to the memory hierarchy and Load operations that transfer of data from the memory hierarchy to the execution unit of the processor. The SRB partitions up the Load and Store operations into several smaller operations in order to perform them in parallel with other Load and Store requests. System elements are included to determine unambiguously which of these Load and Store operations may be performed without waiting for prior operations to be completed. The SRB also includes system elements to detect whether requests may be satisfied by existing entries in the SRB without having to access the cache. The SRB is operated as a content addressable memory. Load request are simultaneously launched to cache and to the SRB with the Cache request being canceled if the Load request may be satisfied by an SRB entry.

Abstract: An encryption system permits end-to-end encryption of information over an untrusted interconnection network. The information encryption system includes at least one client for processing information. The system also includes at least one storage device for holding the information. At least one key server provides a data key for encrypting and decrypting the information. An encryption module is associated with each client. Each encryption module has a first processor accessing a first memory and a second processor accessing a second memory different from the first memory. The first processor communicates with the associated client. The second processor communicates with the storage device. The first processor communicates with the second processor through a dedicated channel. The second processor obtains the data key from the key server. Information is received from the first processor over the dedicated channel and encrypted using the data key. The encrypted information is then stored on the storage device.

Abstract: This invention involves a Distributed-Structure-based parallel module structure and parallel processing method. The object of the invention is to provide a novel sequence-net computer architecture. A parallel operating structure with N+1 independent flow-sequences is created, and the N+1 flow-sequences control independently the distributed token via the sequence-net instructions to realize the parallel operating of module. Wherein N flow-sequences is regular type, a new consistency flow-sequence Sc running independently is composed by consistency tokens. The distributed token connecting among multi-machines support the co-operation running among N+1 flow-sequences.