Abstract: A data processing system supports a predicated-loop instruction that controls vectorised execution of a program loop body in respect of a plurality of vector elements. When the number of elements to be processed is not a whole number multiple of the number of lanes of processing supported for that element size, then the predicated-loop instruction controls suppression of processing in one or more lanes not required.

Abstract: A machine instruction is provided that has associated therewith a result location to be used for a set operation, a first source, a second source, and an operation select field configured to specify a plurality of selectable operations. The machine instruction is executed, which includes obtaining the first source, the second source, and a selected operation, and performing the selected operation on the first source and the second source to obtain a result in one data type. That result is quantized to a value in a different data type, and the value is placed in the result location.

Abstract: A better compromise between encoding complexity and achievable rate distortion ratio, and/or to achieve a better rate distortion ratio is achieved by using multitree sub-divisioning not only in order to subdivide a continuous area, namely the sample array, into leaf regions, but using the intermediate regions also to share coding parameters among the corresponding collocated leaf blocks. By this measure, coding procedures performed in tiles—leaf regions—locally, may be associated with coding parameters individually without having to, however, explicitly transmit the whole coding parameters for each leaf region separately. Rather, similarities may effectively exploited by using the multitree subdivision.

Abstract: A better compromise between encoding complexity and achievable rate distortion ratio, and/or to achieve a better rate distortion ratio is achieved by using multitree sub-divisioning not only in order to subdivide a continuous area, namely the sample array, into leaf regions, but using the intermediate regions also to share coding parameters among the corresponding collocated leaf blocks. By this measure, coding procedures performed in tiles—leaf regions—locally, may be associated with coding parameters individually without having to, however, explicitly transmit the whole coding parameters for each leaf region separately. Rather, similarities may effectively exploited by using the multitree subdivision.

Abstract: An analysis model execution unit executing a part of an analysis model, an analysis model partial execution unit partially executing the analysis model based on intermediate data generated during execution of the analysis model, external storage storing the intermediate data and mapping information which is corresponding relationship between the intermediate data and the analysis model, and an analysis model general processing unit generating the mapping information by associating the intermediate data with the analysis model and reading the intermediate data associated with the analysis model from the external storage based on the mapping information are provided.

Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed.

Abstract: An apparatus and method for processing efficient multicast operation.

Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. In hardware, an input buffer stores incoming input records from a compressed stream. A plurality of decoders decode at least one input record from the input buffer out output an intermediate record from the decoded data and a subset of the plurality of decoders to output a stream of literals. Finally, a reformat circuit formats an intermediate record into one of two types of tokens.

Abstract: A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.

Abstract: Techniques are described to perform a shuffle operation. Rather than using an all-lane to all-lane cross bar, a shuffler circuit having a smaller cross bar is described. The shuffler circuit performs the shuffle operation piecewise by reordering data received from processing lanes and outputting the reordered data.

Abstract: A method for controlling powering of a mobile platform comprising a first Finite State Machine (FSM) and a second FSM. The method comprises synchronizing the first FSM with the second FSM, wherein the first FSM is arranged on a first Integrated Circuit (IC) comprised in the mobile platform and configured to control a first Power Management Unit (PMU) arranged on the first IC, and wherein the second FSM is arranged on a second IC comprised in the mobile platform and configured to control a second PMU arranged on the second IC, whereby the first PMU and the second PMU are synchronized to operate simultaneously during rank-up and rank-down, thereby providing power control of the mobile platform.

Abstract: An access management robot facilitation system facilitates a robot to execute access management tasks on a target system.

Abstract: A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The optimized microinstruction sequence is output to a microprocessor pipeline for execution. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.

Abstract: A packet parsing engine comprises a DMEM configured to store packet data; one or more registers configured to store parsing instructions or parse results; and one or more arithmetic logic units configured to parse the packet data based on the parsing instructions and to derive the parse results. The engine may be one engine of a plurality of engines configured to access a shared memory, and the engine may be configured to receive data from the shared memory or to send data to the shared memory. The DMEM may be divided into subsections, and at least one of the one or more registers may be divided into subsections, and the subsections may be configured such that while a DMEM subsection and its corresponding register subsection is parsing packet data for a first packet, one or more other subsections load packed data or unload parse results for a second packet.

Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

Abstract: A system comprises generation of a parse tree comprising a plurality of query parse nodes, each of the plurality of query parse nodes corresponding to a respective one of a plurality of portions of a script definition, generation of a first intermediate representation tree comprising an intermediate representation node corresponding to a respective one of each of the plurality of query parse nodes, wherein an intermediate representation node represents a logical operation corresponding to the portion of the script definition of the query parse node which corresponds to the intermediate representation node, definition of links between each of the plurality of query parse nodes and its corresponding the intermediate representation node, determination of a second intermediate representation tree, the second intermediate representation tree resulting from an optimizer transformation executed on the first intermediate representation tree, generation of an intermediate representation node corresponding to a transfo

Abstract: Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.

Abstract: A processor including a first vector register for storing a plurality of source data elements, a second vector register for storing a plurality of control elements, and a vector bit shuffle logic. Each of the control elements in the first vector register corresponds to a different source data element and includes a plurality of bit fields. Each of the bit fields is associated with a single corresponding bit position in a destination mask register and identifies a single bit from the corresponding source data element to be copied to the single corresponding bit position in the destination mask register. The vector bit shuffle logic is to read the bit fields from the second vector register and, for each bit field, to identify a single bit from a single corresponding source data element and copy it to a single corresponding bit position in the destination mask register.

Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed.

Abstract: A system and method are described below for encoding interactive low-latency video using interframe coding. For example, one embodiment of a computer-implemented method for performing video compression comprises: logically subdividing each of a sequence of images into a plurality of tiles, each of the tiles having a defined position within each of the sequence of images, the defined position remaining the same between successive images; detecting motion within the sequence of images occurring at each of the positions of each of the tiles; and encoding each tile within each image of the sequence of images using a first compression format or a second compression format, wherein the frequency at which a particular tile is encoded according to the first compression format across the sequence of images is based on the detected amount of motion at the position of that tile across the sequence of images.

Abstract: A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The plurality of dependent code groups are then output to a plurality of engines of the microprocessor for execution in parallel. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.

Abstract: A conversion system that converts a standard executable program according to a predetermined ISA into a custom executable program executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The conversion system includes a PEU programming tool that converts a functional description of a processing operation to be performed by the PEU of the processor into programming information for the PEU to perform the processing operation in response to the UDI. A converter converts the standard executable program into the custom executable program and includes an optimization routine that replaces a portion of the standard executable program with the specified UDI and that inserts the UDI into the custom executable program, and that further inserts a UDI load instruction that specifies the UDI and a location of the programming information in the custom executable program.

Abstract: A system and method of storing and analyzing information is disclosed. The system includes a compiler layer to convert user queries to data parallel executable code. The system further includes a library of multithreaded algorithms, processes, and data structures. The system also includes a multithreaded runtime library for implementing compiled code at runtime. The executable code is dynamically loaded on computing elements and contains calls to the library of multithreaded algorithms, processes, and data structures and the multithreaded runtime library.

Abstract: A compiler system that converts an application source program into an executable program according to a predetermined ISA executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The compiler system includes a PEU programming tool that converts a functional description of a processing operation to be performed by the PEU of the processor into programming information for programming the PEU to perform the processing operation in response to the specified UDI. The compiler system includes a compiler that converts the application source program into the executable program, which includes an optimization routine that represents a portion of the application source program with the specified UDI and that inserts the UDI into the executable program, and that further inserts into the executable program a UDI load instruction that specifies the UDI and a location of the programming information in the executable program.

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a control element, coupled to the out-of order processor via a control bus.

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a control element, coupled to the out-of order processor via a control bus.

Abstract: Computer and graphics processing elements, connected generally in series, form a pipeline. Circuit elements known as di/dt throttles are inserted within the pipeline at strategic locations where the potential exists for data flow to transition from an idle state to a maximum data processing rate. The di/dt throttles gently ramp the rate of data flow from idle to a typical level. Disproportionate current draw and the consequent voltage droop are thus avoided, allowing an increased frequency of operation to be realized.

Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.

Abstract: A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions, and of said sequence of instructions, splitting store instructions into a store address instruction and a store data instruction, wherein the store address performs address calculation and fetch, and wherein the store data performs a load of register contents to a memory address. The method further includes, of said sequence of instructions, splitting load instructions into a load address instruction and a load data instruction, wherein the load address performs address calculation and fetch, and wherein the load data performs a load of memory address contents into a register, and reordering the store address and load address instructions earlier and further away from LD/SD the instruction sequence to enable earlier dispatch and execution of the loads and the stores.

Abstract: A hash value generating device for generating a hash value based on the KECCAK algorithm includes a ? processing unit, a ? processing unit, a ? processing unit, a ? processing unit, and an ? processing unit for performing processing of five steps ?, ?, ?, ?, and ?, included in round processing of the KECCAK algorithm. The ? processing unit includes a ?1 processing unit for performing column sum calculation processing and a ?2 processing unit for performing column sum addition processing. In the round processing, the ? processing unit performs processing before the ?2 processing unit and the ? processing unit performs processing, and the ? processing unit performs processing on a lane after rearrangement processing by the ? processing unit.

Abstract: A technique for processing instructions includes examining instructions in an instruction stream of a processor to determine properties of the instructions. The properties indicate whether the instructions may belong in an instruction sequence subject to decode-time instruction optimization (DTIO). Whether the properties of multiple ones of the instructions are compatible for inclusion within an instruction sequence of a same group is determined. The instructions with compatible ones of the properties are grouped into a first instruction group. The instructions of the first instruction group are decoded subsequent to formation of the first instruction group. Whether the first instruction group actually includes a DTIO sequence is verified based on the decoding. Based on the verifying, DTIO is performed on the instructions of the first instruction group or is not performed on the instructions of the first instruction group.

Abstract: Technologies are described herein for distributed storage and retrieval of directed acyclic graphs, such as version control graphs maintained by a version control system. In order to store data contained in a directed acyclic graph, objects stored in the graph may be grouped into chunks utilizing a relatedness heuristic. The chunks may then be stored in a distributed object store. An index to the objects stored in the chunks may also be created that includes an index entry for each object. The index entry for each object includes a unique identifier for the object and data identifying the location of the object in the distributed object store. The index may be utilized to traverse the directed acyclic graph and to obtain all or a portion of the objects in the directed acyclic graph from the distributed object store.

Abstract: An electronic device is provided, which includes a user interface unit configured to receive an input of a user command, a controller configured to perform an operation according to the input user command and to control the user interface to display a screen according to the result of the operation, and a power supply configured to provide a power to the user interface and the controller, wherein the power supply includes a plurality of converters configured to supply the power to respective loads of the electronic device, and the plurality of converters output voltage values that correspond to levels of the respective loads connected thereto.

Abstract: A transaction within a computer program or computer application comprises program instructions performing multiple store operations that appear to run and complete as a single, atomic operation. The program instructions forming a current transaction comprise a transaction begin indicator, a plurality of instructions (e.g., store operations), and a transaction end indicator. A near-end of transaction indicator is triggered based on a speculative look ahead operation such that an interfering transaction requiring a halt operation may be delayed to allow the current transaction to end. A halt operation, also referred to as an abort operation, as used herein refers to an operation responsive to a condition where two transactions have been detected to interfere where at least one transaction must be aborted and the state of the processor is reset to the state at the beginning of the aborted transaction by performing a rollback.

Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

Abstract: A computer-implemented method, system, and/or computer program product protects access to hardware devices through use of a secure processor. A security computer receives a request from a requesting computer for access to a hardware device on a network. A secure processor within the security computer encrypts the request to generate an encrypted request, which is generated within a core of the secure processor. The secure processor protects a secure application that is used to process the request from other software on the secure processor. The security computer transmits the encrypted request to the hardware device, and then receives an encrypted acknowledgement of the encrypted request from a processor associated with the hardware device. The security computer then creates a communication session between the requesting computer and the hardware device.

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

Abstract: An access management robot facilitation system facilitates a robot to execute access management tasks on a target system.

Abstract: End-user software is used to select lists of values of control signals from a predetermined design of a processor, and a unique value of an opcode is assigned to each selected list of values of control signals. The assignments, of opcode values to lists of values of control signals, are used to create a new processor design customized for the end-user software, followed by synthesis, place and route, and netlist generation based on the new processor design, followed by configuring an FPGA based on the netlist, followed by execution of the end-user software in customized processor implemented by the FPGA. Different end-user software may be used as input to generate different assignments, of opcode values to lists of control signal values, followed by generation of different netlists. The different netlists may be used at different times, to reconfigure the same FPGA, to execute different end-user software optimally at different times.

Abstract: A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.

Abstract: A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.

Abstract: An aspect includes performance profiling of an application. A processor executes an instruction stream of the application including instructions that are dynamically grouped at run-time. The processor monitors for an event associated with sampled instructions. A sampled instruction is associated with other events that include instruction grouping information. A number of the instructions in a group that includes the sampled instruction is determined as a group size. The monitored event is tracked as separate events with respect to each of the sampled instruction and one or more other instructions of the group. Subsequent monitored events are tracked as the separate events for each of the instructions from additional groups having various group sizes formed from a sequence of the instructions. An execution count for the sequence of the instructions is generated based on accumulating the separate events over a period of time.

Abstract: An aspect includes performance profiling of an application. A processor executes an instruction stream of the application including instructions that are dynamically grouped at run-time. The processor monitors for an event associated with sampled instructions. A sampled instruction is associated with other events that include instruction grouping information. A number of the instructions in a group that includes the sampled instruction is determined as a group size. The monitored event is tracked as separate events with respect to each of the sampled instruction and one or more other instructions of the group. Subsequent monitored events are tracked as the separate events for each of the instructions from additional groups having various group sizes formed from a sequence of the instructions. An execution count for the sequence of the instructions is generated based on accumulating the separate events over a period of time.

Abstract: The apparatuses, systems, and methods in accordance with the embodiments disclosed herein may facilitate modifying post silicon instruction behavior. Embodiments herein may provide registers in predetermined locations in an integrated circuit. These registers may be mapped to generic instructions, which can modify an operation of the integrated circuit. In some embodiments, these registers may be used to implement a patch routine to change the behavior of at least a portion of the integrated circuit. In this manner, the original design of the integrated circuit may be altered.

Abstract: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

Abstract: A method and circuit arrangement for selectively predicating instructions in an instruction stream based upon a predication filter criteria defined by a predication filter, which describes types or patterns of instructions that should be predicated. Predication logic compares a respective instruction of an instruction stream to predication filter criteria to determine whether the respective instruction matches the predication filter criteria, and the respective instruction is selectively predicated based on whether the respective instruction matches the predication filter criteria.

Abstract: A method includes selecting for execution in a processor a load instruction having at least one dependent instruction. Responsive to selecting the load instruction, the at least one dependent instruction is selectively awakened based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution. A processor includes an instruction pipeline having an execution unit to execute instructions, a scheduler, and a controller. The scheduler selects for execution in the execution unit a load instruction having at least one dependent instruction. The controller, responsive to the scheduler selecting the load instruction, selectively awakens the at least one dependent instruction based on a status of a store instruction associated with the load instruction to indicate that the at least one dependent instruction is eligible for execution by the execution unit.

Abstract: Embodiments relate to vector processors. An aspect includes endian-mode-sensitive memory instructions for a vector processor. One embodiment includes a computer-implemented method for copying data between a vector register that includes byte elements 0 to S and a memory that is byte addressable. The computer-implemented method includes obtaining a vector instruction by a processor in a computer. The processor determines that the vector instruction is a memory access instruction specifying the vector register and a memory address. In response to the determination that is instruction is a memory access instruction and independent of a current global endian mode setting that is selectable in the processor, the processor executes the memory access instruction by copying the byte data between the memory and the vector register so that the byte element n of the vector register corresponds to the memory address+n for n=0 to S.

Abstract: Technologies for local power gate (LPG) interfaces for power-aware operations are described. A processor includes locally-gated circuitry of a core, main core circuitry of the core, the main core, and local power gate (LPG) hardware. The LPG hardware is to power gate the locally-gated circuitry according to local power states of the LPG hardware. The main core decodes a first instruction of a set of instructions to perform a first power-aware operation of a specified length, including computing an execution code path for execution. The main core monitors a current local power state of the LPG hardware, selects one of the code paths based on the current local power state, the specified length, and a specified threshold, and issues a hint to the LPG hardware to power up the locally-gated circuitry and continues execution of the first power-aware operation without waiting for the locally-gated circuitry to be powered up.

Abstract: A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand of the instruction corresponding to the vector element is set to a first defined value, and if the vector element is not of the selected class and sign, the operand element corresponding to the vector element is set to a second defined value.