Abstract: A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgment instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgment instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgment instruction.

Abstract: An integrated circuit includes a processor. An arithmetic logic circuit group includes a plurality of operation units and a connection channel connecting the operation units in a reconfigurable manner. Parameter-based dedicated hardware can change a process specification thereof by parameter setting. An intermodule interface connects the processor, the arithmetic logic circuit group, and the parameter-based hardware to each other.

Abstract: A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.

Abstract: Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.

Abstract: A shared resource access control system having a gating storage responsive to a plurality of controls with each of the controls derived from an instruction context identifying the shared resource, the gating storage including a plurality of sets of access method functions with each set of access method functions including a first access method function and a second access method function with the gating storage producing a particular one access method function from a particular one set responsive to the controls; and a controller, coupled to the gating storage, for controlling access to the shared resource using the particular one access method function.

Abstract: A method, system, and computer readable article of manufacture to enable parallel execution of a divided source code in a multiprocessor system. The method includes the steps of: inputting an original source code by an input device into the computing apparatus; finding a critical path in the original source code by a critical path cut module; cutting the critical path in the original source code into a plurality of process block groups by the critical path cut module; and dividing the plurality of process block groups among a plurality of processors in the multiprocessor system by a CPU assignment code generation module to produce the divided source code. The system includes an input device; a critical path cut module; and a CPU assignment code generation unit to produce the divided source code. The computer readable article of manufacture includes instructions to implement the method.

Abstract: A thread scheduling mechanism is provided that flexibly enforces performance isolation of multiple threads to alleviate the effect of anti-cooperative execution behavior with respect to a shared resource, for example, hoarding a cache or pipeline, using the hardware capabilities of simultaneous multi-threaded (SMT) or multi-core processors. Given a plurality of threads running on at least two processors in at least one functional processor group, the occurrence of a rescheduling condition indicating anti-cooperative execution behavior is sensed, and, if present, at least one of the threads is rescheduled such that the first and second threads no longer execute in the same functional processor group at the same time.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter settings, a network having reconfigurable connections and coupled to the reconfigurable circuit and to the processing circuit, and at least two interfaces each coupled to the network to provide external coupling for the network.

Abstract: A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern.

Abstract: Described herein is an implementation of a technology for the construction, identification, and/or optimization of operating-system processes. At least one implementation, described herein, constructs an operating-system process having the contents as defined by a process manifest. Once constructed, the operating-system process is unalterable.

Abstract: A method of parallel execution of a first and a second instruction in an in-order processor. Embodiments of the invention enable parallel execution of memory instructions that are stalled by cache memory misses. The in-order processor processes cache memory misses of instructions in parallel by overlapping the first cache memory miss with cache memory misses that occur after the first cache memory miss. Memory-level parallelism in the in-order processor can be increased when more parallel and outstanding cache memory misses are generated.

Abstract: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms and define aspects of an instruction set architecture consistent therewith.

Abstract: A microprocessor REP MOVS macroinstruction specifies the word length of the string in the IA-32 ECX register. The microprocessor includes a memory, configured to store a first and second sequence of microinstructions. The first sequence conditionally transfers control to a microinstruction within the first sequence based on the ECX register. The second sequence does not conditionally transfer control based on the ECX register. The microprocessor includes an instruction translator, coupled to the memory. In response to a macroinstruction that moves an immediate value into the ECX register, the instruction translator sets a flag and saves the immediate value. In response to a macroinstruction that modifies the ECX register in a different manner, the translator clears the flag. In response to a REP MOVS macroinstruction, the instruction translator transfers control to the first sequence if the flag is clear; and transfers control to the second sequence if the flag is set.

Abstract: A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends.

Abstract: It is possible to increase the processor instruction set design job efficiency and reduce workload on designers in investigation of an instruction set. An instruction operation code generation system includes an operation code bit width decision means, an instruction sorting means, and an operation code value decision means. The operation code bit width decision means decides a bit width that can be assigned for an operation code of each instruction according to specification data associated with a processor instruction set. The instruction sorting means sorts the instructions according to the operation code bit width. The operation code value decision means decides the value of the operation code of each instruction.

Abstract: An apparatus and method for communicating information within a network having one or more communication buses (5, 6, 7, 8), consisting of one or more elements (20, 30, 40) to maximise throughput and minimise CPU involvement by executing the following. Compare incoming message identifiers (14) against a set of predetermined identifiers (22). Transpose data sets (12) within the incoming message data frame and where necessary, save and/or transmit new frames as defined by operations dependent upon the incoming identifier. By utilising an optimal set of operands the memory requirement is satisfied by a minimal size of standard type.

Abstract: A method and system for controlling timing in a processor is disclosed. In one aspect of the present invention, the method comprises fetching a plurality of instructions, wherein each instruction has a first default execution time during a first condition, and wherein each instruction has a second default execution time during a second condition; during a first mode, executing the plurality of instructions within a same execution time regardless of whether a condition is the first condition or the second condition; and during a second mode, executing the plurality of instructions within random execution time regardless of whether a condition is the first condition or the second condition. According to the system and method disclosed herein, the method effectively modifies the timing of a processor by controlling and/or minimizing variations in the execution times of instructions.

Abstract: A method for analyzing and presenting in a graphical manner single instruction, multiple data (SIMD) instructions involves disassembling a stream of machine instructions into a stream of assembly language instructions. Instruction objects “M” and “N” are created to represent SIMD instructions “M” and “N” from the stream of instructions. Instruction objects “M” and “N” include multiple data objects corresponding to the multiple data items of the respective SIMD instruction. Different colors are assigned to at least two of the multiple data objects of instruction object “M.” If a data item of SIMD instruction “N” is based on a data item of SIMD instruction “M,” the color from the source object is automatically assigned to the target object. Dependencies between data items of instruction “M” and “N” are annotated by arrows between corresponding data objects. Other embodiments are described and claimed.

Abstract: According to one embodiment, an information processing apparatus comprises a storage storing program modules and parallel execution control description describing relationships of the program modules, a conversion module extracting a part relating to the program module from the parallel execution control description, and creating graph data structure creation information including preceding and succeeding information of the program module, an adding module extracting graph data structure creation information to which the input data is given, creating a node, and adding the created node to a formerly created graph data structure, and an execution module subjecting the graph data structure to at least one of depth-first search and breadth-first search with a restricted breadth, selecting one node from nodes stored in the node memory, and executing a program module corresponding to the selected node.

Abstract: Restricting execution by a computing device of instructions within an application program. The application program is modified such that execution of the selected instructions is dependent upon a corresponding expected state of one or more hardware components in the computing device. In an embodiment, the application program is modified to place the hardware components in the expected states prior to execution of the corresponding selected instructions. Creating the dependency on the hardware components prevents the unintended or malicious execution of the selected instructions.

Abstract: A multi-mode register file is described. In one embodiment, the multi-mode register file includes an operand in a first mode. The multi-mode register file further includes auxiliary information which replaces the operand in a second mode.

Abstract: One embodiment of the present invention provides a processor that is configured to execute load-swapped-partial instructions. An instruction fetch unit within the processor is configured to fetch the load-swapped-partial instruction to be executed. Note that the load-swapped-partial instruction specifies a source address in a memory, which is possibly an unaligned address. Furthermore, an execution unit within the processor is configured to execute the load-swapped-partial instruction. This involves loading a partial-vector-sized datum from a naturally-aligned memory region encompassing the source address.

Abstract: A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

Abstract: Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search algorithms, information security, chemical and biological applications, filtering and the like as well as for systolic wavefront computations for fluid flow and structures analysis, bioinformatics etc. Some applications may also employ both the multi-dimensional pipeline and systolic wavefront methodologies disclosed.

Abstract: One embodiment of the present invention provides a processor which is configured to execute load-swapped instructions, which are possibly directed to unaligned source address. The processor is configured to execute the load-swapped instruction by loading a vector from a naturally-aligned memory region encompassing the source address, and in doing so rotating the bytes of the vector to cause the byte at the specified source address to reside at the least-significant byte position within the vector for a little-endian memory transaction, or causing said byte to be positioned at the most-significant byte position within the vector for a big-endian memory transaction.

Abstract: In the host, an IP issues CCW, and a CH encodes the CCW and a CCW chain by the encode program to create a code including the description of controlling a conditional branch with the DKC and transmits the code to a PORT in the DKC. In the DKC, the PORT decodes the code by the decode program, and a CP sequentially processes each command obtained by the decoding and returns a return code representing the end state of the processing. The host receives the return code to recognize the end state of the processing.

Abstract: An electronic device comprising a ROM, a reprogrammable memory, a processor, and a patching device. The ROM stores a first function starting from a first address, the reprogrammable memory stores a second function starting from a second address, the patching device couples to the ROM and the reprogrammable memory, and the processor couples to the patching device. The patching device receives directive information from the processor and determines whether the processor is going to fetch the first function, and generates and returns a branch instruction to the processor when the processor is going to fetch the first function. After receiving the branch instruction, the processor executes the branch instruction to cause an unconditional jump to the second address and subsequently fetches the second function.

Abstract: It is an object of the present invention to provide an obfuscation device that can achieve both sufficient obfuscation and the appropriate instruction block to be executed. In the obfuscation device, a first instruction generating unit, for each of the first process and the second process, generates an initialization instruction for securing a management area for managing the identification information indicating an instruction block that should be executed next so as to proceed with the process, and to store the initialization instruction in said storage unit.

Abstract: A processing architecture supports executing instructions in parallel after identifying at least one level of dependency associated with a set of traces within a segment of code. Each trace represents a sequence of logical instructions within the segment of code that can be executed in a corresponding operand stack. Scheduling information is generated based on a dependency order identified among the set of traces. Thus, multiple traces may be scheduled for parallel execution unless a dependency order indicates that a second trace is dependent upon a first trace. In this instance, the first trace is executed prior to the second trace. Trace dependencies may be identified at run-time as well as prior to execution of traces in parallel. Results associated with execution of a trace are stored in a temporary buffer (instead of memory) until after it is known that a data dependency was not detected at run-time.

Abstract: A plurality of instructions to be executed in an order of being issued without an appointment of a waiting time or a starting moment are designed to be executed after a certain waiting time; instructions to be executed in an order of being issued without designation of starting moment or waiting time are provided with starting moment or waiting time information so that the instructions can be executed in an order designated by the time information.

Abstract: A system and method to extend the number of architecturally visible registers in a processor while preserving the number of bits of the instruction encoding. The system comprises: an indirection table that encodes register patterns for the registers used in an instruction; instructions to load and store such table entries; a mechanism to identify instructions that use the indirection table; and a mechanism to identify a set of bits in instructions that are used to index into the indirection table. According to another embodiment, a method of encoding registers in a computer instruction comprises constructing a table having a plurality of entries. Each entry specifies a combination of a plurality of registers. The method also comprises generating an instruction having a reference to one of the entries in the table. The method then comprises accessing the plurality of registers specified by the referenced table entry.

Abstract: A method and system for dynamically controlling functionality of an application program and storage medium for storing instructions which effectuate the method are provided The method includes providing a data structure containing modifiable data which indicates current functionality of the application program. The method also includes providing a set of common instructions and first and second sets of optional instructions. The application program has a first functionality when the application program includes the set of common instructions and the first set of optional instructions. The application program has a second functionality different from the first functionality when the application program includes the set of common instructions and the second set of optional instructions. The method further includes modifying the modifiable data if a desired functionality for the application program is different from the current functionality of the application program.

Abstract: Extended, alternate and/or modified instruction behavior can be established using a program construct that appears outside a bounded block of program code in such a way that the behavioral changes are limited to the bounded block and coincide with a particular point in the execution thereof. These extensions, alternations and/or modifications are supported in some processor embodiments in ways that add neither additional code space nor additional execution cycles to the bounded block. In general, the particular point in execution of the bounded block may be specified in a variety of ways, including positionally or temporally. Techniques described herein have broad applicability, but will be understood by persons of ordinary skill in the art in the context of certain illustrative code blocks, including zero- (or low-) overhead loops, lightweight procedures and very long instruction word (VLIW) type instruction packets, and processors that support them.

Abstract: A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a plurality of predicate registers, and at least one execution unit configured to extract a plurality of bit fields from a source reservoir and to populate a plurality of destination lanes in response to a single instruction. In addition, the execution unit is configured to write supplied fill data into the source reservoir if the number of bits in the source reservoir is less than a predetermined number. In addition or alternatively, the system may include at least one execution unit configured to combine a plurality of bit fields from a plurality of source lanes into a continuous bit stream in response to a single instruction executable by the processor.

Abstract: A processor system. The processor system comprises a processor having a first set of instructions associated therewith. The processor system also comprises a programmable logic device and an extension adapter coupled to the processor and the programmable logic device. The extension adapter allows the programmable logic device to implement a second set of reconfigurable instructions for the processor.

Abstract: An arithmetic processing apparatus capable of performing an arithmetic operation for generating a condition flag commonly referred to by using a condition flag generated on an arithmetic operation unit basis in as few steps as possible is provided. The arithmetic processing apparatus, which processes multiple data in parallel based on single instruction, includes: processing elements capable of performing a common arithmetic operation based on the evaluation result of the instruction stored in the instruction register; and a condition flag arithmetic operation unit capable of performing one of the logical operation and the comparison operation on the condition flag retained in each processing element, transferring the operation result to each processing element, and updating the condition flag based on the operation result.

Abstract: Methods and systems are provided for the selective use of a Java WIDE opcode as a prefix as defined in the instruction set of the Java virtual machine or performing a task assigned to the Java WIDE opcode. A Java WIDE opcode is fetched, a determination is made as to whether the Java WIDE opcode is to be used as a prefix, and when the Java WIDE opcode is not to be used as a prefix, a task assigned to the Java WIDE opcode is performed.

Abstract: A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.

Abstract: Provided are a method, system and program for effecting a processor operating mode change to execute device code. A processor receives a call while the processor is operating in a first mode, wherein the call is made to effect execution of device code to control a device. The processor determines whether the call is intended to change a processor operating mode from the first mode to a second mode. The state of the processor is selectively changed to a second mode in which the processor executes second mode instructions loaded in a protected section of memory inaccessible to an operating system in response to determining that the call is intended to change the processor operating mode. The second mode instructions execute the device code to control the device.

Abstract: A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an instruction involving the processing flaw can be completed by avoiding the processing flaw.

Abstract: A data processing apparatus is provided comprising a processing unit for executing instructions, a cache structure for storing instructions retrieved from memory for access by the processing unit, and profiling logic for identifying a sequence of instructions that is functionally equivalent to an accelerator instruction. When such a sequence of instructions is identified, the equivalent accelerator instruction is stored in the cache structure as a replacement for the first instruction of the sequence, with the remaining instructions in the sequence of instructions being stored unchanged. The accelerator instruction includes an indication to cause the processing unit to skip the remainder of the sequence when executing the accelerator instruction.

Abstract: Illustrative embodiments determine the data type of the operand being accessed as well as analyze the data value subrange of the input operand data type. If the operand's data type does not match the required format of the instruction being processed, a determination is made as to whether a subrange of data values of the data type of the input operand is supported natively. If the subrange of data values of the input operand is not supported natively, then a format conversion is performed on the data and the instruction may then operate on the data. Otherwise, the data may be operated on directly by the instruction without a format conversion operation and thus, the conversion is not performed.

Abstract: The image processing apparatus (data processing apparatus) stores data in a storing unit (storing means), inputs and outputs the data to and from the storing unit via a storage control unit (input-output means) and processes the data outputted from the storing unit with a control unit (processing means). The storage control unit inputs and outputs image data to and from the storing unit by the DMA method through a path via a DMA control unit and inputs and outputs other data such as a control instruction to and from the storing unit by the PIO method through a path via a PIO control unit. Image data to be inputted and outputted to and from the storing unit by the DMA method is encrypted in an input operation and decrypted in an output operation by an encryption/decryption unit provided on the input-output path for DMA method.

Abstract: Dynamic modifier function blocks for use in a process control system are disclosed. In accordance with one aspect, an example function block is stored on a machine readable medium for use in a process control system. The example function block includes a base function block that causes a machine to perform an algorithm associated with the process control system and at least one attribute located within the base function block that causes the machine to delete or instantiate at least one dynamic modifier function block.

Abstract: A system for thread-level speculation includes a memory system for storing a program code, a plurality of registers corresponding to one or more execution contexts, for storing sets of memory addresses that are accessed speculatively, and a plurality of processors, each providing the one or more execution contexts, in communication with the memory system, wherein a processor of the plurality of processors executes the program code to implement method steps of dividing a program into a plurality of epochs to be executed in parallel by the system, wherein one of the epochs is executed non-speculatively and the other epochs are executed speculatively, determining a current epoch to be executed on an execution context, encoding addresses read during execution of the current epoch, encoding addresses written during execution of predecessor epochs of the current epoch, and encoding addresses written during execution of successor epochs of the current epoch.

Abstract: One example would provide for maximum throughput thus increasing capacity during times when only low and medium priority work is running while allowing for the shorter turn around times required by critical work. Moreover, it creates a “SMT Control Monitor” (SCM) which would examine the type of work running on the machine. This monitor would turn ON/OFF SMT feature, and suspend/resume job threads as the work load demanded. This idea is different than other SMT control disclosures because it incorporates information from the batch system. This additional information will be used to better manage the state of SMT and the job threads.

Abstract: In a particular embodiment, a circuit device includes a plurality of network ports, power regulator circuitry coupled to the plurality of network ports, and a control input adapted to receive software updates. The circuit device further includes a memory adapted to store a plurality of instructions, including processor operating system instructions and an upgrade routine. The circuit device further includes a programmable processor that is coupled to the memory and to the control input. The programmable processor is adapted to receive software updates via the control input and to execute the upgrade routine to upgrade the processor operating system instructions to reprogram the programmable processor. Further, the programmable processor is adapted to control the power regulator circuitry to selectively provide a power supply to a network device via a selected network port of the plurality of network ports.

Abstract: In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values. Multiple permute instructions may be combined to perform efficient table lookups. Other embodiments are described and claimed.

Abstract: A processor according to the present invention is capable of executing instructions in parallel, the processor further executing a string of instructions consisting of a plurality of instructions allocated at continuous addresses as an execution unit, comprising an instruction analyzer, an instruction executor and an instruction canceling unit. The instruction analyzer comprising debug instruction detectors for detecting a debug instruction which generates debug interruption, the instruction detectors of the same number as the instructions executable in parallel by the processor is provided.