Effecting a processor operating mode change to execute device code
Provided are a method, system and program for effecting a processor operating mode change to execute device code. A processor receives a call while the processor is operating in a first mode, wherein the call is made to effect execution of device code to control a device. The processor determines whether the call is intended to change a processor operating mode from the first mode to a second mode. The state of the processor is selectively changed to a second mode in which the processor executes second mode instructions loaded in a protected section of memory inaccessible to an operating system in response to determining that the call is intended to change the processor operating mode. The second mode instructions execute the device code to control the device.
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In the current 32 bit system processor architecture, an application may invoke the processor to execute code written for a 16 bit operating mode in a 16 bit operating mode. For instance, many devices include device code in their firmware, such as service routines and interrupts that are intended to be executed in a 16 bit environment. This device code may need to be called during operation in the 32 bit mode to control the device, such as change video settings in a video processor, etc.
The Intel Corporation 386 and above 32 bit processor architectures include a Virtual-8086 (V86) mode that emulates a 16 bit environment in which 16 bit instructions, such as device code, may be executed. The processor may switch between V86 mode and protected mode. The processors enters V86 mode from protected mode to execute 16 bit device code, such as an 8086 program, then leaves V86 mode and enters protected mode to continue executing a native 32 bit program, e.g., 80386 program. Further details of V86 mode are described in the publication “Intel Architecture Software Developer's Manual, Volume 3: System Programming” (Copyright Intel, 1999).
For the 64 bit architecture, emulators have been developed because V86 mode is not supported in the 64 bit architecture. Emulators allow execution of instructions intended for 16 bit real mode by emulating the real mode 16 bit device code as 64 bit instructions. Another option is to allow the 64 bit operating system transition to 32-bit protected mode in which the 16 bit mode execution can occur, but this entails having separate interrupt handlers and is costly from a systems and support perspective.
In the following description, reference is made to the accompanying drawings which form a part hereof and which illustrate several embodiments. It is understood that other embodiments may be utilized and structural and operational changes may be made without departing from the scope of the embodiments.
The memory 8 further includes a configuration table 32, such as an Advanced Configuration and Power Interface (ACPI) table, indicating registered ports and values, such that writing one registered value to the registered port invokes system management mode (SMM) to perform device related operations, such as power management operations, updating or controlling a device, etc. The device driver 12 updates the configuration table 32 with information on an I/O port and value, such that writing to that I/O port with that value causes switching to SMM mode to perform operations with respect to that device 14 in the second mode, e.g., real mode. General purpose registers 34 may be accessed by the processor in the first mode (e.g., 64 bit mode) or the second mode (e.g., 16 bit real mode). Before invoking the system management mode (SMM), the device driver 12 or operating system 10 may write to the general purpose registers 34 arguments for the call and an identifier of the device operation associated with device code to execute. The SMM (second mode) code 22 executes the device code associated with the device operation indicated in the general purpose registers 34. The SMM code 22 may use arguments also included in the registers 34 when executing the device code 26 in the second mode, e.g., 16 bit real mode.
The processor determines (at block 206) whether the configuration table 32 includes an entry associating the I/O port and the value subject to the write operation with changing the operating mode of the processor 4. If (at block 206) the configuration table 32 provides this association, then the processor 4 executes (at block 208) a system interrupt to change the processor operating mode from the first mode (e.g., 64 bit) to the second mode (e.g., real mode—16 bit). As part of the state change, the processor 4 saves (at block 210) state information for the first mode operating context in the state save area 30. After changing the state, the processor 4 executes (at block 212) the second mode code 22 to determine a buffer, e.g., general purpose registers 34, associated with the value included in the write to the I/O port, where the buffer may indicate a device operation associated with device code 26 to execute. The processor 4 executes (at block 214) the SMM 22 (second mode) code to execute the device code 26 associated with the device operation indicated in the buffer 34. The SMM code 22 may execute the device operation directly or if the device operation comprises an interrupt, determine from the interrupt table 28 the device code 26 to execute to control the device 14. As discussed, the SMM code 22 is executed in the second (real 16 bit) mode.
The SMM code 22, executing the device code 26 for the device operations, may also write (at block 216) any output data to a buffer, e.g., the general purpose registers 34, accessible to the processor 4 when subsequently executing in the first mode. The output from executing the device code in the second (real) mode may be written to the same or different registers 34 that included the call state information. After executing the device code 26, the SMM code 22 executes (at block 218) an exit instruction to change (at block 220) the state back to the first mode. As part of the state change back to the first mode, the processor 4 may read in data from the state save area 30 to return to the state prior to the state change from the first mode to the second mode. The program from which the initial call was made may then access (at block 222) any return data in the general purpose registers 34.
If (at block 206) the processor does not support a processor/hardware implemented state change for the specific call, then an emulator may be invoked (at block 224) to execute the device code 26 in the first mode having a functionality of the device code. The emulator may include a translator and maps to map a request for a device code instruction intended to be executed in the second (real) mode to corresponding instructions executed in the first mode, e.g., 64 bit mode, to implement the functionality of the device code in the first mode.
Described embodiments provide a technique to enable a hardware state change from a first to a second mode to execute device code in a device non-volatile memory.
Additional Embodiment DetailsThe described embodiments may be implemented as a method, apparatus or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof. The term “article of manufacture” as used herein refers to code or logic implemented in hardware logic (e.g., an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (ASIC), etc.) or a computer readable medium, such as magnetic storage medium (e.g., hard disk drives, floppy disks, tape, etc.), optical storage (CD-ROMs, optical disks, etc.), volatile and non-volatile memory devices (e.g., EEPROMs, ROMs, PROMs, RAMs, DRAMs, SRAMs, firmware, programmable logic, etc.). Code in the computer readable medium is accessed and executed by a processor. The code in which preferred embodiments are implemented may further be accessible through a transmission media or from a file server over a network. In such cases, the article of manufacture in which the code is implemented may comprise a tangible transmission media, such as a network transmission line, wireless transmission media, optical cable, signals propagating through space, radio waves, infrared signals, etc. Thus, the “article of manufacture” may comprise the medium in which the code is embodied. Additionally, the “article of manufacture” may comprise a combination of hardware and software components in which the code is embodied, processed, and executed. Of course, those skilled in the art will recognize that many modifications may be made to this configuration without departing from the scope of the embodiments, and that the article of manufacture may comprise any information bearing medium known in the art.
The described operations may be performed by circuitry, where “circuitry” refers to either hardware or software or a combination thereof. The circuitry for performing the operations of the described embodiments may comprise a hardware device, such as an integrated circuit chip, Programmable Gate Array (PGA), Application Specific Integrated Circuit (ASIC), etc. The circuitry may also comprise a processor component, such as an integrated circuit, and code in a computer readable medium, such as memory, wherein the code is executed by the processor to perform the operations of the described embodiments.
In one embodiment, the invocation of the SMM code may utilize ACPI tables and the second (real) mode operations may utilize the SMM operating mode, which is part of the Intel Corporation's (“Intel”) processor architecture. Further details of the SMM mode are described in the publication from Intel entitled “Intel Architecture Software Developer's Manual, Volume 3: System Programming” (Copyright Intel, 1999). In an alternative embodiment, different vendor protocols may be used to cause a processor/hardware state change to execute device code loaded into memory.
In the described embodiments, the first mode was described as a 64 bit mode and the second mode as a 16 bit real mode. In additional embodiments, the first mode may be a mode other than a 64 bit mode, e.g., 32 bit mode, and the second mode may be a 16 bit mode, or a mode other than a 16 bit mode, such as a 32 bit mode, 8 bit mode, etc.
The illustrated operations of
The foregoing description of various embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Many modifications and variations are possible in light of the above teaching.
Claims
1. A method, comprising: receiving, by a processor, a call while the processor is operating in a first mode, wherein the call is made to effect execution of device code to control an Input/Output (I/O) device, wherein the device code is implemented in a non-volatile memory in the I/O device; loading second mode instructions into a protected second mode section of a computer memory; loading the device code from the non-volatile memory in the I/O device into the second mode section of the computer memory, wherein the device code is executed from the second mode section to the computer memory by the processor operating in the second mode; determining, by the processor, whether the call is intended to change a processor operating mode from the first mode to a second mode; selectively changing the state of the processor to the second mode in which the processor executes second mode instructions loaded in the protected second mode section of the computer memory, wherein the second mode section of the computer memory is inaccessible to an operating system, in response to determining that the call is intended to change the processor operating mode; and executing, by the second mode instructions, the device code to control the I/O device.
2. The method of claim 1, wherein in the first mode, an operand and address sizes are a first bit size and in the second mode, the operand and address sizes are a second bit size.
3. The method of claim 2, wherein the first bit size comprises 64 bits and wherein the second bit size comprises 16 bits.
4. The method of claim 1, further comprising:
- selectively generating a system interrupt to change the processor operating mode from the first mode to the second mode in response to determining that the call is intended to change the processor operating mode, wherein the second mode instructions are executed in response to the system interrupt.
5. The method of claim 4, further comprising:
- writing call state information to at least one buffer accessible to the processor when operating in the second mode, wherein the call state information indicates arguments and a device operation associated with the device code, wherein the call is received after the state information is written to the at least one buffer, and wherein the second mode instructions access the at least one buffer to determine the device code to execute.
6. The method of claim 4, further comprising:
- selectively executing, by the second mode instructions, an exit instruction in response to executing the device code; and
- selectively changing the state of the processor to execute in the first mode in response to executing the exit instruction.
7. The method of claim 6, further comprising:
- selectively writing data to a buffer in response to executing the device code in the second mode before executing the exit instruction; and
- accessing, by instructions executed by the processor in the first mode, data written to the buffer.
8. The method of claim 1, wherein the call comprises writing to an Input/Output port with a value, and wherein determining whether the call is intended to change the processor operating mode comprises determining whether a configuration table associates the I/O port and the value with changing the state mode, further comprising:
- using, by the processor executing in the second mode, the value to determine a buffer indicating a device operation associated with device code, wherein executing the device code comprises executing the device code associated with the indicated device operation.
9. The method of claim 1, further comprising:
- selectively invoking an emulator to execute the device code in response to determining that the I/O port is not indicated in the table as associated with changing the processor operating mode, wherein the emulator executes code in the first mode having a functionality of the device code.
10. A system, comprising: a processor; an operating system; an Input/Output (I/O) device having non-volatile memory including device code to control the I/O device; a computer memory including second mode instructions in a protected second mode section of the computer memory inaccessible to the operating system; system code executed by the processor, wherein execution of the system code is capable of causing operations to be performed, the operations comprising: loading second mode instructions into a protected second mode section of the computer memory; loading the device code from the non-volatile memory, in the I/O device into the second mode section of the computer memory, wherein the device code is executed from the second mode section of the computer memory by the processor operating in the second mode; receiving a call from the device driver while the processor is operating in a first mode, wherein the call is made to effect execution of the device code to control the I/O device; determining whether the call is intended to change the processor operating mode from the first mode to a second mode; selectively changing the state of the processor to execute in the second mode in which the processor executes the second mode instructions in response to determining that the call is intended to change the processor operating mode; and executing the second mode instruction to execute the device code in the second mode to control the I/O device.
11. The system of claim 10, wherein in the first mode, an operand and address sizes are a first bit size and in the second mode, the operand and address sizes are a second bit size.
12. The system of claim 10, wherein the processor executes the system code to further perform:
- selectively generating a system interrupt to change the processor operating mode from the first mode to the second mode in response to determining that the call is intended to change the processor operating mode, wherein the second mode instructions are executed in response to the system interrupt.
13. The system of claim 12, wherein the I/O device further includes a non-volatile memory in which the device code is implemented, further comprising: a device driver, wherein the device driver loads the device code from the non-volatile memory in the I/O device into the second mode section of the computer memory, wherein the device code is executed from the second mode section of the computer memory by the processor operating in the second mode; and wherein the system code is executed by the processor to further perform loading second mode instructions in a second mode section of the computer memory.
14. The system of claim 12, further comprising:
- a device driver;
- wherein the operating system or device driver further perform writing call state information to at least one buffer accessible to the processor when operating in the second mode, wherein the call state information indicates arguments and a device operation associated with the device code, wherein the call is received after the state information is written to the at least one buffer, and wherein the second mode instructions access the at least one buffer to determine the device code to execute.
15. A system, comprising:
- a processor;
- an operating system;
- an Input/Output (I/O) device having a non-volatile memory including device code to control the I/O device;
- a computer memory including second mode section of the computer memory inaccessible to the operating system;
- system code executed by the processor, wherein execution of the system code is capable of causing operations to be performed, the operations comprising: loading second mode instructions into a protected second mode section of the computer memory; loading the device code from the non-volatile memory in the I/O device into the second mode section of the computer memory, wherein the device code is executed from the second mode section of the computer memory by the processor operating in the second mode; receiving a call from the operating system while the processor is operating in a 64 bit mode, wherein the call is made to effect execution of the device code to control the I/O device; determining whether the call is intended to change a processor operating mode from the 64 bit mode to a real bit mode; selectively changing the state of the processor to execute in a real mode in response to determining that the call is intended to change the processor operating mode; and executing the device code in the real mode to control the I/O device.
16. The system of claim 15, wherein in the first mode, an operand and address sizes are 64 bits and in the real mode, the operand and address sizes are 16 bits.
17. An article of manufacture comprising code in a computer readable storage medium executed by a processor in communication with a Input/Output (I/O) device having a non-volatile memory including device code to control the I/O device and with a protected second mode section of computer memory including second mode instructions inaccessible to an operating system, wherein the code is executed by the processor to perform operations comprising: loading second mode instructions into the protected second mode section of the computer memory; loading the device code from the non-volatile memory in the O/I device into the second mode section of the computer memory, wherein the device code is executed from the second mode section of the computer memory by the processor operating in the second mode; receiving a call while the processor is operating in a first mode, wherein the call is made to effect execution of device code to control the I/O device; determining whether the call is intended to change the processor operating mode from the first mode to a second mode; selectively changing the state of the processor to execute in a second mode in which the processor executes the second mode instructions in response to determining that the call is intended to change the processor operating mode; and executing the second mode instructions to execute the device code in the second mode to control the I/O device.
18. The article of manufacture of claim 17, wherein in the first mode, an operand and address sizes are a first bit size and in the second mode, the operand and address sizes are a second bit size.
19. The article of manufacture of claim 18, wherein the first bit size comprises 64 bits and wherein the second bit size comprises 16 bits.
20. The article of manufacture of claim 17, wherein the code includes second mode instructions, wherein the operations further comprise:
- selectively generating a system interrupt to change the processor operating mode from the first mode to the second mode in response to determining that the call is intended to change the processor operating mode, wherein the second mode instructions are executed in response to the system interrupt.
21. The article of manufacture of claim 20, wherein the operating system or a device driver writes call state information to at least one buffer accessible to the processor when operating in the second mode, wherein the call state information indicates arguments and a device operation associated with the device code, wherein the call is received after the state information is written to the at least one buffer, and wherein the second mode instructions access the at least one buffer to determine the device code to execute.
22. The article of manufacture of claim 20, wherein the operations further comprise:
- selectively executing, by the second mode instructions, an exit instruction in response to executing the device code; and
- selectively changing the state of the processor to execute in the first mode in response to executing the exit instruction.
23. The article of manufacture of claim 22, wherein the operations further comprise:
- selectively writing data to a buffer in response to executing the device code in the second mode before executing the exit instruction, wherein the processor is capable of accessing data written to the buffer in the first mode.
24. The article of manufacture of claim 17, wherein the call comprises writing to an Input/Output port with a value, and wherein determining whether the call is intended to change the processor operating mode comprises determining whether a configuration table associates the I/O port and the value with changing the state mode, wherein the operations further comprise:
- using, by the processor executing in the second mode, the value to determine a buffer indicating a device operation associated with device code, wherein executing the device code comprises executing the device code associated with the indicated device operation.
25. The article of manufacture of claim 17, the code is in communication with an operating system having an emulator, wherein the operations further comprise:
- selectively invoking the emulator to execute the device code in response to determining that the I/O port is not indicated in the table as associated with changing the processor operating mode, wherein the emulator executes code in the first mode having a functionality of the device code.
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Type: Grant
Filed: Mar 15, 2005
Date of Patent: Aug 25, 2009
Patent Publication Number: 20060212609
Assignee: Intel Corporation (Santa Clara, CA)
Inventors: Vincent J. Zimmer (Federal Way, WA), Michael D. Kinney (Olympia, WA), Michael A. Rothman (Puyallup, WA), Andrew J. Fish (Olympia, WA)
Primary Examiner: Henry W. H. Tsai
Assistant Examiner: Kris Rhu
Attorney: Konrad Raynes & Victor LLP
Application Number: 11/081,238
International Classification: G06F 3/00 (20060101); G06F 9/00 (20060101); G06F 9/44 (20060101); G06F 15/177 (20060101);