Abstract: A semiconductor device and data transfer method capable of efficient DMA transfer processing. The device comprises: a sector buffer which temporarily stores data during transfer, the buffer having an I/O port used for DMA transfer with a system bus and having an I/O port used for data transfer with the I/O controller; a switching section which switches whether to connect between the system bus and the I/O controller, or to connect between the sector buffer and the I/O controller or the system bus; and a sector buffer controller which separately starts data transfer through the I/O ports and which, when detecting completion of the data transfer of a transfer unit between the sector buffer and the I/O controller, transmits to the switching section a control signal for cutting off data transfer between the sector buffer and the I/O controller and for connecting the system bus and the I/O controller.

Abstract: An instruction mode identification apparatus includes a program counter and a processor. The program counter stores an instruction address, which comprises a plurality of bits for indicating an address of an instruction currently executed or to be executed. At least one of the plurality of bits is a redundant bit. The processor identifies an instruction mode according to the redundant bit. The instruction mode represents an execution mode of the current instruction. An instruction mode identification method is also disclosed.

Abstract: A computing system may support an endian toggle register (ETR) and the endianess of the endian toggle register may be designated using a set endian bit (SEB) or a clear endian bit (CEB) instruction. An endian conversion is performed on the data that is moved into and moved out of the ETR. However, if the destination memory is an endian toggle disabled memory, the contents of the ETR may be transferred to the endian toggle disabled memory without performing the endian conversion. A compiler supported on the computing system may comprise an endian storage class to perform endian conversion, transparently, using high-level languages.

Abstract: A machine readable description of a new feature of a processor is provided by a processor vendor. Control code executing on a processor, such as a traditional operating system kernel, a partitioning kernel, or the like can be programmed to receive the description of the feature and to use information provided by the description to detect, enable and manage operation of the new feature.

Abstract: A programmable device having a processing core is configured to use a subset of configuration memory cells as read/write memory. The subset of memory cells is a don't care set that includes configuration memory cells that can be set or reset without modifying the function or behavior of the configured circuits of the programmable device.

Abstract: A mode processing apparatus includes an MCU. The MCU executes a processing operation according to one of an audio reproducing mode and an audio recording mode, by using a battery as a power supply. Also, the MCU cyclically determines, in parallel with the processing operation according to an operating mode at a current time point, whether or not a terminal voltage Vbat of the battery is equal to or less than a threshold value. When a determination result indicating the terminal voltage Vbat?the threshold value is continued, the MCU requests to stop the processing operation according to the operating mode at a current time point. Moreover, the MCU adjusts a length of a cycle in which the above-described determining process is performed to a length different depending on each operating mode.

Abstract: The operation of a multi-mode application. The multi-mode application has a number of mode-specific logical containers of components. Each mode-specific container contains components that assist the multi-mode application in operating in a corresponding mode. If the application transitions to another mode, the component(s) of the other corresponding mode-specific logical container is used to assist in operating in the other mode. The logical containers may be activated and deactivated during execution time as the application transitions from mode to mode.

Abstract: A processor of SIMD/MIMD dual mode architecture comprises common controlled first processing elements, self-controlled second processing elements and a pipelined (ring) network connecting the first PEs and the second PEs sequentially. An access controller has access control lines, each access control line being connected to each PE of the first and second PEs to control data access timing between each PE and the network. Each PE can be self-controlled or common controlled, such as dual mode SIMD/MIMD architectures, reducing the wiring area requirement.

Abstract: An intelligent case for a handheld computer, the case including a compartment for removably housing the handheld computer; a microcontroller; a first communication device to enable communication between the handheld computer and the microcontroller; one or more recesses for housing one or more data-capture modules; and a second communication device to enable communication between the data-capture modules and the microcontroller; wherein the microcontroller includes: a module manager adapted to handle activation of the data-capture modules, collection of data from the data-capture modules, and communication of the collected data to the hand-held computer; and a first set of applications for controlling, in a first mode, at least some operations of the module manager independently of the handheld computer.

Abstract: A multi-processing system-on-chip including a cluster of processors having respective CPUs is operated by: defining a master CPU within the respective CPUs to coordinate operation of said multi-processing system, running on the CPU a cluster manager agent. The cluster manager agent is adapted to dynamically migrate software processes between the CPUs of said plurality and change power settings therein.

Abstract: Selective power control of one or more processing elements matches a degree of parallelism to requirements of a task performed in a highly parallel programmable data processor. For example, when program operations require less than the full width of the data path, a software instruction of the program sets a mode of operation requiring a subset of the parallel processing capacity. At least one parallel processing element, that is not needed, can be shut down to conserve power. At a later time, when the added capacity is needed, execution of another software instruction sets the mode of operation to that of the wider data path, typically the full width, and the mode change reactivates the previously shut-down processing element.

Abstract: A secure promotion mechanism promotes a current privilege level of a processor in a computer system. The current privilege level controls application instruction execution in the computer system by controlling accessibility to system resources. An operating system performs a privilege promotion instruction, which is stored in a first page of memory not writeable by an application instructions at a first privilege level. The privilege promotion instruction reads a stored previous privilege level state, compares the read previous privilege level state to the current privilege level, and if the previous privilege level state is equal to or less privileged than the current privilege level, promotes the current privilege level to a second privilege level which is higher than the first privilege level.

Abstract: A mobile terminal and method for switching states thereof are disclosed. The mobile terminal comprises a communication processor and an application processor, wherein a state in which only the communication processor is in control is defined as a second state, a state in which both the application processor and the communication processor operate and the application processor is in control is defined as a first state, the method comprising: obtaining, in the second state, trigger information corresponding to an event set; and switching the mobile terminal from the second state to the first state based on the trigger information. The mobile terminal according to the present invention can switch to a state in which only the communication processor is in control by obtaining the trigger information corresponding to an event set.

Abstract: A system and method of power management for computer processor systems, the method including measuring power usage; monitoring execution of instructions for a finishing instruction; determining a finishing instruction address for the finishing instruction; determining measured power usage for the finishing instruction; and storing the finishing instruction address in association with the measured power usage in a Power History Table (PHT). The information stored in the PHT can be employed to manage the power used by the computer processor system.

Abstract: In one embodiment, a reconfigurable cyclic shifter is selectively configurable to operate in (i) five-bit mode to cyclically shift N five-bit messages by up to N degrees or (ii) ten-bit mode to cyclically shift N ten-bit messages by up to N degrees. The reconfigurable cyclic shifter has two five-bit N/2-way non-reconfigurable cyclic shifters. The two non-reconfigurable cyclic shifters together, without additional hardware, do not perform N degrees of cyclic shifting. Thus, five-bit and ten-bit reordering hardware is provided that enables the reconfigurable cyclic shifter to perform up to N degrees of cyclic shifting in the five- and ten-bit modes, respectively. In the five-bit mode, the N five-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts N/2 of the N messages. In ten-bit mode, N/2 of the N ten-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts five of the ten bits of each ten-bit message.

Abstract: An accounting method and multi-threaded processor include a mechanism for accounting for processor resource usage by threads within programs. Relative resource use is determined by detecting a particular cycle state of threads active within the processor. If instructions are dispatched for all threads or no threads, the processor cycle is accounted equally to all threads. Alternatively if no threads are in the particular cycle state, the accounting may be made using a prior state, or in conformity with ratios of the threads' priority levels. If only one thread is in the particular cycle state, that thread is accounted the entire processor cycle. If multiple threads are dispatching, but less than all threads are dispatching, the processor cycle is billed evenly across the dispatching threads.

Abstract: A method for establishing an initial state in a computer system having at least two execution units, a switchover between a performance mode and a compare mode being performed, and during the switchover from the performance mode to the compare mode, an initial state for the compare mode being generated, wherein memories or memory areas that are potentially to be adapted for the initial state are provided with an identifier that indicates whether or not the data and/or instructions in these memories or memory areas must be modified for the initial state.

Abstract: A method and system for controlling timing in a processor is disclosed. In one aspect of the present invention, the method comprises fetching a plurality of instructions, wherein each instruction has a first default execution time during a first condition, and wherein each instruction has a second default execution time during a second condition; during a first mode, executing the plurality of instructions within a same execution time regardless of whether a condition is the first condition or the second condition; and during a second mode, executing the plurality of instructions within random execution time regardless of whether a condition is the first condition or the second condition. According to the system and method disclosed herein, the method effectively modifies the timing of a processor by controlling and/or minimizing variations in the execution times of instructions.

Abstract: Embodiments include a device and a method. In an embodiment, a method applies a first resource management strategy to a first resource associated with a first processor and executes an instruction block in a first processor. The method also applies a second resource management strategy to a second resource of a similar type as the first resource and executes the instruction block in a second processor. The method further selects a resource management strategy likely to provide a substantially optimum execution of the instruction group from the first resource management strategy and the second resource management strategy.

Abstract: A circuit having a pipeline and a configuration circuit. The pipeline generally has multiple stages linked in series by registers. The registers may be governed by a clock signal having a first frequency in a first mode and a second frequency in a second mode. The second frequency may be slower than the first frequency. Each stage may have a respective one of multiple first latencies each shorter than a first period of the first frequency. The configuration circuit may be disposed in the pipeline. The configuration circuit generally bypassing selectively a particular register while in the second mode to form a combined stage. The combined stage may (i) comprise a first of the stages adjoining the particular register and a second of the stages adjoining the particular register and (ii) have a second latency shorter than a second period of the second frequency.

Abstract: Processor resource management devices and methods are disclosed. In some implementations, a device includes a processor, a hardware resource, and a resource manager operable to compare a first execution of one or more instructions pursuant to an optimistic resource management policy and a second execution of one or more instructions pursuant to a pessimistic resource management policy, the optimistic resource management policy assuming that less than an optimistic level of at least one error will occur during the first execution, and the pessimistic resource management policy assuming that greater than a pessimistic level of the at least one error will occur during the second execution. Based at least partially on the comparison, the resource manager selects a resource management policy from between the optimistic and pessimistic resource management policies, and associates the selected resource management policy with the one or more instructions.

Abstract: A circuit capable of being operated in a first and a second mode of operation comprises a storage location adapted to store at least a first state, a second state and a third state, wherein the circuit is adapted to switch to the first mode of operation when the storage location acquires the first or the third state, and wherein the circuit is adapted to switch to the second mode of operation when the storage location acquires the second state.

Abstract: In a processor, a SIMD group (a group of threads for which instructions are issued in parallel using single instruction, multiple data instruction issue techniques) is logically divided into two or more “SIMD subsets,” each containing one or more of the threads in the SIMD group. Each SIMD subset is associated with a different instance of a variable state parameter. The processor determines which of the instructions to be executed for the SIMD group rely on the state variable and serializes execution of such instructions so that the instruction is executed separately for each SIMD subset. Instructions that do not rely on the state variable are advantageously not serialized.

Abstract: One embodiment of the present invention provides a system which performs simultaneous speculative threading. The system staffs by executing instructions in normal execution mode using a first thread. Upon encountering a data-dependent stall condition, the first thread generates an architectural checkpoint and commences execution of instructions in execute-ahead mode. During execute-ahead mode, the first thread executes instructions that can be executed and defers instructions that cannot be executed into a deferred queue. When the data dependent stall condition has been resolved, the first thread generates a speculative checkpoint and continues execution in execute-ahead mode. At the same time, the second thread commences execution in a deferred mode. During execution in the deferred mode, the second thread executes instructions deferred by the first thread.

Abstract: In a data transmission coordinating method, the computer system enters a coordinating state, and a first signal is issued from the central processing unit to the data transmission standard storage unit of the bridge chip. In response to the first signal, a second signal is issued from the data transmission standard storage unit of the bridge chip to the central processing unit to inform the central processing unit of a first operable transmission standard of the bridge chip. After the computer system exits the coordinating state, data transmission between the central processing unit and the bridge chip is performed according to the first operable transmission standard in a first condition.

Abstract: A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads causes the execution of a different predetermined number of operation cells in series, and successively reconfigures an operation cell that has completed a last operation thereof in the time period allocated to a current thread, based on a stored piece of configuration information of the operation cell that corresponds to a next thread, and causes concurrent execution of an operation cell having a configuration for the current thread and (ii) an operation cell having a configuration for the next thread.

Abstract: Methods, systems and computer program products for architecting fault tolerant applications. Embodiments of the invention include a method for executing an application in a computer system, the method including monitoring a behavior of the computer system, the computer system having a subsystem in an operating system of the computer system, in response to encountering a problem in the computer system, performing switching the application from a normal mode of operation to a critical mode of operation, executing the application in the critical mode of operation, determining if the computer system has returned to the normal mode of operation, in response to the computer system returning to the normal mode of operation switching the application to execute in the normal mode and executing the application in the normal mode of operation.

Abstract: A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a second memory unit of a second arithmetic unit; switching the first arithmetic unit to a test mode, in which a first scan chain of the first arithmetic unit is accessible; reading the first test data from the second memory unit; shifting the first test data which have been read through the first scan chain of the first arithmetic unit switched to the test mode for providing test result data for the first arithmetic unit; checking the provided test result data for plausibility for providing a test result for the first arithmetic unit.

Abstract: A pipelined execution unit incorporates one or more low power modes that reduce power consumption by dynamically merging pipeline stages in an execution pipeline together with one another. In particular, the execution logic in successive pipeline stages in an execution pipeline may be dynamically merged together by setting one or more latches that are intermediate to such pipeline stages to a transparent state such that the output of the pipeline stage preceding such latches is passed to the subsequent pipeline stage during the same clock cycle so that both such pipeline stages effectively perform steps for the same instruction during each clock cycle. Then, with the selected pipeline stages merged, the power consumption of the execution pipeline can be reduced (e.g., by reducing the clock frequency and/or operating voltage of the execution pipeline), often with minimal adverse impact on performance.

Abstract: A system is disclosed that includes a fetch stage to retrieve an instruction to be utilized by processing units in a multi-path pipeline. The instruction can have selectors that can select functions to be performed by individual paths of the pipeline that can accept and utilize the same instruction. A first processing unit in a first path can execute a part of the retrieved instruction in response to the function selector, and a second processing unit can execute a part of the retrieved instruction in response to the function selector. Other embodiments are also disclosed.

Abstract: In at least some embodiments, an electronic device comprises a processor and an encryption/decryption (E/D) engine coupled to the processor via a bus. The E/D engine selectively operates in a first mode and a second mode. For the first mode, an E/D engine output is provided to the bus. For the second mode, the E/D engine output is not provided to the bus and is accessible only to the E/D engine.

Abstract: Methods, systems, and products are disclosed for configuring an application for execution on a parallel computer that include: booting up a first subset of a plurality of nodes in a serial processing mode; booting up a second subset of the plurality of nodes in a parallel processing mode; profiling, prior to application deployment on the parallel computer, the application to identify the serial segments and the parallel segments of the application; and deploying the application for execution on the parallel computer in dependence upon the profile of the application and proximity within the data communications network of the nodes in the first subset relative to the nodes in the second subset.

Abstract: Methods, systems, and products are disclosed for executing an application on a parallel computer having a plurality of nodes. Executing an application on a parallel computer includes: booting up a first subset of a plurality of nodes in a serial processing mode; booting up a second subset of the plurality of nodes in a parallel processing mode; profiling, prior to application execution, an application to identify serial segments of the application, parallel segments of the application, and application data utilized by each of the serial segments and the parallel segments; and executing the application on the plurality of nodes, including migrating, in dependence upon the profile for the application upon encountering the parallel segments during execution, only specific portions of the application and the application data from the nodes booted up in the serial processing mode to the nodes booted up in the parallel processing mode.

Abstract: Disclosed is a system and method of adding functionality to a microprocessor, especially a RISC machine having a plurality of cores, with minimal changes in circuitry and while maintaining legacy features. An enhancement to the microprocessor involves modifying a program counter register (P-register). This invention increases the number of bits in the P-register from 9 to 10. A tenth bit signals an extended instruction mode. When the tenth bit is not set, microprocessor instructions perform legacy functions. When the tenth bit is set, the extended instruction mode is active and instructions perform different or enhanced functions.

Abstract: A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.

Abstract: A microprocessor includes a first information holding unit, a second information holding unit, and a switching authorization unit. The first information holding unit holds process identification information and authentication information which are associated with each other. The second information holding unit denies access from outside, and holds entry information of a process and the authentication information which are associated with each other. The switching authorization unit allows switching process when the authentication information held in the first information holding unit with the authentication information held in the second information holding unit match.

Abstract: An apparatus, a method, and a computer program are provided for an architected register file system for multithread system. In conventional architected register file systems, a thread is only capable of utilizing a single register file. However, when register files of other thread are unused, the system resources are wasted. In the modified architected register file system, though, threads are enabled to utilize register files of other threads. The utilization of other thread registers is through the use of control fields added to a Status and Control Register (SCR) associated with each register file that enable and disable usage of other register files.

Abstract: A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode.

Abstract: Methods, systems, and products are disclosed for executing an application on a parallel computer including a plurality of nodes connected together through a data communications network. Each node has a plurality of processors capable of operating independently for serial processing and capable of operating symmetrically for parallel processing. The application has parallel segments for parallel processing and serial segments for serial processing. Embodiments of the invention include: booting up a first subset of the plurality of nodes in a serial processing mode; booting up a second subset of the plurality of nodes in a parallel processing mode; and executing the application on the plurality of nodes, including: migrating the application to the nodes booted up in the parallel processing mode upon encountering the parallel segments during execution, and migrating the application to the nodes booted up in the serial processing mode upon encountering the serial segments during execution.

Abstract: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.

Abstract: Provided are a method, system and program for effecting a processor operating mode change to execute device code. A processor receives a call while the processor is operating in a first mode, wherein the call is made to effect execution of device code to control a device. The processor determines whether the call is intended to change a processor operating mode from the first mode to a second mode. The state of the processor is selectively changed to a second mode in which the processor executes second mode instructions loaded in a protected section of memory inaccessible to an operating system in response to determining that the call is intended to change the processor operating mode. The second mode instructions execute the device code to control the device.

Abstract: A method and device for performing switchover operations in a computer system having at least two execution units are provided, in which switchover units are included which are configured in such a way that they switch over between at least two operating modes, a first operating mode corresponding to a compare mode, and a second operating mode corresponding to a performance mode. An interrupt controller is provided and, furthermore, at least three memory areas are provided, and the access to the memory areas is implemented in such a way that one first memory area is assigned to at least one first execution unit, and one second memory area is assigned to the at least one second execution unit, and at least one third memory area is assignable to the at least two execution units.

Abstract: A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline.

Abstract: A processor performance state optimization includes a system to change a performance state of a processor. In an embodiment, the system to change a performance state of the processor includes a processor and a step logic sub-system operatively coupled with the processor and is operable to communicate a performance state change request to the processor. A core voltage regulator is operatively coupled with the step logic sub-system. An end performance state sub-system to determine a desired end performance state is coupled with the step logic sub-system. And, an enable sub-state transition sub-system to enable sub-state transitions is coupled with the step logic sub-system.

Abstract: A reconfigurable processor (RP) structure is provided, and particularly, a multi-mode providing apparatus including an exclusive coarse-grained array unit for each mode and a multi-mode providing method thereof are provided.

Abstract: The image processing apparatus (data processing apparatus) stores data in a storing unit (storing means), inputs and outputs the data to and from the storing unit via a storage control unit (input-output means) and processes the data outputted from the storing unit with a control unit (processing means). The storage control unit inputs and outputs image data to and from the storing unit by the DMA method through a path via a DMA control unit and inputs and outputs other data such as a control instruction to and from the storing unit by the PIO method through a path via a PIO control unit. Image data to be inputted and outputted to and from the storing unit by the DMA method is encrypted in an input operation and decrypted in an output operation by an encryption/decryption unit provided on the input-output path for DMA method.

Abstract: A register file for a data processing system comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of memory locations. Each memory location is addressable by an encoded address, wherein the encoded address corresponds to at least one register and processor mode. The input ports receive inputs for addressing at least one memory location using an encoded address. The output ports output data from at least memory location addressable by an encoded address.

Abstract: A multirate execution unit is capable of being operated in a plurality of modes, with the execution unit being capable of clocked at multiple different rates relative to a multithreaded issue unit such that, in applications where maximum performance is desired, the execution unit can be clocked at a rate that is faster than the clock rate for the multithreaded issue unit, and in applications where a lower power profile is desired, the execution unit can be throttled back to a slower rate to reduce the power consumption of the execution unit. When the execution unit is clocked at a faster rate than the multithreaded issue unit, the issue unit is permitted to issue more instructions per cycle than when the execution unit is throttled to the slower rate to increase overall instruction throughput.

Abstract: A method for generating a valid signal for an application program in a signal processing system having a plurality of execution units which operate in a performance mode, and in which while the application program is running, a user switches the signal processing system to a comparison mode in which the mode the signals delivered by the execution units are compared with one another to generate the valid signal.

Abstract: A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the automatic modification of the register addressing is not tied to a single vector instruction nor to repeat or loop instructions. Rather, the technique, termed register file indexing (RFI) allows full programmer flexibility in control of the block data operational facility and provides the capability to mix non-RFI instructions with RFI instructions. The block-data operation facility is embedded in the iVLIW ManArray architecture allowing its generalized use across the instruction set architecture without specialized vector instructions or being limited in use only with repeat or loop instructions.