Branch Prediction Patents (Class 712/239)
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Patent number: 7487334Abstract: Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the target of the branch prior to writing the branch into a Level 1 (L1) cache to provide a pre-decoded branch, and then writing the pre-decoded branch into the L1 cache. By pre-calculating matters relating to the targets of branches before the branches are written into the L1 cache, for example, by re-encoding relative branches as absolute branches, a reduction in branch redirect delay can be achieved, thus providing a substantial improvement in overall processor performance.Type: GrantFiled: February 3, 2005Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Brian R. Konigsburg, Hung Qui Le, David Stephen Levitan, John Wesley Ward, III
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Patent number: 7487340Abstract: Embodiments of the invention provide a method of storing branch prediction information. In one embodiment, the method includes receiving a branch instruction and storing local branch prediction information for the branch instruction including a local predictability value for the local branch prediction information. The method further includes storing global branch prediction information for the branch instruction only if the local predictability value is below a threshold value of predictability.Type: GrantFiled: June 8, 2006Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventor: David A. Luick
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Patent number: 7484042Abstract: A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains, and a cache memory within the first coherency domain. The cache memory comprises a data array, a cache directory of contents of the data array, and a cache controller including a prefetch predictor. The prefetch predictor determines a predicted scope of broadcast on the interconnect fabric for a first prefetch operation having a first target address based upon a scope of a previous second prefetch operation having a different second target address. The cache controller issues the first prefetch operation on the interconnect fabric with the predicted scope.Type: GrantFiled: August 18, 2006Date of Patent: January 27, 2009Assignee: International Business Machines CorporationInventors: Benjiman L. Goodman, William J. Starke, Jeffrey A. Stuecheli
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Publication number: 20090006826Abstract: A branch prediction method, capable of predicting a first taken branch instruction within a plurality of fetched instructions, includes: determining whether one of the fetched instructions is the first taken branch instruction to be predicted according to hint instruction(s) or according to latest statistics of whether respective fetched instructions have been taken. The branch prediction method further includes: if one of the fetched instructions is determined to be the first taken branch instruction, performing branch prediction on the first taken branch instruction.Type: ApplicationFiled: June 28, 2007Publication date: January 1, 2009Inventor: Yao-Chung Hu
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Patent number: 7472264Abstract: One embodiment of the present invention provides a system that predicts a jump target for a jump instruction. During operation, the system starts fetching the jump instruction while executing a process. Next, the system uses a program counter for the process and uses state information that is specific to the process to look up the jump target for the jump instruction. Finally, the system uses the jump target returned by the lookup as a predicted jump target for the jump instruction.Type: GrantFiled: June 30, 2006Date of Patent: December 30, 2008Assignee: Sun Microsystems, Inc.Inventors: Edmond H. Yip, Paul Caprioli, Shailender Chaudhry, Jiejun Lu
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Patent number: 7472263Abstract: A branch prediction apparatus includes a branch information receiving unit that receives simultaneously, branch information for each of a plurality of branch instructions that are completed simultaneously, and a parallel branch predicting unit that performs branch prediction in parallel for the branch instructions completed simultaneously, based on the branch information received and a branch history of the respective branch instructions, to obtain branch prediction results.Type: GrantFiled: May 10, 2004Date of Patent: December 30, 2008Assignee: Fujitsu LimitedInventor: Megumi Yokoi
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Publication number: 20080313446Abstract: Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in an instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. Branch instruction predicting section includes a history memory section that stores the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction at either one of a plurality of storing places determined from the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction.Type: ApplicationFiled: August 21, 2008Publication date: December 18, 2008Applicant: FUJITSU LIMITEDInventors: Megumi YOKOI, Masaki Ukai, Takashi Suzuki
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Publication number: 20080313445Abstract: A system to prevent livelock. An outcome of an event is predicted to form an event outcome prediction. The event outcome prediction is compared with a correct value for a datum to be accessed. An instruction is appended with a real event outcome when the outcome of the event is mispredicted to form an appended instruction. A prediction override bit is set on the appended instruction. Then, the appended instruction is executed with the real event outcome.Type: ApplicationFiled: March 19, 2008Publication date: December 18, 2008Inventors: ERIK R. ALTMAN, Vijayalakshmi Srinivasan
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Publication number: 20080307209Abstract: A polymorphic branch predictor and method includes a plurality of branch prediction methods. The methods are selectively enabled to perform branch prediction. A selection mechanism is configured to select one or more of the branch prediction methods in accordance with a dynamic setting to optimize performance of the branch predictor during operation in accordance with a current task.Type: ApplicationFiled: August 19, 2008Publication date: December 11, 2008Inventor: Michael Gschwind
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Patent number: 7461243Abstract: In one embodiment, a processor comprises a branch prediction array, an index generator coupled to the branch prediction array, and a control unit coupled to the index generator. The branch prediction array is configured to store a plurality of branch predictions for conditional branches. The index generator is configured to generate an index to the branch prediction array responsive to at least a portion of a fetch address corresponding to a fetch request that is at a first pipeline stage of the processor and further responsive to a branch history. The control unit is configured to update the branch history responsive to a first fetch request at the first pipeline stage and to defer the update for a second fetch request to a second pipeline stage subsequent to the first pipeline stage.Type: GrantFiled: December 22, 2005Date of Patent: December 2, 2008Assignee: Sun Microsystems, Inc.Inventors: Abid Ali, Jiejun Lu, Brian F. Keish
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Patent number: 7461211Abstract: A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as a prefetcher for predicting accesses to a memory. The prefetcher includes a prediction generator configured to generate a prediction that is unpatternable to an address. Also, the prefetcher also can include a target cache coupled to the prediction generator to maintain the prediction in a manner that determines a priority for the prediction. In another embodiment, the prefetcher can also include a priority adjuster. The priority adjuster sets a priority for a prediction relative to other predictions. In some cases, the placement of the prediction is indicative of the priority relative to priorities for the other predictions. In yet another embodiment, the prediction generator uses the priority to determine that the prediction is to be generated before other predictions.Type: GrantFiled: August 17, 2004Date of Patent: December 2, 2008Assignee: Nvidia CorporationInventors: Ziyad S. Hakura, Brian Keith Langendorf, Stefano A. Pescador, Radoslav Danilak, Brad W. Simeral
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Patent number: 7454602Abstract: A method and apparatus for updating global branch history information are disclosed. A dynamic branch predictor within a data processing system includes a global branch history (GBH) buffer and a branch history table. The GBH buffer contains GBH information of a group of the most recent branch instructions. The branch history table includes multiple entries, each entry is associated with one or more branch instructions. The GBH information from the GBH buffer can be used to index into the branch history table to obtain a branch prediction signal. In response to a fetch group of instructions, a fixed number of GBH bits is shifted into the GBH buffer. The number of GBH bits is the same regardless of the number of branch instructions within the fetch group of instructions. In addition, there is a unique bit pattern associated with the case of no taken branch in the fetch group, regardless of the number of not-taken branches of even if there are any branches in the fetch group.Type: GrantFiled: December 15, 2004Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: Chris M. Abernathy, Jeffrey P. Bradford, Jason N. Dale, Timothy H. Heil
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Patent number: 7454596Abstract: Methods and apparatus for partitioning a microprocessor pipeline to support pipelined branch prediction and instruction fetching of multiple execution threads. A thread selection stage selects a thread from a plurality of execution threads. In one embodiment, storage in a branch prediction output queue is pre-allocated to a portion of the thread in one branch prediction stage in order to prevent stalling of subsequent stages in the branch prediction pipeline. In another embodiment, an instruction fetch stage fetches instructions at a fetch address corresponding to a portion of the selected thread. Another instruction fetch stage stores the instruction data in an instruction fetch output queue if enough storage is available. Otherwise, instruction fetch stages corresponding to the selected thread are invalidated and refetched to avoid stalling preceding stages in the instruction fetch pipeline, which may be fetching instructions of another thread.Type: GrantFiled: June 29, 2006Date of Patent: November 18, 2008Assignee: Intel CorporationInventors: Stephan Jourdan, Robert Hinton
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Publication number: 20080276080Abstract: Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.Type: ApplicationFiled: July 11, 2008Publication date: November 6, 2008Applicant: International Business Machines CorporationInventors: Brian R. Konigsburg, David Stephen Levitan, Wolfram M. Sauer, Samuel Jonathan Thomas
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Publication number: 20080276069Abstract: Predictive decoding is achieved by fetching an instruction, accessing a predictor containing predictor information including prior instruction execution characteristics, obtaining predictor information for the fetched instruction from the predictor; and generating a selected one of a plurality of decode operation streams corresponding to the fetched instruction. The decode operation stream is selected based on the predictor information.Type: ApplicationFiled: May 3, 2007Publication date: November 6, 2008Inventors: Bartholomew Blaner, Michael K. Gschwind
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Patent number: 7447881Abstract: A branch prediction apparatus has a configuration such that a predicted branch target address and an offset are obtained by referring to a branch history, an instruction fetch address and the offset are added to obtain a branch instruction address, the branch instruction address is subtracted from the predicted branch target address to obtain a predicted displacement, and this predicted displacement is compared with a displacement cut-out from an instruction by an instruction decoder, to judge whether the predicted branch target address is correct or not.Type: GrantFiled: January 9, 2003Date of Patent: November 4, 2008Assignee: Fujitsu LimitedInventor: Masaki Ukai
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Patent number: 7447885Abstract: A branch prediction mechanism includes a history value register storing a history value which is used to address into a history buffer from which a plurality of prediction values are read and stored into a prediction value store. The one or more prediction values to be used with a potential branch instruction are selected from the prediction values store using a multiplexer switched by a branch predicting portion of a fetch address. The history buffer is only read when the history value changes whereas the prediction values store is read each time a potential branch instruction is identified requiting a prediction value to be associated with it. The reduced duty cycle of the history buffer saves power.Type: GrantFiled: April 20, 2005Date of Patent: November 4, 2008Assignee: ARM LimitedInventor: Matthew Paul Elwood
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Patent number: 7447884Abstract: A first storage unit stores an address of a branching instruction and a branched address. A first detector detects whether or not an instruction of the present address has previously been branched from an output of the first storage unit. When the first detector detects previous branching of the instruction of the present address, the second storage unit stores the branched address corresponding to the address of the instruction to be executed following the branching instruction. When a second detector detects an output of a program counter as the address of the instruction to be executed following the branching instruction, the second storage unit outputs the branched address.Type: GrantFiled: April 30, 2002Date of Patent: November 4, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Junji Mori, Harutaka Goto
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Publication number: 20080270774Abstract: A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path.Type: ApplicationFiled: April 30, 2007Publication date: October 30, 2008Applicant: Raza Microelectronics, Inc.Inventors: Gaurav Singh, Srivatsan Srinivasan, Ricardo Ramirez, Wei-Hsiang Chen, Hai Ngoc Nguyen
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Publication number: 20080263341Abstract: A data processing apparatus and method are provided for generating prediction data. The data processing apparatus has processing circuitry for performing processing operations including high priority operations and low priority operations, events occurring during performance of those processing operations. Prediction circuitry is responsive to a received event to generate prediction data used by the processing circuitry. The prediction circuitry includes a history storage having a plurality of counter entries for storing count values, and index circuitry for identifying, dependent on the received event, at least one counter entry and for causing the history storage to output the count value stored in that at least one counter entry, with the prediction data being derived from the output count value. Further update control circuitry is provided for modifying at least one count value stored in the history storage in response to update data generated by the processing circuitry.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Applicant: ARM LIMITEDInventors: Emre Ozer, Alastair David Reid, Stuart David Biles
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Publication number: 20080256346Abstract: Provided are a central processing unit (CPU) and method for executing a branch instruction of a CPU, which can protect user's data by preventing an error due to a computer virus and a hacker is provided. The CPU includes: a branch instruction verification unit which verifies whether a branch instruction is valid; and a branch instruction execution unit which executes the branch instruction when the branch instruction is valid. The method includes: verifying whether the branch instruction is valid; and not executing the branch instruction when the branch instruction is invalid.Type: ApplicationFiled: December 27, 2007Publication date: October 16, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Gyung Ho LEE, Tae Joon Park, Byung Chang Kang, Edward Jung, Yixin Shi
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Publication number: 20080256345Abstract: An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.Type: ApplicationFiled: April 10, 2007Publication date: October 16, 2008Applicant: IBM CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, Michael Karl Gschwind, Ravi Nair, Robert Alan Philhower, Wolfram Sauer, Raymond Cheung Yeung
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Publication number: 20080235500Abstract: A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. Instruction branches are predicted taken or not taken using a highly accurate branch history table (BHT). Branches that are predicted not taken are appended to a trace buffer and the next basic block is constructed from the remaining instructions in the fetch buffer. Branches that are predicted taken flush the remaining fetch buffer and the next address is determined using a Branch Target Address Register (BTAC).Type: ApplicationFiled: June 2, 2008Publication date: September 25, 2008Inventors: GORDON T. DAVIS, Richard W. Doing, John D. Jabusch, M. V.V. Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
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Patent number: 7428632Abstract: A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a plurality of compressed representations of these such that when they recur their termination can be predicted. This enables program loops which are longer in length than can be represented within a reasonably sized branch prediction memory to nevertheless be detected and have their loop ends predicted.Type: GrantFiled: March 24, 2005Date of Patent: September 23, 2008Assignee: ARM LimitedInventor: Alexander Nancekievill
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Patent number: 7426631Abstract: Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.Type: GrantFiled: February 2, 2005Date of Patent: September 16, 2008Assignee: International Business Machines CorporationInventors: Brian R. Konigsburg, David Stephen Levitan, Wolfram M. Sauer, Samuel Jonathan Thomas
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Patent number: 7424578Abstract: A compiler apparatus for a computer system capable of improving the hit rate of a cache memory, which includes a prefetch target extraction device, a thread activation process insertion device, and a thread process creation device. The compiler apparatus creates threads for performing prefetch and prepurge. Prefetch and prepurge threads created by this compiler apparatus perform prefetch and prepurge in parallel with the operation of the main program, by taking into consideration program priorities and the usage ratio of the cache memory.Type: GrantFiled: July 8, 2004Date of Patent: September 9, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Nakashima, Taketo Heishi, Shohei Michimoto
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Publication number: 20080215865Abstract: Instruction cache memory having a plurality of memory (for example, cache WAY), means 3 for storing prediction data of a conditional branch of a branch instruction being taken or not taken and for storing prediction data of memory storing the branch instruction data of the plurality of memory when the prediction is the branch being taken, and means for, when an instruction to be executed is a branch instruction, outputting a read active control signal to the plurality of memories 1 by using two pieces of prediction data obtained from the means by an index corresponding to the branch instruction, are comprised.Type: ApplicationFiled: February 29, 2008Publication date: September 4, 2008Applicant: FUJITSU LIMITEDInventors: Mitsuaki Hino, Yasuhiro Yamazaki
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Patent number: 7421572Abstract: A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register (80, 78, 76b) being set or cleared and which specifies which bit of the specified register to use as a branch control bit.Type: GrantFiled: August 31, 2000Date of Patent: September 2, 2008Assignee: Intel CorporationInventors: Gilbert Wolrich, Matthew J. Adiletta, William R. Wheeler, Debra Bernstein, Donald F. Hooper
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Publication number: 20080209173Abstract: An apparatus for executing branch predictor directed prefetch operations. During operation, a branch prediction unit may provide an address of a first instruction to the fetch unit. The fetch unit may send a fetch request for the first instruction to the instruction cache to perform a fetch operation. In response to detecting a cache miss corresponding to the first instruction, the fetch unit may execute one or more prefetch operation while the cache miss corresponding to the first instruction is being serviced. The branch prediction unit may provide an address of a predicted next instruction in the instruction stream to the fetch unit. The fetch unit may send a prefetch request for the predicted next instruction to the instruction cache to execute the prefetch operation. The fetch unit may store prefetched instruction data obtained from a next level of memory in the instruction cache or in a prefetch buffer.Type: ApplicationFiled: February 28, 2007Publication date: August 28, 2008Inventors: Marius Evers, Trivikram Krishnamurthy
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Publication number: 20080201565Abstract: An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.Type: ApplicationFiled: April 24, 2008Publication date: August 21, 2008Applicant: International Business Machines CorporationInventors: Jeffrey Powers Bradford, Harold F. Kossman, Timothy John Mullins
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Publication number: 20080189532Abstract: A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback. The maximum data rate that may be achieved by the disclosed reduced state Viterbi detectors is improved by precomputing a number of candidate branch metrics and performing pipelined selection of an appropriate branch metric. A reduced state Viterbi detector is thus disclosed that precomputes branch metrics for speculative sequences of one or more channel symbols; selects one of said precomputed branch metrics based on at least one decision from at least one corresponding state using at least two pipeline registers; and selects a path having a best path metric for a given state.Type: ApplicationFiled: April 11, 2008Publication date: August 7, 2008Inventor: Erich Franz Haratsch
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Publication number: 20080184018Abstract: Systems, methods, and apparatuses including computer program products for speculative throughput computing are disclosed. Speculative throughput computing is used to execute program segments in parallel.Type: ApplicationFiled: January 30, 2008Publication date: July 31, 2008Applicant: NEMA LABS ABInventors: Alexander Busck, Mikael Engbom, Per Stenstrom, Fredrik Warg
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Patent number: 7404070Abstract: A computer system comprises a processor that comprises a hardware branch predictor and software instructions executed by the processor. The software instructions comprise conditional branch instructions and separate static branch prediction instructions. The static branch prediction instructions comprise a plurality of groups of static branch prediction bits, each group being configurable to provide prediction information for a separate conditional branch instruction.Type: GrantFiled: November 28, 2000Date of Patent: July 22, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Harish G. Patil, Joel S. Emer, Stephen Felix
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Publication number: 20080162908Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure comprises a processor. The processor comprises a cache, an execution unit, and circuitry. The circuitry is configured to receive a branch instruction from the cache to be executed in a program order. The circuitry is further configured to, before execution of the branch instruction in the program order, issue the branch instruction to the execution unit to determine a predicted outcome of the branch instruction, and use the predicted outcome of the branch instruction to schedule execution of one or more instructions succeeding the branch instruction in the program order.Type: ApplicationFiled: March 14, 2008Publication date: July 3, 2008Inventor: DAVID A. LUICK
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Patent number: 7380110Abstract: An efficient branch prediction structure is described that bifurcates a branch prediction structure into at least two portions where information stored in the second portion is aliased amongst multiple entries of the first portion. In this way, overall storage (and layout area) can be reduced and scaling with a branch prediction structure that includes a (2N)K×1 branch direction entries and a (N/2)K×1 branch prediction qualifier entries is less dramatic than conventional techniques. An efficient branch prediction structure includes entries for branch direction indications and entries for branch prediction qualifier indications. The branch direction indication entries are more numerous than the branch prediction qualifier entries.Type: GrantFiled: September 11, 2003Date of Patent: May 27, 2008Assignee: Sun Microsystems, Inc.Inventors: Robert D. Nuckolls, Rabin A. Sugumar, Chandra M. R. Thimmannagari
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Patent number: 7380111Abstract: A method for processing registers in an out-of-order processor. A predicate in an instruction is predicted. An architecturally correct value is then computed using a read-modify-write operation. The predicted value is compared to the architecturally correct value. The instruction with an incorrectly-predicted predicate is flushed from the pipeline if the predicted value and the architecturally correct value are different.Type: GrantFiled: July 8, 2004Date of Patent: May 27, 2008Assignee: Intel CorporationInventors: Edward T. Grochowski, Jared W. Stark
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Publication number: 20080120496Abstract: A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.Type: ApplicationFiled: November 17, 2006Publication date: May 22, 2008Inventors: Jeffrey P. Bradford, Richard W. Doing, Richard J. Eickemeyer, Wael R. El-Essawy, Douglas R. Logan, Balaram Sinharoy, William E. Speight, Lixin Zhang
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Publication number: 20080077781Abstract: A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.Type: ApplicationFiled: September 27, 2006Publication date: March 27, 2008Inventors: Rodney Wayne Smith, Brian Michael Stempel, James Norris Dieffenderfer, Thomas Andrew Sartorius
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Publication number: 20080072024Abstract: Methods and apparatus to perform efficient branch prediction operations are described. In one embodiment, branch prediction may be performed by utilizing a combination of a bimodal predictor, a plurality of global predictors, and a loop predictor. Other embodiments are also described.Type: ApplicationFiled: September 14, 2006Publication date: March 20, 2008Inventors: Mark C. Davis, Robert Hinton, Boyd Phelps
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Patent number: 7346737Abstract: A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The BTAC access bits represent a presence of a branch instruction on the next cache line of a cache line corresponding to the instruction cache. The BTAC is selectively accessed in accordance with values of the BTAC access bits corresponding to I'th (I is a positive integer) cache lines presently accessed in the instruction cache.Type: GrantFiled: April 26, 2005Date of Patent: March 18, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Hoi-Jin Lee
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Patent number: 7343481Abstract: A data processing system incorporates an instruction prefetch unit 8 including a static branch predictor 12. A static branch prediction cache 30, 32, 34 is provided for storing a most recently encountered static branch prediction such that a subsequent request to fetch the already encountered branch instruction can be identified before the opcode for that branch instruction is returned. The cached static branch prediction can thus redirect the prefetching to the branch target address sooner than the static predictor 12.Type: GrantFiled: March 19, 2003Date of Patent: March 11, 2008Assignee: ARM LimitedInventor: David James Williamson
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Publication number: 20080059779Abstract: In one embodiment, the present invention includes a method for determining if an entry corresponding to a prediction address is present in a first predictor, and overriding a prediction output from a second predictor corresponding to the prediction address if the entry is present in the first predictor. Other embodiments are described and claimed.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Inventors: Mark C. Davis, Stephan Jourdan, Robert L. Hinton, Boyd S. Phelps
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Publication number: 20080052499Abstract: Hardware and/or software countermeasures are provided to reduce or eliminate vulnerabilities due to the observable and/or predictable states and state transitions of microprocessor components such as instruction cache, data cache, branch prediction unit(s), branch target buffer(s) and other components. For example, for branch prediction units, various hardware and/or software countermeasures are provided to reduce vulnerabilities in the branch prediction unit (BPU) and to protect against the security vulnerabilities due the observable and/or predictable states and state transitions during BPU operations.Type: ApplicationFiled: July 9, 2007Publication date: February 28, 2008Inventor: Cetin Kaya Koc
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Patent number: 7337271Abstract: A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.Type: GrantFiled: December 1, 2003Date of Patent: February 26, 2008Assignee: International Business Machines CorporationInventors: Philip George Emma, Allan Mark Hartstein, Brian R. Prasky, Thomas Roberts Puzak, Moinuddin Khalil Ahmed Qureshi, Vijayalakshmi Srinivasan
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Patent number: 7334143Abstract: A computer measures a processor load and configures itself so that a lesser amount of speculative execution is enabled when the processor is lightly loaded than is enabled when the processor is heavily loaded.Type: GrantFiled: April 19, 2004Date of Patent: February 19, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventor: Lee W Atkinson
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Patent number: 7334115Abstract: The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.Type: GrantFiled: June 30, 2000Date of Patent: February 19, 2008Assignee: Intel CorporationInventors: Reynold V. D'Sa, Alan B. Kyker, Slade A. Morgan, Rebecca E. Hebda, Richard A. Weier, Robert F. Krick
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Patent number: 7320066Abstract: A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack stores, when an execution of a call instruction of a subroutine is completed, address information of a return destination of a corresponding return instruction. A second return address stack stores, when presence of a call instruction of a subroutine is predicted, address information of a return destination of a corresponding return instruction. An output selecting unit selects, when presence of a return instruction is predicted, if address information is stored in the second return address stack, the address information as a result of the branch prediction with a highest priority, and outputs the address information selected.Type: GrantFiled: February 25, 2005Date of Patent: January 15, 2008Assignee: Fujitsu LimitedInventor: Megumi Yokoi
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Publication number: 20080005544Abstract: Methods and apparatus for partitioning a microprocessor pipeline to support pipelined branch prediction and instruction fetching of multiple execution threads. A thread selection stage selects a thread from a plurality of execution threads. In one embodiment, storage in a branch prediction output queue is pre-allocated to a portion of the thread in one branch prediction stage in order to prevent stalling of subsequent stages in the branch prediction pipeline. In another embodiment, an instruction fetch stage fetches instructions at a fetch address corresponding to a portion of the selected thread. Another instruction fetch stage stores the instruction data in an instruction fetch output queue if enough storage is available. Otherwise, instruction fetch stages corresponding to the selected thread are invalidated and refetched to avoid stalling preceding stages in the instruction fetch pipeline, which may be fetching instructions of another thread.Type: ApplicationFiled: June 29, 2006Publication date: January 3, 2008Inventors: Stephan Jourdan, Robert Hinton
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Publication number: 20080005543Abstract: A multiple stage branch prediction system including a branch target address cache (BTAC) and a branch predictor circuit is disclosed. The BTAC is configured to store a BTAC entry. The branch predictor circuit is configured to store state information. The branch predictor circuit utilizes the state information to predict the direction of a branch instruction and to manage the BTAC entry based on the stored state information in response to actual resolution of the branch instruction.Type: ApplicationFiled: June 29, 2006Publication date: January 3, 2008Inventor: Bohuslav Rychlik
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Publication number: 20080005545Abstract: One embodiment of the present invention provides a system that predicts a jump target for a jump instruction. During operation, the system starts fetching the jump instruction while executing a process. Next, the system uses a program counter for the process along with process state information to look up the jump target for the jump instruction. Finally, the system uses the jump target returned by the lookup as a predicted jump target for the jump instruction.Type: ApplicationFiled: June 30, 2006Publication date: January 3, 2008Inventors: Edmond H. Yip, Paul Caprioli, Shailender Chaudhry, Jiejun Lu