History Table Patents (Class 712/240)
  • Patent number: 10540181
    Abstract: Instructions are executed in a pipeline of a processor, where each instruction is associated with a particular context. A first storage stores branch prediction information characterizing results of branch instructions previously executed. The first storage is dynamically partitioned into partitions of one or more entries. Dynamically partitioning includes updating a partition to include an additional entry by associating the additional entry with a particular subset of one or more contexts. A predicted branch result is determined based on at least a portion of the branch prediction information. An actual branch result provided based on an executed branch instruction is used to update the branch prediction information. Providing a predicted branch result for a first branch instruction includes retrieving a first entry from a first partition based at least in part on an identified first subset of one or more contexts associated with the first branch instruction.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: January 21, 2020
    Assignee: Marvell World Trade Ltd.
    Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, David Kravitz, Edward McLellan, Rabin Sugumar
  • Patent number: 10534612
    Abstract: Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Carlos Cavanna, Reid Copeland, Chad McIntyre, Ali Sheikh
  • Patent number: 10515217
    Abstract: Technologies for control flow validation a computing device having a processor with real-time instruction tracing support. The processor generates trace data indicative of control flow of a protected application. The computing device identifies an indirect branch target based on the trace data and determines whether the indirect branch target is included in the same module as a previous indirect branch target. If the indirect branch target and the previous indirect branch target are not included in the same module, the computing device determines whether an inter-module transfer policy is satisfied. If satisfied, the indirect branch target is stored as the previous indirect branch target and the protected application continues to execute. If the policy is not satisfied, the computing device generates an exception. The policy may be satisfied, for example, if the indirect branch target is an exported function. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Mingwei Zhang, Salmin Sultana, Ravi L. Sahita
  • Patent number: 10296337
    Abstract: Methods and apparatus for preventing premature reads from a general purpose register (GPR) including receiving an instruction comprising a source operand identifying a source GPR entry; setting a read-enabled flag based on a value in a particular entry of a source ready vector; if the read-enabled flag indicates data in the source GPR entry is ready for reading, dispatching the received instruction, including performing a read operation of the data in the source GPR entry; and if the read-enabled flag indicates data in the source GPR entry is not ready for reading, dispatching the received instruction without performing a read operation of the data in the source GPR entry.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
  • Patent number: 10289604
    Abstract: Aspects of the present invention provide a memory system comprising a plurality of stacked memory layers, each memory layer divided into memory sections, wherein each memory section connects to a neighboring memory section in an adjacent memory layer, and a logic layer stacked among the plurality of memory layers, the logic layer divided into logic sections, each logic section including a memory processing core, wherein each logic section connects to a neighboring memory section in an adjacent memory layer to form a memory vault of connected logic and memory sections, and wherein each logic section is configured to communicate directly or indirectly with a host processor. Accordingly, each memory processing core may be configured to respond to a procedure call from the host processor by processing data stored in its respective memory vault and providing a result to the host processor. As a result, increased performance may be provided.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: May 14, 2019
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Karthikeyan Sankaralingam, Jaikrishnan Menon, Lorenzo De Carli
  • Patent number: 10261798
    Abstract: Methods and indirect branch predictor logic units to predict the target addresses of indirect branch instructions. The method comprises storing in a table predicted target addresses for indirect branch instructions indexed by a combination of the indirect path history for previous indirect branch instructions and the taken/not-taken history for previous conditional branch instructions. When a new indirect branch instruction is received for prediction, the indirect path history and the taken/not-taken history are combined to generate an index for the indirect branch instruction. The generated index is then used to identify a predicted target address in the table. If the identified predicted target address is valid, then the target address of the indirect branch instruction is predicted to be the predicted target address.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: April 16, 2019
    Assignee: MIPS Tech, LLC
    Inventor: Manouk Manoukian
  • Patent number: 10204175
    Abstract: At a cache manager of a directed acyclic graph-based data analytic platform, memory usage statistics are obtained from each of a plurality of monitor components on a plurality of worker nodes. The worker nodes have a plurality of tasks executing thereon, and each of the tasks has at least one distributed dataset associated therewith. Each of the worker nodes has a distributed dataset cache. At least one of the following is carried out: increasing a size of a given one of the distributed dataset caches if the memory usage statistics indicate that corresponding ones of the tasks are using too little memory; and decreasing a size of another given one of the distributed dataset caches if the memory usage statistics indicate contention between corresponding ones of the tasks and a corresponding one of the distributed datasets.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenhua Hu, Min Li, Luna Xu, Yandong Wang, Li Zhang
  • Patent number: 10175982
    Abstract: A method and system for storing branch information is disclosed. First data may be stored in a first entry of a first table in response to a determination that a fetched instruction is a branch instruction. Second data that is dependent upon at least one previously taken branch may be stored in a second entry in a second table in response to a determination that a branch associated with the instruction is predicted to be taken. The first data may be updated to include an index to the second data in response to the determination that the branch is predicted to be taken.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: January 8, 2019
    Assignee: Apple Inc.
    Inventors: Conrado Blasco, Ian D. Kountanis
  • Patent number: 10108424
    Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 23, 2018
    Assignee: Nvidia Corporation
    Inventors: Nathan Tuck, Alexander Klaiber, Ross Segelken, David Dunn, Ben Hertzberg, Rupert Brauch, Thomas Kistler, Guillermo J. Rozas, Madhu Swarna
  • Patent number: 9921846
    Abstract: This disclosure includes a method for performing branch prediction by a processor having an instruction pipeline. The processor speculatively updates a global history register having fetch group history and branch history, fetches a fetch group of instructions, and assigns a global history vector to the instructions. The processor predicts any branches in the fetch group using the global history vector and a predictor, and evaluates whether the fetch group contains a predicted taken branch. If the fetch group contains a predicted taken branch, the processor flushes subsequently fetched instructions in the pipeline following the predicted taken branch, repairs the global history register to the global history vector, and updates the global history register based on branch prediction information. If the fetch group does not contain a predicted taken branch, the processor updates the global history register with a branch history value for each branch in the fetch group.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Heil, Andrew D. Hilton
  • Patent number: 9904551
    Abstract: Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: David S. Levitan, Jose E. Moreira, Mauricio J. Serrano
  • Patent number: 9898287
    Abstract: A method, a non-transitory computer readable medium, and a processor for repacking dynamic wavefronts during program code execution on a processing unit, each dynamic wavefront including multiple threads are presented. If a branch instruction is detected, a determination is made whether all wavefronts following a same control path in the program code have reached a compaction point, which is the branch instruction. If no branch instruction is detected in executing the program code, a determination is made whether all wavefronts following the same control path have reached a reconvergence point, which is a beginning of a program code segment to be executed by both a taken branch and a not taken branch from a previous branch instruction. The dynamic wavefronts are repacked with all threads that follow the same control path, if all wavefronts following the same control path have reached the branch instruction or the reconvergence point.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: February 20, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sooraj Puthoor, Bradford M. Beckmann, Dmitri Yudanov
  • Patent number: 9898294
    Abstract: Embodiments relate to selectively blocking branch instruction predictions. An aspect includes computer implemented method for performing selective branch prediction. The method includes detecting, by a processor, a branch-prediction blocking instruction in a stream of instructions and blocking, by the processor, branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Ulrich Mayer, Anthony Saporito, Chung-Lung K. Shum, Timothy Slegel
  • Patent number: 9898295
    Abstract: Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: David S. Levitan, Jose E. Moreira, Mauricio J. Serrano
  • Patent number: 9891922
    Abstract: Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: February 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Ulrich Mayer, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9891923
    Abstract: A loop predictor trains a branch instruction to determine a trained loop count of a loop. When the loop fits in an instruction buffer, the processor stops fetching from an instruction cache, sends the loop instructions to an execution engine from the buffer without fetching from the cache, maintains a loop pop count of times the branch is sent to the execution engine from the buffer, and predicts the branch instruction is taken when the loop pop count is less than the trained loop count and otherwise predicts not taken.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: February 13, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Guo Hua Chen, Meng Chen Yang, Xin Yu Gao, Fan Gong Gong, Zhen Hua Huang
  • Patent number: 9891918
    Abstract: A microprocessor includes a predicting unit having storage for holding a prediction history of characteristics of instructions previously executed by the microprocessor. The predicting unit accumulates the prediction history and uses the prediction history to make predictions related to subsequent instruction executions. The storage comprises a plurality of portions separately controllable for accumulating the prediction history. The microprocessor also includes a control unit that detects the microprocessor is running an operating system routine and controls the predicting unit to use only a fraction of the plurality of portions of the storage to accumulate the prediction history while the microprocessor is running the operating system routine.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: February 13, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Rodney E. Hooker, Terry Parks, John D. Bunda
  • Patent number: 9858081
    Abstract: This disclosure includes a method for performing branch prediction by a processor having an instruction pipeline. The processor speculatively updates a global history register having fetch group history and branch history, fetches a fetch group of instructions, and assigns a global history vector to the instructions. The processor predicts any branches in the fetch group using the global history vector and a predictor, and evaluates whether the fetch group contains a predicted taken branch. If the fetch group contains a predicted taken branch, the processor flushes subsequently fetched instructions in the pipeline following the predicted taken branch, repairs the global history register to the global history vector, and updates the global history register based on branch prediction information. If the fetch group does not contain a predicted taken branch, the processor updates the global history register with a branch history value for each branch in the fetch group.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Heil, Andrew D. Hilton
  • Patent number: 9851979
    Abstract: A split level history buffer in a central processing unit is provided. A first instruction and a second instruction are fetched, tagged, and the first instruction is stored an entry of a register file. The first instruction is evicted from the entry and the second instruction is stored in the entry. If the first instruction is evicted, then the first instruction is stored in a first portion of a history buffer. If a result for the first instruction is generated, then the first instruction is moved to a second portion of the history buffer and the result is stored with the first instruction in the second portion of the history buffer. If it is determined that a third instruction evicts the second instruction from the entry, then the second instruction is stored in the first portion of the history buffer.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 9792123
    Abstract: Methods and indirect branch predictor logic units to predict the target addresses of indirect branch instructions. The method comprises storing in a table predicted target addresses for indirect branch instructions indexed by a combination of the indirect path history for previous indirect branch instructions and the taken/not-taken history for previous conditional branch instructions. When a new indirect branch instruction is received for prediction, the indirect path history and the taken/not-taken history are combined to generate an index for the indirect branch instruction. The generated index is then used to identify a predicted target address in the table. If the identified predicted target address is valid, then the target address of the indirect branch instruction is predicted to be the predicted target address.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: October 17, 2017
    Assignee: Imagination Technologies LImited
    Inventor: Manouk Manoukian
  • Patent number: 9733943
    Abstract: A branch history table cache is a write cache that stores values of branch history counters written to a branch history table. An update to a branch history table counter is reflected in both the branch history table cache and the branch history table. Before a branch history table counter is updated, a check is made to see if the branch history table counter is in the cache. If not, the branch history table counter is updated based on a value of the branch history table counter that was saved during fetch of the branch history table counter. If, however, the branch history table counter value is in the cache, the value in the cache is used to update the branch history table counter. All branches that use the branch history table counter update the correct counter value, improving processor performance by providing more accurate predictions of branches taken.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Heil, Brent F. Hilgart, Andrew D. Hilton
  • Patent number: 9652356
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: May 16, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
  • Patent number: 9639370
    Abstract: Techniques relate to dynamic branch history pattern adjustment. Past histories of branch instruction results are collected as part of a branch history pattern. A branch prediction structure with a pattern history buffer predicts a direction of a branch instruction using the branch history pattern. The branch prediction structure executes one or more branch history pattern recording adjustment instructions prior to one or more branch instructions. Executing the one or more branch history pattern recording adjustment instructions changes default behaviors of recording and usage of the branch history pattern.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 2, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Karl Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9594564
    Abstract: An arithmetic processing device includes: first prediction units which output branch prediction information of a fetched conditional branch instruction based on past branch history information of conditional branch instructions; a second prediction unit which stores a branch taken consecutive number of times and a branch not-taken consecutive number of times to a pattern information storage unit, and outputs branch prediction information of a fetched conditional branch instruction based on the past branch taken consecutive number of times or branch not-taken consecutive number of times stored; selecting units which selectively output the branch prediction information output from the first prediction units or the second prediction unit; and a selector which outputs a next instruction address of the conditional branch instruction or a branch target address of the conditional branch instruction to an instruction fetch unit in accordance with the branch prediction information output by the selecting units.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: March 14, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kotaro Kuwahara, Takashi Suzuki
  • Patent number: 9535703
    Abstract: A predictor data structure is used for pipelined processing by a pipelined processor. The predictor data structure includes a predicted address to be used in return from execution of a selected instruction, and a predicted operating state associated with the predicted address. Based on determining a selected return instruction is to be executed, the predicted address to which processing is to be returned is obtained from the predictor data structure. Further, based on determining the selected return instruction is to be executed, a transitional operating state to be entered based on the predicted operating state stored in the predictor data structure is predicted, wherein at least one of the predicted address and the predicted transitional operating state are to be used to validate execution of the selected return instruction.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: January 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 9513924
    Abstract: A predictor data structure is used for pipelined processing by a pipelined processor. The predictor data structure includes a predicted address to be used in return from execution of a selected instruction, and a predicted operating state associated with the predicted address. Based on determining a selected return instruction is to be executed, the predicted address to which processing is to be returned is obtained from the predictor data structure. Further, based on determining the selected return instruction is to be executed, a transitional operating state to be entered based on the predicted operating state stored in the predictor data structure is predicted, wherein at least one of the predicted address and the predicted transitional operating state are to be used to validate execution of the selected return instruction.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 9507597
    Abstract: A microprocessor includes a predicting unit and a control unit. The control unit controls the predicting unit to accumulate a history of characteristics of executed instructions and makes predictions related to subsequent instructions based on the history while the microprocessor is running a first thread. The control unit also detects a transition from running the first thread to running a second thread and controls the predicting unit to selectively suspend accumulating the history and making the predictions using the history while running the second thread. The predicting unit makes static predictions while running the second thread. The selectivity may be based on the privilege level, identity or length of the second thread, static prediction effectiveness during a previous execution instance of the thread, whether the transition was made due to a system call, and whether the second thread is an interrupt handler.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: November 29, 2016
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Rodney E. Hooker, Terry Parks, John Michael Greer
  • Patent number: 9495164
    Abstract: Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: November 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: David S. Levitan, Jose E. Moreira, Mauricio J. Serrano
  • Patent number: 9465615
    Abstract: A branch prediction unit BPU (500) for prediction of a next taken branch instruction in a processing unit (100). The BPU (500) comprises a pattern history memory (504) comprising branch source addresses and branch indicators; a branch target buffer (506) comprising branch targets; and branch prediction logical circuit (502). By means of a search PC, the circuit finds in the memory a branch indicator indicating a predicted taken branch instruction. The circuit selects a first found branch indicator as an indication of a first predicted taken branch instruction. Using the first found branch indicator, the circuit retrieves from the memory, a branch source address of the first predicted taken branch instruction. When the retrieved branch source address is the branch source address nearest to the search PC, the circuit outputs as next PC a branch target retrieved from the buffer. Then the prediction stops.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: October 11, 2016
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Jean-Paul Smeets, Erik Rijshouwer
  • Patent number: 9395994
    Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Xiaowei Jiang, Srihari Makineni, Zhen Fang, Dmitri Pavlov, Ravi Iyer
  • Patent number: 9389860
    Abstract: A method of predicting a backward conditional branch instruction used in a vector partitioning loop includes detecting the first conditional branch instruction that occurs after consumption of a dependency index vector by a predicate generating instruction. The dependency index vector includes information indicative of a number of iterations of the vector partitioning loop, and the conditional branch instruction may branch backwards when taken. The conditional branch instruction may then be predicted to be taken a number of times that is determined by the dependency index vector.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: July 12, 2016
    Assignee: Apple Inc.
    Inventor: Jeffry E. Gonion
  • Patent number: 9378017
    Abstract: A machine readable storage medium containing program code is described that when processed by a processor causes a method to be performed. The method includes creating a resultant rolled version of an input vector by forming a first intermediate vector, forming a second intermediate vector and forming a resultant rolled version of an input vector. The first intermediate vector is formed by barrel rolling elements of the input vector along a first of two lanes defined by an upper half and a lower half of the input vector. The second intermediate vector is formed by barrel rolling elements of the input vector along a second of the two lanes. The resultant rolled version of the input vector is formed by incorporating upper portions of one of the intermediate vector's upper and lower halves as upper portions of the resultant's upper and lower halves and incorporating lower portions of the other intermediate vector's upper and lower halves as lower portions of the resultant's upper and lower halves.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: June 28, 2016
    Assignee: Intel Corporation
    Inventors: Tal Uliel, Boris Bolshem, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 9367314
    Abstract: A processor is operable to process conditional branches. The processor includes instruction fetch logic to fetch a conditional short forward branch. The conditional short forward branch is to include a conditional branch instruction and a set of one or more instructions that are to sequentially follow the conditional branch instruction in program order. The set of the one or more instructions are between the conditional branch instruction and a forward branch target instruction that is to be indicated by the conditional branch instruction. The processor also includes instruction conversion logic coupled with the instruction fetch logic. The instruction conversion logic is to convert the conditional short forward branch to a computationally equivalent set of one or more predicated instructions. Other processors are also disclosed, as are various methods and systems.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 14, 2016
    Assignee: Intel Corporation
    Inventors: Edward Thomas Grochowski, Martin Guy Dixon, Yazmin A. Santiago, Mishali Naik
  • Patent number: 9342433
    Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device and an LBR structure communicably coupled to the LBR counter. The LBR structure comprises a plurality of LBR entries. Furthermore, an LBR entry of the plurality of LBR entries comprises an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter when the LBR entry is created.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Ahmad Yasin, Michael W. Chynoweth, Ofer Levy, Jason W. Brandt, Angela Schmid
  • Patent number: 9274795
    Abstract: A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not perform the operation. A predictor provides a prediction about a conditional non-branch instruction. An instruction translator translates the conditional non-branch instruction into a no-operation microinstruction when the prediction predicts the condition will not be satisfied, and into a set of one or more microinstructions to unconditionally perform the operation when the prediction predicts the condition will be satisfied. An execution pipeline executes the no-operation microinstruction or the set of microinstructions. The predictor translates into a second set of one or more microinstructions to conditionally perform the operation when the prediction does not make a prediction.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: March 1, 2016
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Terry Parks, Rodney E. Hooker
  • Patent number: 9262169
    Abstract: Embodiments relate to branch prediction table install source tracking. An aspect includes a system for branch prediction table install source tracking. The system includes memory configured to store instructions accessible by a processor. The processor includes a branch target buffer, where the processor is configured to perform a method. The method includes receiving at the branch target buffer a request to install a branch target buffer entry corresponding to a branch instruction for branch prediction, and identifying a source of the request as an install source of the branch target buffer entry. The method further includes storing an install source identifier in the branch target buffer based on the install source.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Brian R. Prasky
  • Patent number: 9256436
    Abstract: Embodiments relate to branch prediction table install source tracking. An aspect includes a computer-implemented method for branch prediction table install source tracking. The method includes receiving at a branch target buffer a request to install a branch target buffer entry corresponding to a branch instruction for branch prediction. The method further includes identifying, by a computer, a source of the request as an install source of the branch target buffer entry. The method also includes storing, by the computer, an install source identifier in the branch target buffer based on the install source.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Brian R. Prasky
  • Patent number: 9152425
    Abstract: Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: October 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Brian R. Prasky, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 9152424
    Abstract: Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: October 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Brian R. Prasky, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 9146739
    Abstract: Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Marcel Mitran, Brian R. Prasky, Joran Siu, Timothy J. Slegel, Alexander Vasilevskiy
  • Patent number: 9141388
    Abstract: A digital system includes a processor core and a cache control unit. The processor core can be coupled to a first memory containing data and a second memory with a faster speed than the first memory, and is configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register. The cache control unit is configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data, and is further configured to examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information and to create a track corresponding to the segment of instructions based on the extracted instruction information.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: September 22, 2015
    Assignee: SHANGHAI XIN HAO MICRO ELECTRONICS CO., LTD.
    Inventors: Kenneth Chenghao Lin, Haoqi Ren
  • Patent number: 9141553
    Abstract: A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: September 22, 2015
    Assignee: SHANGHAI XIN HAO MICRO ELECTRONICS CO. LTD.
    Inventors: Kenneth Chenghao Lin, Haoqi Ren
  • Patent number: 9135012
    Abstract: Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: September 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: James J. Bonanno, Adam B. Collura, Ulrich Mayer, Brian R. Prasky, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 9116686
    Abstract: A method for suppressing prediction of a backward branch instruction used in a vector partitioning loop includes detecting the first backward branch instruction that occurs after a predicate generating instruction. The predicate generating instruction generates a predicate vector that is dependent upon a dependency vector where each element of the dependency vector indicates whether a data dependency exists between elements of a vector instruction. The method also includes receiving an indication of a prediction accuracy of a prediction of the backward branch instruction. If the prediction accuracy does not satisfy a threshold value, the prediction of the backward branch instruction is suppressed until the dependency vector on which the predicate-generating instruction depends is available.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: August 25, 2015
    Assignee: Apple Inc.
    Inventor: Jeffry E. Gonion
  • Patent number: 9110683
    Abstract: While fetching the instructions from a loop in program code, a processor calculates a number of times that a backward-branching instruction at the end of the loop will actually be taken when the fetched instructions are executed. Upon determining that the backward-branching instruction has been predicted taken more than the number of times that the branch instruction will actually be taken, the processor immediately commences a mispredict operation for the branch instruction, which comprises: (1) flushing fetched instructions from the loop that will not be executed from the processor, and (2) commencing fetching instructions from an instruction following the branch instruction.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: August 18, 2015
    Assignee: APPLE INC.
    Inventor: Jeffry E. Gonion
  • Patent number: 9092618
    Abstract: A method for making secure execution of a computer program includes a set of at least one instruction, characterized in that it includes: a first step which consists in calculating and storing, prior to execution of the computer program, a first signature representing the expected execution of the set of instructions; a second step which consists in calculating and storing, during execution of the set of instructions, a second signature representing the execution of the set of instructions; and a step which consists in detecting an anomaly of execution of the set of instructions from the first and second signatures.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: July 28, 2015
    Assignee: OBERTHUR TECHNOLOGIES
    Inventors: Jean-Bernard Fischer, Paul Dischamp
  • Patent number: 9032191
    Abstract: A hypervisor and one or more guest operating systems resident in a data processing system and hosted by the hypervisor are configured to selectively enable or disable branch prediction logic through separate hypervisor-mode and guest-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic for different operating scenarios.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Adam J. Muff, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs
  • Patent number: 9032174
    Abstract: A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventor: Naoki Nishiguchi
  • Patent number: 8990545
    Abstract: This is a program analysis technique using a branch history table (BHT). Upon start of a program, a plurality of flags, each corresponding to an instruction of the program, are initialized to a disabled state and an initial state of a BHT is stored. Upon execution of a branch instruction, if a branch has not been taken, a value of history information of a corresponding entry of the BHT is decremented. If the branch has been taken, the value of the history information of the corresponding entry is incremented and whether a corresponding flag is enabled or disabled is determined. If the corresponding flag is disabled, the flag is enabled. Upon termination of the program, a differential history information value of each entry is obtained from the stored initial state and a final state of the BHT. A final state of each flag is obtained.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Kenta Nakamura
  • Patent number: 8977816
    Abstract: A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a part of the valid data may be transmitted to a plurality of member disks. That is, all of the valid data or the specific data may exist in the cache only, and may be deleted from the plurality of member disks. Accordingly, the plurality of member disks may secure more space, an internal copy overhead may be reduced, and more particularly, solid state disks may achieve better performance.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 10, 2015
    Assignee: OCZ Storage Solutions Inc.
    Inventor: Soo Gil Jeong