Abstract: Techniques are disclosed relating to predicting values for load operations. In some embodiments, front-end circuitry is configured to predict values of load operations based on multiple value tagged geometric length predictor (VTAGE) prediction tables (based on program counter information and branch history information). Training circuitry may adjust multiple VTAGE learning tables based on completed load operations. Control circuitry may pre-compute access information (e.g., an index) for a VTAGE learning table for a load based on branch history information that is available to the front-end circuitry but that is unavailable to the training circuitry, store the pre-computed access information, and provide the pre-computed access information from the first storage circuitry to the training circuitry to access the VTAGE learning table based on completion of the load. This may facilitate VTAGE training without pipelining the branch history information.

Abstract: An exemplary branch predictor apparatus comprises a Pattern History Table (PHT) configured with a PHT allocation multiplexer/demultiplexer (PAMD) configurable to output a prediction logically selected from a portion of the PHT entries selectively allocated among a plurality of threads. The PHT entries may be allocated among a plurality of threads based on control bits read from a Control and Status Register (CSR) at system initialization. The branch predictor may govern a plurality of threads fetching instructions from an address selected from a Branch Target Buffer (BTB) entry indexed based on a per-thread Program Counter (PC) or a PHT entry indexed based on a per-thread Global History Register (GBHR). The PHT entries may be saturating binary counters. The saturating counters may be two-bit counters. An exemplary implementation may permit reduced misprediction rate, increased throughput, or reduced energy consumption resulting from increased allocation of PHT entries to more branch-intensive threads.

Abstract: Disclosed techniques relate to work distribution in graphics processors. In some embodiments, an apparatus includes circuitry that implements a plurality of logical slots and a set of graphics processor sub-units that each implement multiple distributed hardware slots. The circuitry may determine different distribution rules for first and second sets of graphics work and map logical slots to distributed hardware slots based on the distribution rules. In various embodiments, disclosed techniques may advantageously distribute work efficiently across distributed shader processors for graphics kicks of various sizes.

Abstract: Apparatus and methods for training a neural network accelerator using quantized precision data formats are disclosed, and in particular for storing activation values from a neural network in a compressed format having lossy or non-uniform mantissas for use during forward and backward propagation training of the neural network. In certain examples of the disclosed technology, a computing system includes processors, memory, and a compressor in communication with the memory. The computing system is configured to perform forward propagation for a layer of a neural network to produced first activation values in a first block floating-point format. In some examples, activation values generated by forward propagation are converted by the compressor to a second block floating-point format having a non-uniform and/or lossy mantissa. The compressed activation values are stored in the memory, where they can be retrieved for use during back propagation.

Abstract: Techniques are disclosed relating to load value prediction. In some embodiments, a processor includes learning table circuitry that is shared for both address and value prediction. Loads may be trained for value prediction when they are eligible for both value and address prediction. Entries in the learning table may be promoted to an address prediction table or a load value prediction table for prediction, e.g., when they reach a threshold confidence level in the training table. In some embodiments, the learning table stores a hash of a predicted load value and control circuitry uses a probing load to retrieve the actual predicted load value for the value prediction table.

Abstract: A multiprocessor system includes a plurality of processors, a first cache device corresponding to a first processor of the plurality of processors and including a first cache memory configured to store a plurality of first cache lines, and a second cache device at different level than the first cache device, corresponding to the plurality of processors, and including a second cache memory that stores a plurality of second cache lines, in which the first cache device is configured to, in response to a request related to data access, search the first cache memory for data, and the second cache device is configured to, in response to the data cache-missed in the first cache memory, search the second cache memory for data, and in response to the data cache-hit in the second cache memory, set cache line of the second cache memory corresponding to the data as clean cache line.

Abstract: A prediction unit includes a single-cycle predictor (SCP) configured to provide a series of outputs associated with a respective series of fetch blocks on a first respective series of clock cycles and a fetch block prediction unit (FBPU) configured to use the series of SCP outputs to provide, on a second respective series of clock cycles, a respective series of fetch block descriptors that describe the respective series of fetch blocks. The fetch block descriptors are useable by an instruction fetch unit to fetch the series of fetch blocks from an instruction cache. The second respective series of clock cycles follows the first respective series of clock cycles in a pipelined fashion by a latency of the FBPU.

Abstract: Reuse of branch information queue entries for multiple instances of predicted control instructions in captured loops in a processor, and related methods and computer-readable media. The processor establishes and updates a branch entry in a branch information queue (BIQ) circuit with branch information in response to a speculative prediction made for a predicted control instruction. The branch information is used for making and tracking flow path predictions for predicted control instructions as well as verifying such predictions against its resolution for possible misprediction recovery. The processor is configured to reuse the same branch entry in the BIQ circuit for each instance of the predicted control instruction. This conserves space in the BIQ circuit, which allows for a smaller sized BIQ circuit to be used thus conserving area and power consumption. The branch information for each instance of a predicted control instruction within a loop remains consistent.

Abstract: A data processing apparatus provides predictions for hard to predict instructions. Prediction circuitry generates predictions relating to predictable instructions in a stream and stores, with respect to each of the predictable instructions, a reference to a set of monitored instructions in the stream to be used for generating predictions for the predictable instructions. Processing circuitry executes the predictable instructions in the stream using the predictions. A given correlation parameter is stored between a given predictable instruction in the stream and a subset of the set of monitored instructions of the given predictable instruction to assist in generating the predictions. If the given correlation parameter is currently stored, the prediction circuitry generates a given prediction relating to the given predictable instruction based on the subset of the set of monitored instructions.

Abstract: Selectively updating branch predictors for loops executed from loop buffers is disclosed herein. In some aspects, a branch predictor update circuit of a processor is configured to detect a loop comprising a plurality of loop instructions in an instruction stream, and to determine that the loop is stored within a loop buffer circuit of the processor. The branch predictor update circuit is further configured to determine a count of potential history register updates to the history register for the plurality of loop instructions, and to determine whether the count of potential history register updates exceeds a size of the history register. The branch predictor update circuit is also configured to, responsive to determining that the count of potential history register updates does not exceed the size of the history register, update a branch predictor of the branch predictor circuit based on the plurality of loop instructions.

Abstract: A data processing apparatus includes receive circuitry that receives an indication of a trigger block of instructions.

Abstract: Aspects of the present disclosure relate to an apparatus comprising prediction circuitry having a plurality of hierarchical prediction units to perform respective hierarchical predictions of instructions for execution, wherein predictions higher in the hierarchy have a higher expected accuracy than predictions lower in the hierarchy. Responsive to a given prediction higher in the hierarchy being different to a corresponding prediction lower in the hierarchy, the corresponding prediction lower in the hierarchy is corrected. A prediction correction metric determination unit determines a prediction correction metric indicative of an incidence of uncorrected predictions performed by the prediction circuitry. Fetch circuitry fetches instructions predicted by at least one of said plurality of hierarchical predictions, and delays said fetching based on the prediction correction metric indicating an incidence of uncorrected predictions below a threshold.

Abstract: A method, system, and computer program product for augmenting cache replacement operations are provided. The method identifies a set of cache lines within a first cache level of a multilevel cache. A first candidate cache line is identified based on a first replacement scheme of the first cache level. A second candidate cache line is identified based on the first replacement scheme of the first cache level. A replacement cache line is selected for replacement in the first cache level. The replacement cache line is selected from the first candidate cache line and the second candidate cache line and based on the first replacement scheme of the first cache level and a second replacement scheme of a second cache level. The method removes the replacement cache line from the first cache level.

Abstract: A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.

Abstract: A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.

Abstract: In some examples, a method includes determining, during a boot sequence of a controller, a hash value for data of a block of a flash storage device, the block including executable code, determining a bit pattern based on a randomly generated number, extracting a subset of data bits of the hash value according to the bit pattern to obtain a snippet, and storing the snippet to a secure storage device.

Abstract: Provided are an expression realization method and device for virtual character, and a storage medium, the method comprising: acquiring sequence frames of respective parts of a face of the virtual character, wherein the sequence frames of respective parts contain part sequences corresponding to respective expressions; acquiring a first part sequence corresponding to a first expression and a second part sequence corresponding to a second expression from the sequence frames of respective parts, wherein the first part sequence comprises a first transition part sequence, and the second part sequence comprises a second transition part sequence; and successively playing the first part sequence and the second part sequence according to a first preset instruction, wherein a playing of the first transition part sequence is located at a tail of the playing of the first part sequence, and a playing of the second transition part sequence is located at a head of the playing of the second part sequence.

Abstract: A predictor includes a memory having a plurality of entries. Each entry includes a prediction of a hash of a next fetch address produced by a fetch block J of a series of successive fetch blocks in program execution order and a branch direction produced by the fetch block J. An input selects an entry for provision on the output. The output is fed back to the input such that the output provides the prediction of the hash of the next fetch address and the branch direction produced by each fetch block over a series of successive clock cycles. The hash of the next fetch address is insufficient for use by an instruction fetch unit to fetch from an instruction cache a fetch block J+1, whereas the next fetch address itself is sufficient for use by the instruction fetch unit to fetch from the instruction cache the fetch block J+1.

Abstract: A microprocessor includes a prediction unit pipeline having a first stage that makes first predictions at a rate of one per clock cycle. Each first prediction comprises a hash of a fetch address of a current fetch block and branch history update information produced by a previous fetch block immediately preceding the current fetch block. Second one or more stages, following the first stage, with a latency of N (at least one) clock cycles, use the first predictions to make second predictions at a rate of one per clock cycle. Each second prediction includes a fetch address of a next fetch block immediately succeeding the current fetch block and branch history update information produced by the current fetch block. For each second prediction of the second predictions, logic uses the second prediction to check whether the first prediction made N?1 clock cycles earlier than the second prediction is a mis-prediction.

Abstract: Embodiments of apparatuses, methods, and systems for selective use of branch prediction hints are described. In an embodiment, an apparatus includes an instruction decoder and a branch predictor. The instruction decoder is to decode a branch instruction having a hint. The branch predictor is to provide a prediction and a hint-override indicator. The hint-override indicator is to indicate whether the prediction is based on stored information about the branch instruction. The prediction is to override the hint if the hint-override indicator indicates that the prediction is based on stored information about the branch instruction.

Abstract: A processor may include an instruction distribution circuit and a plurality of execution pipelines. The instruction distribution circuit may distribute a conditional instruction to a first execution pipeline for execution when the conditional instruction is associated with a prediction of a high confidence level, or to a second execution pipeline for execution when the conditional instruction is associated with a prediction of a low confidence level. The second execution pipeline, not the first execution pipeline, may directly instruct the processor to obtain an instruction from a target address for execution, when the conditional instruction is mispredicted. Thus, when the conditional instruction is distributed to the first execution pipeline for execution and determined to be mispredicted, the first execution pipeline may cause the conditional instruction to be re-executed in the second execution pipeline to cause the instruction from the correct target address to be obtained for execution.

Abstract: A branch prediction system includes a neuron cache and logic coupled to the neuron cache. The neuron cache includes one or more weights of a neural network model trained for one or more selected code sections, and the logic is to be used with the neuron cache to predict a target address for a branch instruction of the one or more selected code sections.

Abstract: Systems and methods include receiving a machine learning model that is configured to detect anomalies in network devices operating in a multi-layer network, wherein the machine learning model is trained via unsupervised learning that includes training the machine learning model with unlabeled data that describes an operational status of the network devices over time; receiving live data related to a current operational status of the network devices; analyzing the live data with the machine learning model; and detecting an anomaly related to any of the network device based on the analyzing.

Abstract: In one embodiment, a method implemented in a microprocessor, including receiving a fetched branch instruction; performing a privilege level test on a fetched branch instruction using a privilege level indicated by a first tag corresponding to a privilege level in a branch prediction table comprising plural entries, each of the plural entries comprising a tag corresponding to a privilege level; and providing a prediction branch miss for the fetched branch instruction based on a failure of the privilege level test.

Abstract: An apparatus comprises at least a first storage node of a plurality of storage nodes of a distributed storage system. The first storage node comprises a processor coupled to a memory. The first storage node is configured to receive from a host device a read operation directed to a particular portion of a logical address space of the storage system, where the logical address space is divided among the storage nodes. The first storage node is further configured to determine that the read operation is potentially part of a stream of multiple read operations directed to respective particular portions of the logical address space, and to send, to at least a second one of the storage nodes, an indication of the determination made by the first storage node. The stream of multiple read operations may comprise a sequential read stream directed to respective contiguous portions of the logical address space.

Abstract: An exception summary is provided for an invalid value detected during instruction execution. An indication that a value determined to be invalid was included in input data to a computation of one or more computations or in output data resulting from the one or more computations is obtained. The value is determined to be invalid due to one exception of a plurality of exceptions. Based on obtaining the indication that the value is determined to be invalid, a summary indicator is set. The summary indicator represents the plurality of exceptions collectively.

Abstract: An instruction processing apparatus is disclosed and includes: an instruction cache, which maps data blocks in a memory based on a multi-way set-associative structure and includes a plurality of cache lines; and an access control unit, coupled between an instruction fetch unit and the instruction cache, and adapted to read the plurality of cache lines respectively by using a plurality of data channels, and select a hit cache line from the plurality of cache lines by using a plurality of selection channels, to obtain an instruction, where the access control unit includes a path prediction unit, where the path prediction unit obtains, based on a type of the instruction, path prediction information corresponding to an instruction address, and enables at least one data channel and/or at least one selection channel based on the path prediction information.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. Upon a stream break instruction specifying one of the nested loops, the stream engine ends a current iteration of the loop. If the specified loop was not the outermost loop, the streaming engine begins an iteration of a next outer loop. If the specified loop was the outermost nested loop, the streaming engine ends the stream. The streaming engine places a vector of data elements in order in lanes within a stream head register. A stream break instruction is operable upon a vector break.

Abstract: A taint report represents a taint flow from a source value at a source program point to a sink value at a sink program point. Candidate watchpoints that correspond to taint-like values similar to the source value may be inferred from an execution trace. Different subsets of candidate watchpoints represent solutions to the problem of determining an optimal subset of watchpoints contributing to a taint flow. Using a hill-climbing heuristic, incremental improvements are efficiently applied to a solution until no more improvements are found. An objective function may determine whether one solution improves another solution. The objective function may be based on validity, understandability, and performance. Validity favors candidate watchpoints that reduce the edit distance between the source and sink values. Understandability favors candidate watchpoints included in a call chain from the source program point to the sink program point. Performance favors small subsets of candidate watchpoints.

Abstract: An instruction processing device and an instruction processing method are provided.

Abstract: Methods and parallel processing units for avoiding inter-pipeline data hazards identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. When a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted to indicate that the hazard related to the primary instruction has been resolved.

Abstract: A data processing apparatus and a method are disclosed.

Abstract: Instruction processing circuitry comprises fetch circuitry to fetch instructions for execution; instruction decoder circuitry to decode fetched instructions; execution circuitry to execute decoded instructions; and program flow prediction circuitry to predict a next instruction to be fetched; in which the instruction decoder circuitry is configured to decode a loop control instruction in respect of a given program loop and to derive information from the loop control instruction for use by the program flow prediction circuitry to predict program flow for one or more iterations of the given program loop.

Abstract: A processor including a processor pipeline having one or more execution units configured to execute branch instructions, a branch predictor coupled to the processor pipeline and configured to predict a branch instruction outcome, and a branch classification unit coupled to the processor pipeline and the branch prediction unit. The branch classification unit is configured to, in response to detecting a branch instruction, classify the branch instruction as at least one of the following: static taken branch, static not-taken branch, simple easy-to-predict branch, flip flop hard-to-predict (HTP) branch, dynamic HTP branch, biased positive HTP branch, biased negative HTP branch, and other HTP branch.

Abstract: A branch target buffer, BTB, is provided to store at least one BTB entry corresponding to a respective branch in a control flow in a sequence of machine-readable instructions of a computer program. The BTB has a tag field to compare with a program counter of a fetch address generator and at least one further field to store information characteristic of the branch instruction identified by the corresponding tag field and allowing a conditional branch to be distinguished from an unconditional branch instruction. The BTB has a predetermined storage capacity and is utilized such that unconditional branch instructions are preferentially allocated storage space in the BTB relative to conditional branch instructions.

Abstract: An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.

Abstract: Circuitry comprises prediction storage to store, for a given branch operation, a multi-bit data item and indicator data defining a subset of bits of the multi-bit data item, the subset being one of an ordered succession of different subsets of bits of the multi-bit data item; and prediction generator circuitry to generate a predicted branch outcome for the given branch operation in dependence upon the subset of bits defined by the indicator data and, in response to generation of the predicted branch outcome, to change the subset of bits defined by the indicator data to a next subset in the ordered succession of subsets.

Abstract: There is provided a blade replacing apparatus for replacing a cutting blade. The blade replacing apparatus includes a blade storage unit including a movable storage section configured to store the cutting blade, a transporting unit including a holding unit configured to hold the cutting blade and a moving mechanism configured to move the holding unit, a camera configured to photograph the holding unit, and a control unit including an operation control section configured to control operation of the blade storage unit and the transporting unit and a position registration section in which positions of the storage section and the holding unit. The storage section includes a first mark portion photographable by the camera, and the holding unit includes a second mark portion photographable by the camera.

Abstract: In an embodiment, an indirect branch predictor generates indirect branch predictions based on one or more register values. The register values may be the contents of registers on which the indirect branch instruction is directly or indirectly dependent for generating the branch target address, for example. In an embodiment, at least one of the registers may be a source for a load instruction, and the indirect branch may be dependent (directly or indirectly) on the target of the load. In an embodiment, the indirect branch predictor may be one of at least two indirect branch predictors in a processor. The other indirect branch predictor may be based on a fetch address, or PC, associated with the indirect branch instruction. The other indirect branch predictor may generate a first predicted target address, and the indirect branch predictor may generate a second predicted target address for the same indirect branch instruction.

Abstract: An apparatus has processing circuitry, and history storage circuitry to store local history records. Each local history record corresponds to a respective subset of instruction addresses and tracks a sequence of observed instruction behaviour observed for successive instances of instructions having addresses in that subset. Pointer storage circuitry to store a shared pointer shared between the local history records. The shared pointer indicates a common storage position reached in each local history record. Prediction circuitry determines predicted instruction behaviour for a given instruction address based on a selected portion of a selected local history record stored in the history storage circuitry. The prediction circuitry selects the selected local history record based on the given instruction address and selects the selected portion based on the shared pointer.

Abstract: Methods and apparatuses relating to instruction set architecture (ISA) based and automatic load tracking hardware for opportunistic re-steer of data-dependent flaky branches are described.

Abstract: Techniques are disclosed relating to protecting branch prediction information. In various embodiments, an integrated circuit includes branch prediction logic having a table that maintains a plurality of entries storing encrypted target address information for branch instructions. The branch prediction logic is configured to receive machine context information for a branch instruction having a target address being predicted by the branch prediction logic, the machine context information including a program counter associated with the branch instruction. The branch prediction logic is configured to use the machine context information to decrypt encrypted target address information stored in one of the plurality of entries identified based on the program counter.

Abstract: An integrated circuit comprising instruction processing circuitry for processing a plurality of program instructions and instruction prediction circuitry. The instruction prediction circuitry comprises circuitry for detecting successive occurrences of a same program loop sequence of program instructions. The instruction prediction circuitry also comprises circuitry for predicting a number of iterations of the same program loop sequence of program instructions, in response to detecting, by the circuitry for detecting, that a second occurrence of the same program loop sequence of program instructions comprises a same number of iterations as a first occurrence of the same program loop sequence of program instructions.

Abstract: An apparatus comprises data processing circuitry to perform data processing operations in response to a sequence of instructions, where the sequence of instructions comprises branch instructions. Trace generating circuitry generates a trace stream of trace items indicative of the data processing operations. The trace generating circuitry is responsive to one or more not-taken branch instructions followed by a taken branch instruction in the sequence of instructions to: include at least one not-taken trace item corresponding to the one or more not-taken branch instructions followed by a taken trace item in the trace stream when a current status condition of the apparatus is met, and to include a source address associated with the taken branch instruction in the trace stream when the current status condition of the apparatus is not met. A hybrid approach between tracing not-taken branch instructions and tracing a source address associated with the taken branch instruction is thus provided.

Abstract: In one embodiment, a microprocessor, comprising: prediction logic comprising a branch predictor comprising a group of multi-set associative tables, each of the tables corresponding to branch pattern histories of different lengths; and control logic configured to provide an adjustable write policy for the prediction logic.

Abstract: Dynamic hammock branch training for branch hammock detection in an instruction stream executing in a processor is disclosed. A branch hammock detection circuit is configured to dynamically detect branch hammocks in an instruction stream during run-time processing of the instruction stream. In response to an identified conditional branch instruction, the branch hammock detection circuit starts a training process for a potential branch hammock predicated by the conditional branch instruction. The branch hammock detection circuit is configured to determine if an identified in-training branch hammock is an actual branch hammock based on setting a potential convergence point as the target address for the conditional branch instruction based on whether the branch is taken or not taken. If an instruction is processed at the set convergence point, this means the set convergence point can be an actual convergence point and the in-training branch hammock can be detected as an actual branch hammock.

Abstract: A method at a computing device for identification of secure binary images, the method including: dissecting a binary image into routines and functions; disassembling byte code for the dissected routines and functions; retrieving local routine and function parameters; counting a number of conditional routines for each local routine and function parameter; and creating a confidence score for each dissected routine and function.

Abstract: An apparatus and method are provided for handling prediction information. The apparatus has processing circuitry for performing data processing operations in response to instructions, the processing circuitry comprising transactional memory support circuitry to support execution of a transaction comprising a sequence of instructions. Prediction circuitry is used to generate predictions in relation to instruction flow changing instructions, and prediction storage is provided to store a plurality of items of prediction information that are referenced by the prediction circuitry when generating the predictions. The items of prediction information maintained by the prediction storage change based on the instructions being executed by the processing circuitry. A recovery storage is activated by the transactional memory support circuitry at a transaction start point to store a restore pointer identifying a chosen location in the prediction storage.

Abstract: Circuitry comprises a prediction register storing a plurality of entries each having respective data values for association with one or more branch instructions; prediction circuitry to detect, using prediction data derived by a mapping function from the stored data values associated with a given branch instruction, whether or not a branch represented by the given branch instruction is predicted to be taken; update circuitry to modify the stored data values associated with the given branch instruction in dependence upon a resolution of whether the branch represented by the given branch instruction is taken or not; and control circuitry configured to selectively alter one or more of the data values other than data values associated with the given branch instruction.

Abstract: Provided is a method, computer program product, and system for performing data address prediction. The method comprises receiving a first instruction for execution by a processor. A load address predictor (LAP) accesses a LAP table entry for a section of an instruction cache. The section is associated with a plurality of instructions that includes the first instruction. The LAP predicts a set of data addresses that will be loaded using the LAP table entry. The method further comprises sending a recommendation to prefetch the set of data addresses to a load-store unit (LSU).