Particular Data Driven Memory Structure Patents (Class 712/27)
  • Patent number: 10447732
    Abstract: Techniques are provided for displaying a uniform resource locator (URL) to assist a user in determining whether a URL destination is what the user expects. A link is presented for selection to a user, and a URL corresponding to the link is accessed. A portion of the URL that corresponds to a hostname component of the URL may be identified, and the URL may be displayed. The hostname component of the URL is visually distinguished from other components of the URL. In addition to or as an alternative to displaying the URL and visually distinguishing the hostname component, a warning message relating to the hostname portion of the URL may be displayed. The techniques may be implemented as a software plug-in or in any type of software application that is capable of recognizing URLs.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: October 15, 2019
    Assignee: Facebook, Inc.
    Inventor: Conor P. Cahill
  • Patent number: 10250677
    Abstract: Systems and methods are provided for decentralized network address control, including a computer-implemented method for decentralized load balancing for a plurality of network resources. The method can include determining a load characteristic for the first network resource. The load characteristic can be determined by a first load balancing application associated with a first network resource. The method can further include sending a report to a network address resolution resource, based on the determined load characteristic. The network address resolution resource can be configured to also receive reports from other load balancing applications associated with other network resources based on determined load characteristics for the other network resources. Both the first network resource and the other network resources can be associated with a common network resource name.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: April 2, 2019
    Assignee: CyberArk Software Ltd.
    Inventor: Evgeni Aizikovich
  • Patent number: 10171299
    Abstract: A method for configuring a proxy server is disclosed. The method includes: establishing a first speed performance indicator and a second speed performance indicator, wherein the first speed performance indicator is configured for indicating a minimum threshold speed of the proxy server, and the second speed performance indicator is configured for determining whether the proxy server reaches a predefined standard speed; and selecting at least one proxy server from multiple candidate proxy servers according to the first speed performance indicator and/or the second speed performance indicator, and configuring the selected proxy server as a currently used proxy server. An apparatus for configuring a proxy server is also disclosed.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: January 1, 2019
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Mengqing Wu, Ning Zhang, Jinzhou Jiang, Liang Kang, Yuelong Teng, Yuguo Liu, Zhenxing Zhou
  • Patent number: 10162726
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium are disclosed. In one aspect, a method includes filtering a first plurality of requests based on one or more criteria to generate first filtered requests, the first plurality of requests being associated with a first query plan that is associated with a first instance, identifying a first application associated with at least a portion of the first filtered requests, and determining a quantity of cores used by the first application based at least in part on the portion of the first filtered requests associated with the first application.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: December 25, 2018
    Assignee: Accenture Global Services Limited
    Inventors: Scott A. Albrecht, Joshua Davidson
  • Patent number: 10146468
    Abstract: An addressless merge command includes an identifier of an item of data, and a reference value, but no address. A first part of the item is stored in a first place. A second part is stored in a second place. To move the first part so that the first and second parts are merged, the command is sent across a bus to a device. The device translates the identifier into a first address ADR1, and uses ADR1 to read the first part. Stored in or with the first part is a second address ADR2 indicating where the second part is stored. The device extracts ADR2, and uses ADR1 and ADR2 to issue bus commands. Each bus command causes a piece of the first part to be moved. When the entire first part has been moved, the device returns the reference value to indicate that the merge command has been completed.
    Type: Grant
    Filed: September 20, 2014
    Date of Patent: December 4, 2018
    Assignee: Netronome Systems, Inc.
    Inventors: Salma Mirza, Gavin J. Stark
  • Patent number: 9712611
    Abstract: The present disclosure presents systems and methods for obtaining metric information by a multi-core GSLB intermediary device and providing global server load balancing services using the obtained information. A first core of a multi-core GSLB appliance establishes a transport layer connection to a remote load balancer at a site of a plurality of sites. The first core transmits a message to each of the other cores of the multi-core GSLB appliance that the first core is a master core for receiving metric information from the load balancer. The first core receives metric information of the remote site from the load balancer. The first core propagates the metric information to each of the other cores of the GSLB appliance. A GSLB virtual server on a slave core receives a DNS request. The GSLB virtual server determines a DNS resolution for the DNS request based on the metric information.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: July 18, 2017
    Assignee: CITRIX SYSTEMS, INC.
    Inventors: Raghav Somanahalli Narayana, Murali Raja, Rishi Mutnuru, Ravi Kondamuru
  • Patent number: 9519488
    Abstract: An external intrinsic interface. A processor may include a core including a plurality of functional units, an intrinsic module located outside the core, and an interface module to perform relaying between the intrinsic module and a functional unit, among the plurality of functional units.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: December 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwon Taek Kwon, Seok Yoon Jung
  • Publication number: 20150006848
    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Glenn Hinton, Bret Toll, Ronak Singhal
  • Patent number: 8799706
    Abstract: A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: August 5, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: William F. Bruckert, David J. Garcia, Thomas A. Heynemann, James S. Klecka, Jeffrey A. Sprouse
  • Publication number: 20140195776
    Abstract: A method and device for memory access in processors is provided. A processor, comprising a plurality of computational units, is capable of executing a single instruction on multiple pieces of data simultaneously (SIMD). A read operation is initiated to load data from memory into the plurality of computational units (CUs) arranged into a plurality of CU groups. The memory is arranged into a plurality of memory macro-blocks each associated with a respective CU group of the plurality of CU groups. For each CU group a respective first memory address is determined and for each CU group, the data in the associated memory macro-block is accessed at the respective first memory address.
    Type: Application
    Filed: January 9, 2013
    Publication date: July 10, 2014
    Applicant: COGNIVUE CORPORATION
    Inventors: Malcolm STEWART, Ali Osman ORS, Daniel LAROCHE
  • Patent number: 8677078
    Abstract: A device for managing multiple instructions to access multiple wide registers may include logic to receive the multiple instructions to access one of the multiple wide registers, associate each received instruction with a corresponding one of multiple buffer memories, and allow simultaneous processing of the multiple instructions associated with each of the multiple buffer memories, where the multiple instructions are processed such that data is transferred between the multiple buffer memories and the multiple wide registers in one operation.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: March 18, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Karthikeyan Veerabadran, David J. Ofelt
  • Patent number: 8583896
    Abstract: Systems and methods for massively parallel processing on an accelerator that includes a plurality of processing cores. Each processing core includes multiple processing chains configured to perform parallel computations, each of which includes a plurality of interconnected processing elements. The cores further include multiple of smart memory blocks configured to store and process data, each memory block accepting the output of one of the plurality of processing chains. The cores communicate with at least one off-chip memory bank.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: November 12, 2013
    Assignee: NEC Laboratories America, Inc.
    Inventors: Srihari Cadambi, Abhinandan Majumdar, Michela Becchi, Srimat Chakradhar, Hans Peter Graf
  • Publication number: 20130232320
    Abstract: A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy.
    Type: Application
    Filed: March 1, 2012
    Publication date: September 5, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: JASON N. DALE, MILES R. DOOLEY, RICHARD J. EICKEMEYER, BRADLY G. FREY, YAOQING GAO, FRANCIS P. O'CONNELL, JEFFREY A. STUECHELI
  • Publication number: 20120185671
    Abstract: This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 19, 2012
    Applicant: Qualcomm Incorporated
    Inventors: Alexei V. Bourd, Andrew Gruber, Aleksandra L. Krstic, Robert J. Simpson, Colin Sharp, Chun Yu
  • Patent number: 8131935
    Abstract: A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Guy L. Guthrie, Robert A. Cargnoni, William J. Starke, Derek E. Williams
  • Patent number: 8095733
    Abstract: A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: January 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Guy L. Guthrie, Michael Siegel, William J. Starke, Derek E. Williams
  • Publication number: 20110119467
    Abstract: Systems and methods for massively parallel processing on an accelerator that includes a plurality of processing cores. Each processing core includes multiple processing chains configured to perform parallel computations, each of which includes a plurality of interconnected processing elements. The cores further include multiple of smart memory blocks configured to store and process data, each memory block accepting the output of one of the plurality of processing chains. The cores communicate with at least one off-chip memory bank.
    Type: Application
    Filed: July 26, 2010
    Publication date: May 19, 2011
    Applicant: NEC Laboratories America, Inc.
    Inventors: Srihari Cadambi, Abhinandan Majumdar, Michela Becchi, Srimat Chakradhar, Hans Peter Graf
  • Patent number: 7894791
    Abstract: The present invention discloses a multi-channel multi-media data processing method, comprising the steps of: providing a demodulator circuit and a multi-media processing circuit, the multi-media processing circuit including a DRAM; receiving multi-channel analog signals, and performing analog-to-digital conversion and demodulation on the signals by the demodulator circuit; storing the converted and demodulated multi-channel signals in the DRAM; and reading the signals of at least one channel from the DRAM.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: February 22, 2011
    Assignee: Alpha Imaging Technology Corporation
    Inventors: Chao-Chung Chang, Ming-Feng Yu, Ming-Jun Hsiao, Wei-Hao Yuan, Wei-Cheng Chang Chien
  • Patent number: 7870395
    Abstract: In an array of groups of cryptographic processors, the processors in each group operate together but are securely connected through an external shared memory. The processors in each group include cryptographic engines capable of operating in a pipelined fashion. Instructions in the form of request blocks are supplied to the array in a balanced fashion to assure that the processors are occupied processing instructions.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Dewkett, Camil Fayad, John K. Li, Siegfried K. H. Sutter, Phil C. Yeh
  • Patent number: 7707393
    Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: April 27, 2010
    Assignee: Broadcom Corporation
    Inventor: Sophie Wilson
  • Patent number: 7694151
    Abstract: An architecture, system and method for operating on encrypted and/or hidden information (e.g., code and/or data). The invention enables creators, owners and/or distributors of proprietary code to keep such code inaccessible to users and user-controlled software programs. A memory architecture includes first and second protected memory spaces, respectively storing operating system instructions and a decrypted version of the encrypted information. The first protected memory space may further store a table linking the locations of the encrypted and/or hidden, decrypted information with a decryption and/or authorization key. The system includes the memory architecture and a processor for executing instructions, and the method loads, stores and operates on the encrypted and/or hidden information according to the memory architecture functionality and/or constraints.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: April 6, 2010
    Inventors: Richard C. Johnson, Andrew Morgan, H. Peter Anvin, Linus Torvalds
  • Patent number: 7545896
    Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: June 9, 2009
    Assignee: STMicroelectronics Limited
    Inventor: Matthew Peter Hutson
  • Patent number: 7493469
    Abstract: From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the packet rates of the input arc and the output arc are lower than an upper-limit value of a pipeline transfer rate of a processor element. Based on the determination result, it is determined whether it is possible to execute the described flow graph program in the processor element. Performance evaluation of a program to be executed by a data driven processor based on an asynchronous pipeline transfer control can be carried out with ease and in a short time.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: February 17, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ricardo T. Shichiku, Shinichi Yoshida
  • Publication number: 20090031105
    Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
    Type: Application
    Filed: October 31, 2007
    Publication date: January 29, 2009
    Applicant: MicroUnity Systems Engineering, Inc.
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Patent number: 7480679
    Abstract: A clustered enterprise Java™ distributed processing system is provided. The distributed processing system includes a first and a second computer coupled to a communication medium. The first computer includes a Java™ virtual machine (JVM) and kernel software layer for transferring messages, including a remote Java™ virtual machine (RJVM). The second computer includes a JVM and a kernel software layer having a RJVM. Messages are passed from a RJVM to the JVM in one computer to the JVM and RJVM in the second computer. Messages may be forwarded through an intermediate server or rerouted after a network reconfiguration. Each computer includes a Smart stub having a replica handler, including a load balancing software component and a failover software component. Each computer includes a duplicated service naming tree for storing a pool of Smart stubs at a node. The computers may be programmed in a stateless, stateless factory, or a stateful programming model.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: January 20, 2009
    Assignee: BEA Systems, Inc.
    Inventors: Dean B. Jacobs, Eric M. Halpern
  • Patent number: 7467286
    Abstract: A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, James Coke, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar
  • Publication number: 20080301404
    Abstract: A method for controlling an electronic circuit including selecting at least one pre-stored generating rule from a plurality of pre-stored generating rules according to which a message which is to be transmitted to the electronic circuit for carrying out a controlling function to control the electronic circuit is to be generated, and generating the message according to the at least one selected generating rule.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 4, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: ANGEL JOERN, Christian Duerdodt
  • Patent number: 7315932
    Abstract: Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: January 1, 2008
    Inventor: William C. Moyer
  • Patent number: 7278013
    Abstract: Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: October 2, 2007
    Assignee: Intel Corporation
    Inventor: Lawrence A. Booth
  • Patent number: 7251721
    Abstract: For use in a wide-issue processor, a mechanism for, and method of, conditionally executing instructions and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a conditional execution block state machine that tags and generates link pointers for instructions located in a conditional execution block and (2) conditional link pointer registers, associated with stages in a pipeline of the processor, that contain and cause the link pointers to move therethrough as the instructions located in the conditional execution block move through the stages.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: July 31, 2007
    Assignee: VeriSilicon Holdings (Cayman Islands) Co. Ltd.
    Inventors: Hung T. Nguyen, Shannon A. Wichman
  • Patent number: 7216218
    Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: May 8, 2007
    Assignee: Broadcom Corporation
    Inventor: Sophie Wilson
  • Patent number: 7184003
    Abstract: A novel personal electronic device includes a first (embedded) and second (non-embedded) processors including associated operating systems and functions. In one aspect, the first processor performs relatively limited functions, while the second processor performs relatively broader functions under control of the first processor. Often the second processor requires more power than the first processor and is selectively operated by the first processor to minimize overall power consumption. Protocols for functions to be performed by the second processor may be provided directly to the second processor and processed by the second processor. In another aspect, a display controller is designed to interface with both processors. In another aspect, the operating systems work with one another. In another aspect, the first processor employs a thermal control program. Advantages of the invention include a broad array of functions performed by a relatively small personal electronics device.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: February 27, 2007
    Assignee: Dualcor Technologies, Inc.
    Inventors: Bryan T. Cupps, Timothy J. Glass
  • Patent number: 7130986
    Abstract: According to some embodiments, it is determined if a register is ready to exchange data with a processing element.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Kalpesh D. Mehta, Louis A. Lippincott, Eric F. Vannerson
  • Patent number: 7111119
    Abstract: The present invention makes it possible to transfer information between processors by a method that places little burden on the reception side processors. The information processing device is a device that processes information using a plurality of processors, comprising one or more first processors that have one or a plurality of local memories, and one or more second processors that write write information directly into the local memory that the target first processor has. The second processors store address maps in which local memory addresses for the first processors are recorded; these second processors acquire local memory addresses from these address maps, and write write information into the acquired local memory addresses.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: September 19, 2006
    Assignee: Hitachi, Ltd.
    Inventor: Nobuyuki Minowa
  • Patent number: 7065215
    Abstract: In a microprocessor, a program key for decrypting a program and a data key for encrypting/decrypting data processed by the program are handled as cryptographically inseparable pair inside the microprocessor, so that it becomes possible for the microprocessor to protect processes that actually execute the program, without an intervention of the operating system, and it becomes possible to conceal secret information of the program not only from the other user program but also from the operating system.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: June 20, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Shirakawa, Mikio Hashimoto, Keiichi Teramoto, Satoshi Ozaki, Kensaku Fujimoto
  • Patent number: 7032098
    Abstract: A data-driven type information processing apparatus includes at least a paired data generating unit, a memory control unit, and data memory. The memory control unit includes a pipeline register receiving a data packet output from the paired data generating unit, including a page address, a set value for setting an effective bit and data, and an address generating unit for generating an address for accessing the data memory by retrieving effective data from the data included in the data packet based on the set value and attaching the page address included in the data packet to the retrieved effective data.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: April 18, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Motoki Takase, Tsuyoshi Muramatsu
  • Patent number: 7028108
    Abstract: A data register which outputs an input data as is when the input data fulfills a set data width for outputting, and holds the input data until a bit width of the input data is equal to or more than the set data width, in response to a first enable signal. A first selector which selects an n-bit byte lane from a (2n?1)-bit byte lane of the data register in response to a first select signal, and a second selector which selects an n-bit byte lane out of a (2n?1)-bit byte lane and outputs a valid data in response to a second select signal. A data buffer which receives and stores the valid data in response to a second enable signals.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: April 11, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Hiratsuka, Mineo Fujii
  • Patent number: 7003648
    Abstract: A multi-threaded processor provides for efficient flow-control from a pool of un-executed stores in an instruction queue to a store queue. The processor also includes similar capabilities with respect to load instructions. The processor includes logic organized into a plurality of thread processing units (“TPUs”) and allocation logic that monitors each TPUs demand for entries in the store queue. Demand is determined by subtracting an adjustable threshold value from the most recently assigned store identifier value. If the difference between the most recently assigned instruction identifier for a TPU and the TPU's threshold is non-zero, then it is determined that the TPU has demand for at least one entry in the store queue. The allocation logic includes arbitration logic that determines which one of a plurality of TPUs with store queue demand should be allocated a free entry in the store queue.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: February 21, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: George Z. Chrysos, Chuan-Hua Chang, Joel S. Emer, John H. Mylius, Peter Soderquist
  • Patent number: 6986029
    Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: January 10, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Hiromichi Yamada, Dai Fujii, Yasuhiro Nakatsuka, Takashi Hotta, Kotaro Shimamura, Tatsuki Inuduka, Takanaga Yamazaki
  • Patent number: 6928457
    Abstract: A clustered enterprise Java™ distributed processing system is provided. The distributed processing system includes a first and a second computer coupled to a communication medium. The first computer includes a Java™ virtual machine (JVM) and kernel software layer for transferring messages, including a remote Java™ virtual machine (RJVM). The second computer includes a JVM and a kernel software layer having a RJVM. Messages are passed from a RJVM to the JVM in one computer to the JVM and RJVM in the second computer. Messages may be forwarded through an intermediate server or rerouted after a network reconfiguration. Each computer includes a Smart stub having a replica handler, including a load balancing software component and a failover software component. Each computer includes a duplicated service naming tree for storing a pool of Smart stubs at a node. The computers may be programmed in a stateless, stateless factory, or a stateful programming model.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: August 9, 2005
    Assignee: Bea Systems, Inc.
    Inventors: Dean B. Jacobs, Eric M. Halpern
  • Patent number: 6922737
    Abstract: A storage control device, connected to a host processing device through a full-duplex channel and for storing data received through the channel in a data storage means, comprises a plurality of channel processors for conducting a data-input-and-output process to the data storage means in correspondence with a command contained in data (a frame) sent from the host processing device through the channel, and a channel processor, among the plurality of channel processors, is assigned for executing the data-input-and-output process for the data (frame) according to a type of command contained in the data (frame). Thus, the storage control device of the present invention can use the full-duplex channel efficiently.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: July 26, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masami Maeda, Yoshihiro Asaka, Hidetoshi Sakaki, Masaru Tsukada
  • Patent number: 6862676
    Abstract: A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: March 1, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Micah C. Knapp, Poonacha P. Kongetira, Marc E. Lamere, Julie M. Staraitis
  • Patent number: 6775760
    Abstract: In an integrated circuit, an FPGA (2) has functions of a CPU core (5), and includes a user's circuit and so forth. This configuration allows the number of implemented components such as peripheral circuit chips to be decreased, and cost to be reduced. The integrated circuit is configured such that the CPU core (5), peripheral circuits thereof, and a system bus (8) are stored as logic data in a PROM (3), and the FPGA (2) performs functions as the CPU core (5), peripheral circuits (6) (7), and system bus (8) based on the logic data. Therefore, the CPU core (5), peripheral circuits (6) (7), and system bus (8) which have desired functions can be obtained according to contents of the logic data stored in the PROM (3). Further, a user can readily extend and change functions of the CPU core (5) by retrofitting a separate circuit to the system bus (8).
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: August 10, 2004
    Assignee: Roran Co.
    Inventor: Kenji Shigeki
  • Patent number: 6775687
    Abstract: A method, system, and computer program product for exchanging supplemental information fields between a client and server. This supplemental information can then be used by the server to complete a client's request for content stored at a particular location. For example, the supplemental information may be used to provide a customized response, or for access control to sensitive data. Preferably, the REDIRECT message of the Hypertext Transfer Protocol (HTTP) or the Wireless Session Protocol (WSP) is used to request the supplemental information, encoding a comma-separated list of attribute names in a request header for the desired supplemental information. This solution is designed to be backward-compatible.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: August 10, 2004
    Assignee: International Business Machines Corporation
    Inventors: Carl Binding, Stefan Georg Hild, Luke James O'Connor, Sandeep K. Singhal
  • Patent number: 6757817
    Abstract: Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: June 29, 2004
    Assignee: Intel Corporation
    Inventor: Lawrence A. Booth
  • Patent number: 6728862
    Abstract: An array of processor elements has multiple instruction streams and multiple data streams broadcast to all of the processor elements. The processor elements are each connected to multiple neighbouring processor elements within a cruciate neighbourhood. The architecture is suitable for use in fine-grained applications. The array may have a processor element for each pixel of an image. The array is preferably provided on a single integrated circuit having 10,000 or more processor elements.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: April 27, 2004
    Assignee: Gazelle Technology Corporation
    Inventor: Jeremy Craig Wilson
  • Patent number: 6711665
    Abstract: An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated with different CAM cell arrays at will, to support parallel execution of the same or different arithmetical operations on two or more CAM cell arrays, and to support pipelined arithmetical operations by having two CAM cell arrays share a tags register to transfer data from one CAM cell array to another using appropriate compare and write operations. All the CAM cell arrays share the same mask and pattern registers. Preferably, at least one tags register is located physically between two of the CAM cell arrays.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: March 23, 2004
    Assignee: Neomagic Israel Ltd.
    Inventors: Avidan Akerib, Josh Meir, Ronen Stilkol, Yaron Serfati
  • Patent number: 6654646
    Abstract: A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data. The boundary between the instruction range and the data range can be varied and placed under the control of the processor according to the needs of the particular application being processed. Some or all of the blocks of storage can access either the instruction bus or the data bus system, and the selection is made under the control of a control register within the processor. Advantageously, applications which require a larger amount of instruction storage, this can be provided; for applications which require a larger amount of data storage, that can be provided also; both are limited only by the total amount of storage available.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: November 25, 2003
    Assignee: Lucent Technologies Inc.
    Inventors: Thomas Earl Bowers, Robert Joseph Gamoke, Glen D. Rocque, Paul Ronald Wiley
  • Patent number: 6643763
    Abstract: Method, system and program storage device are provided for implementing a register pipe between processing engines of a multiprocessor computing system. A register pipe includes at least one first register of a first processing engine and at least one second register of a second processing engine. Data is transferred between the first processing engine and the second processing engine through the register pipe without passing through memory. In one embodiment, general purpose registers within the first processing engine and within the second processing engine are employed to implement the register pipe. A control mechanism is provided within each processing engine to dynamically enable or disable the register pipe coupling any two processing engines of the multiprocessor computer system. A technique for broadcasting to multiple register pipes and for implementing barrier synchronization using a register pipe addressed to a processing engine itself are also provided.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: November 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: William J. Starke, Joseph L. Temple, III
  • Patent number: 6629235
    Abstract: A condition code register architecture for supporting multiple execution units is disclosed. A master execution unit is coupled a master condition code register such that condition codes generated by the master execution unit are stored in the master condition code register. A non-master execution unit is coupled to a shadow condition code register such that condition codes generated by the non-master execution unit are stored in the shadow condition code register. A tag unit coupled to the master execution unit and the non-master execution unit such that an entry within the master condition code register can be read only when a corresponding entry within the tag unit is referenced to the master execution unit or the master condition code register.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: September 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: Brian King Flachs, Harm Peter Hofstee, Kevin John Nowka