Abstract: A configuration object is provided to configure a server. The configuration object has an associated type to which the configuration object applies and information about a plurality of file stores available to the server. A method for data access can include, receiving, by the server, a request to perform a first operation with respect to a content object associated with the associated type to which the configuration object applies, using the configuration object to determine, from the plurality of file stores available to the server, a set of candidate file stores to service the request, and selecting a target file store from the set of candidate file stores and servicing the request using the target file store. Selecting the target file store includes mapping the object identifier to the target file store.

Abstract: Systems and associated methods for constructing neural networks (NN) without the benefit of predefined output spike times or predefined network architecture. Functions are constructed from other functions determined from an input construction training set of output variable type. Method aspects of the neural network modeler may comprise partitioning the construction training set, representing the partitions, restricting the representations, constructing subfunctions from the restrictions, and combining the subfunctions to model the target function. Specifically, subfunctions represented from partition-specific neural networks of output value type are created using two fundamental composition operations: same-constant composition and different-constants composition. Different choices of weights and delays lead to different NNs with different output spikes that implement the same function.

Abstract: A DNS service routes network traffic based on a routing policy. A DNS routing policy generation system receives latency data corresponding to a plurality of different users, and a learning system learns the routing policy based on the latency data. In learning the routing policy, the learning system waits latency samples so that more recent latency samples are weighted more heavily than less recent latency samples.

Abstract: Described herein are systems, methods, and software to enhance network traffic management. In one implementation, a method of operating a network interface system on a host computing system includes receiving a plurality of network packets and, for each packet in the plurality of network packets, identifying whether the packet comprises a control packet for fault detection in a software defined network (SDN). The method further includes prioritizing, for processing by a main processing system of the computing system, each packet in the plurality of network packets based on whether the packet comprises a control packet for fault detection in a SDN.

Abstract: Apparatuses and methods related to generating memory characteristic based access commands generating the access commands can include providing a first access command to a memory system of a plurality of memory systems, receiving, at a host coupled to the memory system, data corresponding to characteristics of a memory device of the memory system from a controller of the memory system, where the characteristics are based at least in part on processing of the first access command. Generating access commands can also include generating, at the host, a second access command based on the data and transmitting the second access command to at least the memory system.

Abstract: A system to support data gathering for a machine learning (ML) operation comprises a memory unit configured to maintain data for the ML operation in a plurality of memory blocks each accessible via a memory address. The system further comprises an inference engine comprising a plurality of processing tiles each comprising one or more of an on-chip memory (OCM) configured to load and maintain data for local access by components in the processing tile. The system also comprises a core configured to program components of the processing tiles of the inference engine according to an instruction set architecture (ISA) and a data streaming engine configured to stream data between the memory unit and the OCMs of the processing tiles of the inference engine wherein data streaming engine is configured to perform a data gathering operation via a single data gathering instruction of the ISA at the same time.

Abstract: A system and method of accelerating execution of a NN model, by at least one processor may include: receiving a first matrix A, representing elements of a kernel K of the NN model and a second matrix B, representing elements of an input I to kernel K; producing from matrix A, a group-sparse matrix A?, comprising G tensors of elements. The number of elements in each tensor is defined by, or equal to a number of entries in each index of an input tensor register used for a specific Single Instruction Multiple Data (SIMD) tensor operation, and all elements of A? outside said G tensors are null. The system and method may further include executing kernel K on input I, by performing at least one computation of the SIMD tensor operation, having as operands elements of a tensor of the G tensors and corresponding elements of the B matrix.

Abstract: The present application is directed towards systems and methods for application specific load-balancing for web servers. A device intermediary to a plurality of clients and a plurality of services executing on a plurality of servers, may receive a request from a client for an application. The device may identify an identifier for the application from a table comprising a list of applications and a corresponding identifier assigned to each application. In an embodiment, the device may establish one or more monitors to monitor each service to determine applications available on each service. In an embodiment, the device may determine that one or more services of the plurality of services provides the application and select a service from the one or more services to forward the request. The device may forward the request to the selected service.

Abstract: A circuit that includes a plurality of array cores, each array core of the plurality of array cores comprising: a plurality of distinct data processing circuits; and a data queue register file; a plurality of border cores, each border core of the plurality of border cores comprising: at least a register file, wherein: [i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and [ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.

Abstract: Techniques are provided for displaying a uniform resource locator (URL) to assist a user in determining whether a URL destination is what the user expects. A link is presented for selection to a user, and a URL corresponding to the link is accessed. A portion of the URL that corresponds to a hostname component of the URL may be identified, and the URL may be displayed. The hostname component of the URL is visually distinguished from other components of the URL. In addition to or as an alternative to displaying the URL and visually distinguishing the hostname component, a warning message relating to the hostname portion of the URL may be displayed. The techniques may be implemented as a software plug-in or in any type of software application that is capable of recognizing URLs.

Abstract: Systems and methods are provided for decentralized network address control, including a computer-implemented method for decentralized load balancing for a plurality of network resources. The method can include determining a load characteristic for the first network resource. The load characteristic can be determined by a first load balancing application associated with a first network resource. The method can further include sending a report to a network address resolution resource, based on the determined load characteristic. The network address resolution resource can be configured to also receive reports from other load balancing applications associated with other network resources based on determined load characteristics for the other network resources. Both the first network resource and the other network resources can be associated with a common network resource name.

Abstract: A method for configuring a proxy server is disclosed. The method includes: establishing a first speed performance indicator and a second speed performance indicator, wherein the first speed performance indicator is configured for indicating a minimum threshold speed of the proxy server, and the second speed performance indicator is configured for determining whether the proxy server reaches a predefined standard speed; and selecting at least one proxy server from multiple candidate proxy servers according to the first speed performance indicator and/or the second speed performance indicator, and configuring the selected proxy server as a currently used proxy server. An apparatus for configuring a proxy server is also disclosed.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium are disclosed. In one aspect, a method includes filtering a first plurality of requests based on one or more criteria to generate first filtered requests, the first plurality of requests being associated with a first query plan that is associated with a first instance, identifying a first application associated with at least a portion of the first filtered requests, and determining a quantity of cores used by the first application based at least in part on the portion of the first filtered requests associated with the first application.

Abstract: An addressless merge command includes an identifier of an item of data, and a reference value, but no address. A first part of the item is stored in a first place. A second part is stored in a second place. To move the first part so that the first and second parts are merged, the command is sent across a bus to a device. The device translates the identifier into a first address ADR1, and uses ADR1 to read the first part. Stored in or with the first part is a second address ADR2 indicating where the second part is stored. The device extracts ADR2, and uses ADR1 and ADR2 to issue bus commands. Each bus command causes a piece of the first part to be moved. When the entire first part has been moved, the device returns the reference value to indicate that the merge command has been completed.

Abstract: The present disclosure presents systems and methods for obtaining metric information by a multi-core GSLB intermediary device and providing global server load balancing services using the obtained information. A first core of a multi-core GSLB appliance establishes a transport layer connection to a remote load balancer at a site of a plurality of sites. The first core transmits a message to each of the other cores of the multi-core GSLB appliance that the first core is a master core for receiving metric information from the load balancer. The first core receives metric information of the remote site from the load balancer. The first core propagates the metric information to each of the other cores of the GSLB appliance. A GSLB virtual server on a slave core receives a DNS request. The GSLB virtual server determines a DNS resolution for the DNS request based on the metric information.

Abstract: An external intrinsic interface. A processor may include a core including a plurality of functional units, an intrinsic module located outside the core, and an interface module to perform relaying between the intrinsic module and a functional unit, among the plurality of functional units.

Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.

Abstract: A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.

Abstract: A method and device for memory access in processors is provided. A processor, comprising a plurality of computational units, is capable of executing a single instruction on multiple pieces of data simultaneously (SIMD). A read operation is initiated to load data from memory into the plurality of computational units (CUs) arranged into a plurality of CU groups. The memory is arranged into a plurality of memory macro-blocks each associated with a respective CU group of the plurality of CU groups. For each CU group a respective first memory address is determined and for each CU group, the data in the associated memory macro-block is accessed at the respective first memory address.

Abstract: A device for managing multiple instructions to access multiple wide registers may include logic to receive the multiple instructions to access one of the multiple wide registers, associate each received instruction with a corresponding one of multiple buffer memories, and allow simultaneous processing of the multiple instructions associated with each of the multiple buffer memories, where the multiple instructions are processed such that data is transferred between the multiple buffer memories and the multiple wide registers in one operation.

Abstract: Systems and methods for massively parallel processing on an accelerator that includes a plurality of processing cores. Each processing core includes multiple processing chains configured to perform parallel computations, each of which includes a plurality of interconnected processing elements. The cores further include multiple of smart memory blocks configured to store and process data, each memory block accepting the output of one of the plurality of processing chains. The cores communicate with at least one off-chip memory bank.

Abstract: A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy.

Abstract: This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.

Abstract: A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.

Abstract: A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units.

Abstract: Systems and methods for massively parallel processing on an accelerator that includes a plurality of processing cores. Each processing core includes multiple processing chains configured to perform parallel computations, each of which includes a plurality of interconnected processing elements. The cores further include multiple of smart memory blocks configured to store and process data, each memory block accepting the output of one of the plurality of processing chains. The cores communicate with at least one off-chip memory bank.

Abstract: The present invention discloses a multi-channel multi-media data processing method, comprising the steps of: providing a demodulator circuit and a multi-media processing circuit, the multi-media processing circuit including a DRAM; receiving multi-channel analog signals, and performing analog-to-digital conversion and demodulation on the signals by the demodulator circuit; storing the converted and demodulated multi-channel signals in the DRAM; and reading the signals of at least one channel from the DRAM.

Abstract: In an array of groups of cryptographic processors, the processors in each group operate together but are securely connected through an external shared memory. The processors in each group include cryptographic engines capable of operating in a pipelined fashion. Instructions in the form of request blocks are supplied to the array in a balanced fashion to assure that the processors are occupied processing instructions.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: An architecture, system and method for operating on encrypted and/or hidden information (e.g., code and/or data). The invention enables creators, owners and/or distributors of proprietary code to keep such code inaccessible to users and user-controlled software programs. A memory architecture includes first and second protected memory spaces, respectively storing operating system instructions and a decrypted version of the encrypted information. The first protected memory space may further store a table linking the locations of the encrypted and/or hidden, decrypted information with a decryption and/or authorization key. The system includes the memory architecture and a processor for executing instructions, and the method loads, stores and operates on the encrypted and/or hidden information according to the memory architecture functionality and/or constraints.

Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.

Abstract: From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the packet rates of the input arc and the output arc are lower than an upper-limit value of a pipeline transfer rate of a processor element. Based on the determination result, it is determined whether it is possible to execute the described flow graph program in the processor element. Performance evaluation of a program to be executed by a data driven processor based on an asynchronous pipeline transfer control can be carried out with ease and in a short time.

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Abstract: A clustered enterprise Java™ distributed processing system is provided. The distributed processing system includes a first and a second computer coupled to a communication medium. The first computer includes a Java™ virtual machine (JVM) and kernel software layer for transferring messages, including a remote Java™ virtual machine (RJVM). The second computer includes a JVM and a kernel software layer having a RJVM. Messages are passed from a RJVM to the JVM in one computer to the JVM and RJVM in the second computer. Messages may be forwarded through an intermediate server or rerouted after a network reconfiguration. Each computer includes a Smart stub having a replica handler, including a load balancing software component and a failover software component. Each computer includes a duplicated service naming tree for storing a pool of Smart stubs at a node. The computers may be programmed in a stateless, stateless factory, or a stateful programming model.

Abstract: A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.

Abstract: A method for controlling an electronic circuit including selecting at least one pre-stored generating rule from a plurality of pre-stored generating rules according to which a message which is to be transmitted to the electronic circuit for carrying out a controlling function to control the electronic circuit is to be generated, and generating the message according to the at least one selected generating rule.

Abstract: Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.

Abstract: Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core.

Abstract: For use in a wide-issue processor, a mechanism for, and method of, conditionally executing instructions and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a conditional execution block state machine that tags and generates link pointers for instructions located in a conditional execution block and (2) conditional link pointer registers, associated with stages in a pipeline of the processor, that contain and cause the link pointers to move therethrough as the instructions located in the conditional execution block move through the stages.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: A novel personal electronic device includes a first (embedded) and second (non-embedded) processors including associated operating systems and functions. In one aspect, the first processor performs relatively limited functions, while the second processor performs relatively broader functions under control of the first processor. Often the second processor requires more power than the first processor and is selectively operated by the first processor to minimize overall power consumption. Protocols for functions to be performed by the second processor may be provided directly to the second processor and processed by the second processor. In another aspect, a display controller is designed to interface with both processors. In another aspect, the operating systems work with one another. In another aspect, the first processor employs a thermal control program. Advantages of the invention include a broad array of functions performed by a relatively small personal electronics device.

Abstract: According to some embodiments, it is determined if a register is ready to exchange data with a processing element.

Abstract: The present invention makes it possible to transfer information between processors by a method that places little burden on the reception side processors. The information processing device is a device that processes information using a plurality of processors, comprising one or more first processors that have one or a plurality of local memories, and one or more second processors that write write information directly into the local memory that the target first processor has. The second processors store address maps in which local memory addresses for the first processors are recorded; these second processors acquire local memory addresses from these address maps, and write write information into the acquired local memory addresses.

Abstract: In a microprocessor, a program key for decrypting a program and a data key for encrypting/decrypting data processed by the program are handled as cryptographically inseparable pair inside the microprocessor, so that it becomes possible for the microprocessor to protect processes that actually execute the program, without an intervention of the operating system, and it becomes possible to conceal secret information of the program not only from the other user program but also from the operating system.

Abstract: A data-driven type information processing apparatus includes at least a paired data generating unit, a memory control unit, and data memory. The memory control unit includes a pipeline register receiving a data packet output from the paired data generating unit, including a page address, a set value for setting an effective bit and data, and an address generating unit for generating an address for accessing the data memory by retrieving effective data from the data included in the data packet based on the set value and attaching the page address included in the data packet to the retrieved effective data.

Abstract: A data register which outputs an input data as is when the input data fulfills a set data width for outputting, and holds the input data until a bit width of the input data is equal to or more than the set data width, in response to a first enable signal. A first selector which selects an n-bit byte lane from a (2n?1)-bit byte lane of the data register in response to a first select signal, and a second selector which selects an n-bit byte lane out of a (2n?1)-bit byte lane and outputs a valid data in response to a second select signal. A data buffer which receives and stores the valid data in response to a second enable signals.

Abstract: A multi-threaded processor provides for efficient flow-control from a pool of un-executed stores in an instruction queue to a store queue. The processor also includes similar capabilities with respect to load instructions. The processor includes logic organized into a plurality of thread processing units (“TPUs”) and allocation logic that monitors each TPUs demand for entries in the store queue. Demand is determined by subtracting an adjustable threshold value from the most recently assigned store identifier value. If the difference between the most recently assigned instruction identifier for a TPU and the TPU's threshold is non-zero, then it is determined that the TPU has demand for at least one entry in the store queue. The allocation logic includes arbitration logic that determines which one of a plurality of TPUs with store queue demand should be allocated a free entry in the store queue.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: A clustered enterprise Java™ distributed processing system is provided. The distributed processing system includes a first and a second computer coupled to a communication medium. The first computer includes a Java™ virtual machine (JVM) and kernel software layer for transferring messages, including a remote Java™ virtual machine (RJVM). The second computer includes a JVM and a kernel software layer having a RJVM. Messages are passed from a RJVM to the JVM in one computer to the JVM and RJVM in the second computer. Messages may be forwarded through an intermediate server or rerouted after a network reconfiguration. Each computer includes a Smart stub having a replica handler, including a load balancing software component and a failover software component. Each computer includes a duplicated service naming tree for storing a pool of Smart stubs at a node. The computers may be programmed in a stateless, stateless factory, or a stateful programming model.

Abstract: A storage control device, connected to a host processing device through a full-duplex channel and for storing data received through the channel in a data storage means, comprises a plurality of channel processors for conducting a data-input-and-output process to the data storage means in correspondence with a command contained in data (a frame) sent from the host processing device through the channel, and a channel processor, among the plurality of channel processors, is assigned for executing the data-input-and-output process for the data (frame) according to a type of command contained in the data (frame). Thus, the storage control device of the present invention can use the full-duplex channel efficiently.