Abstract: A method, system, and computer program product for exchanging supplemental information fields between a client and server. This supplemental information can then be used by the server to complete a client's request for content stored at a particular location. For example, the supplemental information may be used to provide a customized response, or for access control to sensitive data. Preferably, the REDIRECT message of the Hypertext Transfer Protocol (HTTP) or the Wireless Session Protocol (WSP) is used to request the supplemental information, encoding a comma-separated list of attribute names in a request header for the desired supplemental information. This solution is designed to be backward-compatible.

Abstract: In an integrated circuit, an FPGA (2) has functions of a CPU core (5), and includes a user's circuit and so forth. This configuration allows the number of implemented components such as peripheral circuit chips to be decreased, and cost to be reduced. The integrated circuit is configured such that the CPU core (5), peripheral circuits thereof, and a system bus (8) are stored as logic data in a PROM (3), and the FPGA (2) performs functions as the CPU core (5), peripheral circuits (6) (7), and system bus (8) based on the logic data. Therefore, the CPU core (5), peripheral circuits (6) (7), and system bus (8) which have desired functions can be obtained according to contents of the logic data stored in the PROM (3). Further, a user can readily extend and change functions of the CPU core (5) by retrofitting a separate circuit to the system bus (8).

Abstract: Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core.

Abstract: An array of processor elements has multiple instruction streams and multiple data streams broadcast to all of the processor elements. The processor elements are each connected to multiple neighbouring processor elements within a cruciate neighbourhood. The architecture is suitable for use in fine-grained applications. The array may have a processor element for each pixel of an image. The array is preferably provided on a single integrated circuit having 10,000 or more processor elements.

Abstract: An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated with different CAM cell arrays at will, to support parallel execution of the same or different arithmetical operations on two or more CAM cell arrays, and to support pipelined arithmetical operations by having two CAM cell arrays share a tags register to transfer data from one CAM cell array to another using appropriate compare and write operations. All the CAM cell arrays share the same mask and pattern registers. Preferably, at least one tags register is located physically between two of the CAM cell arrays.

Abstract: A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data. The boundary between the instruction range and the data range can be varied and placed under the control of the processor according to the needs of the particular application being processed. Some or all of the blocks of storage can access either the instruction bus or the data bus system, and the selection is made under the control of a control register within the processor. Advantageously, applications which require a larger amount of instruction storage, this can be provided; for applications which require a larger amount of data storage, that can be provided also; both are limited only by the total amount of storage available.

Abstract: Method, system and program storage device are provided for implementing a register pipe between processing engines of a multiprocessor computing system. A register pipe includes at least one first register of a first processing engine and at least one second register of a second processing engine. Data is transferred between the first processing engine and the second processing engine through the register pipe without passing through memory. In one embodiment, general purpose registers within the first processing engine and within the second processing engine are employed to implement the register pipe. A control mechanism is provided within each processing engine to dynamically enable or disable the register pipe coupling any two processing engines of the multiprocessor computer system. A technique for broadcasting to multiple register pipes and for implementing barrier synchronization using a register pipe addressed to a processing engine itself are also provided.

Abstract: A condition code register architecture for supporting multiple execution units is disclosed. A master execution unit is coupled a master condition code register such that condition codes generated by the master execution unit are stored in the master condition code register. A non-master execution unit is coupled to a shadow condition code register such that condition codes generated by the non-master execution unit are stored in the shadow condition code register. A tag unit coupled to the master execution unit and the non-master execution unit such that an entry within the master condition code register can be read only when a corresponding entry within the tag unit is referenced to the master execution unit or the master condition code register.

Abstract: A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.

Abstract: A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of the operation. The status of the condition setting indicator determines whether or not multibit condition codes are set. When they are to be set, they are set depending on the results of carrying out the operation for each lane.

Abstract: The data driven type information processing system has a branch unit and a junction unit in the input and output stages thereof, and includes a plurality of data driven type processors between the branch unit and the junction unit. The branch unit, the junction unit and the plurality of data driven type processors are coupled to one another via transmission paths. Each of the data driven type processors can process a unique instruction system. The junction unit collects data packets provided via the transmission paths and outputs the collected data packets to the outside of the system. In operation, when a data packet is provided to the system, the branch unit receives the data packet provided thereto and, according to an instruction code within the received data packet, selects a transmission path connected to a data driven type processor that can process an instruction system corresponding to the instruction code, and sends out the received data packet to the selected transmission path.

Abstract: Disclosed are a data storage library and library computer processor implemented methods for expiring logical volumes in response to expiration selection from a host. A library server maintains a mapping database which identifies each logical volume and maps the logical volumes to data storage media. A library manager classifies the host selected expired logical volume in a category of logical volumes having a “SCRATCH” attribute, which may have an expiration delay, and identifies the selected logical volume in a searchable database as comprising the category having the “SCRATCH” attribute, and may calculate an expiration time for the selected logical volume from the delay. The library manager subsequently searches the searchable database for logical volumes identified as comprising a category having the “SCRATCH” attribute, and whose expiration time has passed, providing an indication to the library server that the searched identified logical volumes are expired.

Abstract: A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

Abstract: This invention is a data synchronous apparatus for synchronization between a first clock domain to a second clock domain asynchronous with the first clock domain. This invention provides for pipelining of data between the two clock domains. Plural synchronizer stages each include a data register (601, 602, 603, 604, 605) and a synchronizer circuit (611, 612, 613, 614, 615). The synchronizer circuit synchronizes a first domain write request signal to the second clock signal. A write pointer (625) enables one synchronizer stage to write first domain data upon receipt of said first domain write request signal (321). The write pointer thereafter increments to indicate a next synchronizer stage in a circular sequence. A read pointer (635) enables an indicated read stage to recall data from the corresponding data register upon output synchronization with the second clock signal. The read pointer thereafter increments to indicate the next synchronizer stage in the circular sequence.

Abstract: A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.

Abstract: A data register which outputs an input data as is when the input data fulfills a set data width for outputting, and holds the input data until a bit width of the input data is equal to or more than the set data width, in response to a first enable signal. A first selector which selects an n-bit byte lane from a (2n-1)-bit byte lane of the data register in response to a first select signal, and a second selector which selects an n-bit byte lane out of a (2n-1)-bit byte lane and outputs a valid data in response to a second select signal. A data buffer which receives and stores the valid data in response to a second enable signals.

Abstract: In accordance with the present invention, an FPGA input/output buffer including a tristate enable register is provided. A bus line provides the FPGA output through a tristate buffer to the pad or pin. A register controls the state of the tristate buffer. A register for providing an input signal from the pad or pin may also be provided. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the output control register and for loading data into the input register.

Abstract: One embodiment of the present invention provides a system that supports space and time dimensional program execution by facilitating accesses to different versions of a memory element. The system supports a head thread that executes program instructions and a speculative thread that executes program instructions in advance of the head thread. The head thread accesses a primary version of the memory element, and the speculative thread accesses a space-time dimensioned version of the memory element. During a reference to the memory element by the head thread, the system accesses the primary version of the memory element. During a reference to the memory element by the speculative thread, the speculative thread accesses a pointer associated with the primary version of the memory element, and accesses a version of the memory element through the pointer. Note that the pointer points to the space-time dimensioned version of the memory element if the space-time dimensioned version of the memory element exists.

Abstract: A system is provided that facilitates space and time dimensional execution of computer programs through selective versioning of memory elements located in a system heap. The system includes a head thread that executes program instructions and a speculative thread that simultaneously executes program instructions in advance of the head thread with respect to the time dimension of sequential execution of the program. The collapsing of the time dimensions is facilitated by expanding the heap into two space-time dimensions, a primary dimension (dimension zero), in which the head thread operates, and a space-time dimension (dimension one), in which the speculative thread operates. In general, each dimension contains its own version of an object and objects created by the thread operating in the dimension. The head thread generally accesses a primary version of a memory element and the speculative thread generally accesses a corresponding space-time dimensioned version of the memory element.

Abstract: A method is provided for load balancing requests for an application among a plurality of instances of the application operating on a plurality of servers. A policy is selected for choosing a preferred server from the plurality of servers according to a specified status or operational characteristic of the application instances, such as the least-loaded instance or the instance with the fastest response time. The policy is encapsulated within multiple levels of objects or modules that are distributed among the servers offering the application and a central server that receives requests for the application. A first type of object, a status object, gathers or retrieves application-specific information concerning the specified status or operational characteristic of an instance of the application. Status objects interact with instances of the load-balanced application and are configured to store their collected information for retrieval by individual server monitor objects.

Abstract: Dynamically typed registers in a processor are provided by associating a type specifier with a register specifier for each register in the processor, storing the register specifiers and associated type specifiers in a register type table. The type specifier associated with an operand register of an instruction is employed to dispatch the instruction to an appropriate execution unit within the processor. The results of the instruction are stored in a register having an associated type specifier matching the execution unit type. Register specifiers are dynamically allocated to particular execution units within the processor by altering the type specifier associated with the register specifiers. Register values may be either discarded or converted when the register specifier type is altered. A general instruction allows conversion of the value from one type to another without storing the converted value in memory.

Abstract: A method of debugging and a method of monitoring an analysis instrument are provided. A microcomputer of the analysis instrument is provided with a debugging personal computer connected thereto via remote communication means. The analysis instrument has detecting means for checking operation status installed therein. An operator debugs contents stored in the analysis instrument via the communication means after checking as to whether trouble exists in each device according to testing information provided by the detecting means.

Abstract: In the CIS installation area of a PC card, the A region contains the basic attribute information of the card, the B region contains data of CIS1 for a modem, and the C region contains CIS2 for an ATA memory. The PC card is provided with a selection signal input means which selectively designates the CIS. A selection signal discriminator receives a signal from the selection signal input means and determines the selective designation of the CIS. When CIS1 and CIS2 are selectively designated together, a CIS switch setting element sets the start of the CIS read-in by a personal computer to the leading address of CIS1, and when CIS2 only is selectively designated, it switchably sets the start of the CIS read-in by the personal computer to the leading address of CIS2.

Abstract: Cache layout is simplified by swizzling the bits of instruction words. Then the words are read out of cache by using a shuffled bit stream which simplifies cache layout. The object is further met using a cache structure which includes a device for storing a shuffled instruction stream; and a device for multiplexing bits from the storage means onto the bus so that the bits are deshuffled. The multiplexing means includes a multiplicity of lines leading from the storage device to the bus. The read lines do not cross each other.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: A trigger is provided in association with a network naming service, such as DNS (Domain Name Service), that handles client requests for an application. The trigger comprises a set of executable instructions referenced by a resource record associated with an identifier of the application. In response to a client request concerning the application, the resource record is retrieved and the instructions are executed. In one implementation of a trigger, a DNS server provides load balancing among a plurality of servers within a network name space (e.g., domain or sub-domain) offering an application program (or replicated service) that is known by a virtual server name. A policy is selected for choosing a preferred server from the plurality of servers according to a specified status or operational characteristic of the application instances, such as the least-loaded instance of the application or the instance with the fastest response time.

Abstract: A communications system utilizes an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

Abstract: A program driver means is disclosed that allows for the exchange of inforion between a NTDS device and a device having a bus topology, especially a VMEbus. The program driver utilizes chain commands which are fully programmable at the user level. The processor itself is programmed at the register level to assure the fastest data rate possible (32 bit access) across the VMEbus. The processor driver is invisible to the user.