Abstract: A Wings array system for communicating between nodes using store and load instructions is described. Couplings between nodes are made according to a 1 to N adjacency of connections in each dimension of a G×H matrix of nodes, where G?N and H?N and N is a positive odd integer. Also, a 3D Wings neural network processor is described as a 3D G×H×K network of neurons, each neuron with an N×N×N array of synaptic weight values stored in coupled memory nodes, where G?N, H?N, K?N, and N is determined from a 1 to N adjacency of connections used in the G×H×K network. Further, a hexagonal processor array is organized according to an INFORM coordinate system having axes at 60 degree spacing. Nodes communicate on row paths parallel to an FM dimension of communication, column paths parallel to an IO dimension of communication, and diagonal paths parallel to an NR dimension of communication.

Abstract: A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

Abstract: Techniques are provided for dynamically re-ordering operation requests that have previously been submitted to a queue management unit. After the queue management unit has placed multiple requests in a queue to be executed in an order that is based on priorities that were assigned to the operations, the entity that requested the operations (the “requester”) sends one or more priority-change messages. The one or more priority-change messages include requests to perform operations that have already been queued. For at least one of the operations, the priority assigned to the operation in the subsequent request is different from the priority that was assigned to the same operation when that operation was initially queued for execution. Based on the change in priority, the operation whose priority has change is placed at a different location in the queue, relative to the other operations in the queue that were requested by the same requester.

Abstract: Node Interconnect architectures to implement a high performance supercomputer are provided. For example, a node interconnect architecture for connecting a multitude of nodes (or processors) of a supercomputer is implemented using an all-to-all electrical and optical connection network which provides two independent communication paths between any two processors of the supercomputer, wherein a communication path includes at most two electrical links and one optical link.

Abstract: An exemplary switch system includes a first central processing unit (CPU), a second CPU, a first switch unit, a second switch unit, and a microcontroller. The first CPU provides an identification signal to the first switch unit and the second switch unit when the first CPU is associated with a motherboard of an electronic device. Both the first switch unit and the second switch unit selectably and electronically connect to the first CPU or the second CPU according to whether or not both the first switch unit and the second switch unit detect the identification signal. The microcontroller is electronically connected between the first switch unit and the second switch unit, and accordingly communicates with the first CPU or the second CPU via the first switch unit and the second switch unit.

Abstract: A multi-core processor includes a tree-like structure having a plurality of computing cores arranged in hierarchical levels, the cores all having the same logical architecture. Each core can include computing, interconnecting, and/or storage elements. The functionality of an individual element can be supplied by an entire core in a lower level. A method for programming the processor includes hierarchically decomposing an application into interconnected sub-functions, mapping the sub-functions onto groups of cores at appropriate levels of the processor, and interconnecting the mapped sub-functions so as to hierarchically compose the complete application. Sub-functions can be sequential, concurrent, and/or pipelined. Interconnections can be static or dynamically switchable under program control. Interconnect elements can also be used to implement flow control as needed in pipelined operations to maintain data coherency.

Abstract: A scheduler receives at least one flexible reservation request for scheduling in a computing environment comprising consumable resources. The flexible reservation request specifies a duration and at least one required resource. The consumable resources comprise at least one machine resource and at least one floating resource. The scheduler creates a flexible job for the at least one flexible reservation request and places the flexible job in a prioritized job queue for scheduling, wherein the flexible job is prioritizes relative to at least one regular job in the prioritized job queue. The scheduler adds a reservation set to a waiting state for the at least one flexible reservation request.

Abstract: An information processing device which has a plurality of process units for performing various kinds of processes includes a detecting unit that detects a processing loads of the process units; a determining unit that determines whether a total amount of the processing loads detected by the detecting unit is equal to or larger than a specific value; a designating unit that designates a process unit having a process state to be controlled, based on the processing loads of the process units detected by the detecting unit, when the determining unit determines that the total amount is equal to or larger than the specific value; a process identifying unit that identifies a process having an execution state to be controlled among processes being performed by the process unit designated by the designating unit; and a control unit that controls the execution state of the process identified by the process identifying unit.

Abstract: A technique for minimizing overhead caused by copying or moving a value from one cluster to another cluster is provided. A number of operations, for example, a mov operation for moving or copying a value from one cluster to another cluster and a normal operation may be executed concurrently. Accordingly, access to a register file outside of the cluster may be reduced and the performance of code may be improved.

Abstract: A microprocessor integrated circuit includes first and second processors, an internal memory accessible by the first and second processors, and a bus interface unit configured to interface to a bus external to the microprocessor for providing access to a memory external to the microprocessor. The bus interface unit, external bus, and external memory are accessible by the second processor but are inaccessible by the first processor. The first processor writes debug information to the internal memory. The first processor detects an event and provides a notification of the event to the second processor. The second processor, coupled to the bus interface unit, executes microcode in response to the event notification received from the first processor. The microcode reads the debug information from the internal memory and writes the debug information to the external memory via the bus interface unit and external bus for use in debugging the second processor.

Abstract: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Abstract: Establishing a data communications connection between a lightweight kernel in a compute node of a parallel computer and an input-output (‘I/O’) node of the parallel computer, including: configuring the compute node with the network address and port value for data communications with the I/O node; establishing a queue pair on the compute node, the queue pair identified by a queue pair number (‘QPN’); receiving, in the I/O node on the parallel computer from the lightweight kernel, a connection request message; establishing by the I/O node on the I/O node a queue pair identified by a QPN for communications with the compute node; and establishing by the I/O node the requested connection by sending to the lightweight kernel a connection reply message.

Abstract: A micro grid apparatus and associated method of formation. Multiple tiers are formed. The tiers are distributed and sequenced in a vertical direction such that each tier is at a different vertical level in the vertical direction. Each tier includes a multiplicity of complex shapes interconnected by bridge modules. Each complex shape is a physical structure having an exterior boundary. Each complex shape includes multiple docking bays such that each docking bay is configured to have a module latched therein. Each complex shape is either a power hub including rechargeable batteries or a processor hub including processors. A sensor module is latched in a sensor docking bay and an actuator module is latched in an actuator docking bay of each complex shape in one or more tiers of the multiple tiers.

Abstract: A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The processor distributes data on-ramps and data off-ramps across the data lanes of a data trunk of the primary interconnect trunk to enable communication with compute elements and other structures both on-chip and off-chip.

Abstract: The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units CPUs and one node controller NC, where any two CPUs in each basic node are interconnected, each CPU in each basic node is connected to the NC in the basic node, the NC in each basic node has a routing function, any two NCs in the M basic nodes are interconnected, and a connection between the L composite nodes formed through a connection between NCs enable communication between any two NCs to require at most three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

Abstract: A computing apparatus and corresponding method for operating are disclosed. The computing apparatus may comprise a set of interconnected central processing units (CPUs). Each CPU may embed an operating system including a kernel comprising a protocol stack. At least one of the CPUs may further embed executable instructions for allocating multiple strands among the rest of the CPUs. The protocol stack may comprise a Transmission Control Protocol/Internet Protocol (TCP/IP), a User Datagram Protocol/Internet Protocol (UDP/IP) stack, an Internet Control Message Protocol (ICMP) stack or any other suitable Internet protocol. The method for operating the computing apparatus may comprise receiving input/output (I/O) requests, generating multiple strands according to the I/O requests, and allocating the multiple strands to one or more CPUs.

Abstract: A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by a context of execution. In some embodiments, each of the plurality of processing stages may be bound to a processing core of the multi-core processor. In other embodiments include one or more processing stages with a point-to-point communication mechanism that operates in shared memory.

Abstract: Dynamically managing a thread pool associated with a plurality of sub-applications. A request for at least one of the sub-applications is received. A quantity of threads currently assigned to the at least one of the sub-applications is determined. The determined quantity of threads is compared to a predefined maximum thread threshold. A thread in the thread pool is assigned to handle the received request if the determined quantity of threads is not greater than the predefined maximum thread threshold. Embodiments enable control of the quantity of threads within the thread pool assigned to each of the sub-applications. Further embodiments manage the threads for the sub-applications based on latency of the sub-applications.

Abstract: In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer, detecting the assertion signal in the accelerators and communicating a request for a lock, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer. Other embodiments are described and claimed.

Abstract: Data transmission efficiency for structured data can be improved by representing structured data using immutable blocks. The contents of the immutable blocks can include data and/or pointers to immutable blocks. An immutable data block cannot be altered after creation of the block. When data represented as immutable blocks is transmitted from one processor to another processor, the transmitter sends block contents for blocks that have not previously been defined at the receiver, and sends block IDs (as opposed to block contents) for blocks that have previously been defined at the receiver. The systematic use of block IDs instead of block contents in transmission where possible can significantly reduce transmission bandwidth requirements.

Abstract: A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.

Abstract: A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.

Abstract: Disclosed are various embodiments of configurable allocation of hardware resources. In one embodiment, a processing device includes a configurable communication grid including a plurality of crossbars interconnected by intercommunication paths in a geometric configuration and a plurality of pipeline elements distributed within the configurable communication grid. Each crossbar is designed to direct communications received at an input to a selected output. Each pipeline element is communicatively coupled to an output of a first crossbar adjacent to the pipeline element and an input of a second crossbar adjacent to the pipeline element. In another embodiment, a process matrix includes a plurality of pipeline elements interconnected by a configurable communication grid. The configurable communication grid includes intercommunication paths connecting crossbars in a geometric configuration.

Abstract: Communication latency, now a dominant factor in computer performance, makes physical size, density, and interconnect proximity crucial system design considerations. The present invention addresses consequential supercomputing hardware challenges: spatial packing, communication topology, and thermal management. A massively-parallel computer with dense, spherically framed, geodesic processor arrangement is described. As a mimic of the problem domain, it is particularly apt for climate modelling. However, the invention's methods scale well, are largely independent of processor technology, and apply to a wide range of computing tasks. The computer's interconnect features globally short, highly regular, and tightly matched distances. Communication modes supported include neighbour-to-neighbour messaging on a spherical-shell lattice, and a radial network for system-synchronous clocking, broadcast, packet-switched networking, and IO.

Abstract: The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

Abstract: This invention generally relates to one or more computer networks having computers like personal computers or network servers with microprocessors linked by broadband transmission means and having hardware, software, firmware, and other means such that at least one parallel processing operation occurs that involve at least two computers in the network

Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Abstract: Systems, methods of operating a memory device, and methods of arbitrating access to a memory array in a memory device having an internal processor are provided. In one or more embodiments, conflicts in accessing the memory array are reduced by interfacing an external processor, such as a memory controller, with the internal processor, which could be an embedded ALU, through a control interface. The external processor can control access to the memory array, and the internal processor can send signals to the external processor to request access to the memory array. The signals may also request a particular bank in the memory array. In different embodiments, the external processor and the internal processor communicate via the control interface or a standard memory interface to grant access to the memory array, or to a particular bank in the memory array, for example.

Abstract: A multi-core processor system including a main processor, an internal EPON bus, and a plurality of secondary core processors. The main processor includes a processing unit; an offload engine operatively connected to the processing unit for routing data to and from the processing unit; a plurality of main processor optical network units (ONU's) operatively connected to the offload engine; and, a dual optical line terminal (OLT) operatively connected to the offload engine. The internal EPON bus is operatively connected to the OLT. The plurality of secondary core processors are located physically separate from the main processor, each secondary core processor having a respective secondary core processor ONU being operatively connected to the main processor via the internal EPON bus.

Abstract: A detachable, logic leaf module having dendritic projections on a surface is connected to a recessed area on the surface of a cluster interface board. The projections are used for electrically connecting the logic module device to the cluster interface board or the like, the projections on the surface of the logic leaf being flexibly and conductively wired to the receiving area on the surface of the cluster interface board. The logic leaf connector is removable without the need for solder softening thermal cycles or special tools, and permits the simple removal or replacement of an individual leaf at any time.

Abstract: Quantum processors and classical computers are employed together to solve computational problems. The classical computer may include a parameter learning module that produces a set of parameters. The quantum processor may be configured with the set of parameters to define a problem Hamiltonian and operated to perform adiabatic quantum computation and/or quantum annealing on the problem Hamiltonian to return a first solution to the problem. The parameter learning module of the classical computer may then be used to revise the set of parameters by performing a classical optimization, such as a classical heuristic optimization. The quantum processor may then be programmed with the revised set of parameters to return a revised solution to the problem. The quantum processor may include a superconducting quantum processor implementing superconducting flux qubits.

Abstract: Embodiments of an apparatus including a first processor core having a local agent running thereon, the agent comprising a local process and a proxy agent and a second processor core having a remote agent running thereon, the remote agent being an instance of the local agent. A shared memory wherein coupled to the first processor core and the second processor core, wherein the local agent and the remote agent communicate via the shared memory. Other embodiments are disclosed and claimed.

Abstract: Systems and methods for accessing common registers in a multi-core processor are disclosed. In an exemplary embodiment a method may comprise streaming at least one transaction from one of a plurality of processing cores in a core domain directly to a register domain. The method may also comprise reassembling the at least one streamed transaction in the register domain for data access operations at the common registers.

Abstract: Synchronizing access to resources in a hybrid computing environment that includes a host computer, a plurality of accelerators, the host computer and the accelerators adapted to one another for data communications by a system level message passing module, where synchronizing access to resources includes providing in a registry, to processes executing on the accelerators and the host computer, a key associated with a resource, the key having a value; attempting, by a process, to access the resource including determining whether a current value of the key represents an unlocked state for the resource; if the current value represents an unlocked state, attempting to lock access to the resource including setting the value to a unique identification of the process; determining whether the current value is the unique identification of the process; if the current value is the unique identification accessing the resource by the process.

Abstract: A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.

Abstract: An image display device that controls an external device and a method therefore are provided. The image display device includes an interface unit which is connected to an external device, a determining unit which determines whether another external device that has a control ownership of the external device exists, and a control unit which registers the control ownership of the external device if it is determined that the other external device does not exist. The external device is controlled by registering the control ownership.

Abstract: A process for maintaining synchronization of processors that are executing a same plurality of applications in parallel includes interrupting a current task between processing two successive instructions of an application being processed when an interrupt request occurs to process another application. An intermediate state reached by the current task is saved when the interrupt request occurs, and a counter for each of the processors indicating a number of instructions processed by each of the processors is maintained. A processor is caused to issue a synchronization confirmation in response to a comparison result that the numbers of instructions processed are identical. The processor is caused to enter a wait state when its number of processed-instructions is the largest among the processors or to execute a procedure for processing the instructions until its processed-instruction counter reaches the largest number.

Abstract: This invention describes an apparatus, architecture, method, operating system, data network, and application program products for a hybrid digital system with multiple heterogeneous components. This invention is applied to a multiple generic microprocessor architecture s with a set (e.g., one or more cores) of controlling components and a set of groups of sub-processing components. Under this arrangement, different technology cores and functional components, such as memory, are organized in a way that different technologies can collaborate as a system.

Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

Abstract: A method for controlling an information processing apparatus including a processor which operates an operating system and a kernel which is operated independently of the operating system, and a network interface through which the information processing apparatus is connectable to an other information processing apparatus, the method includes notifying, by the operating system, the kernel of system down information about the operating system, determining, by the kernel, a kind of an Internet protocol included in a packet received from the other information processing apparatus connected through the network interface, creating, by the kernel, a packet for notifying of the system down in accordance with the determined kind of the Internet protocol, and transmitting, by the kernel, the created packet to the other information processing apparatus via the network interface.

Abstract: The present invention provides embodiments of an apparatus used to implement a pipelined serial ring bus. One embodiment of the apparatus includes one or more ring buses configured to communicatively couple registers associated with logical elements in a processor. The ring bus(s) are configured to concurrently convey information associated with a plurality of load or store operations.

Abstract: A system and method for process synchronization in a multi-core computer system. A separate non-caching memory enables a method to synchronize processes executing on multiple processor cores. Since only a very small amount (a few number of bytes), is needed for the synchronization, it is possible to extend the method for inter-processor core message passing by allocating dedicated address space of the on-chip memory for each processor with exclusive write access. Each of the multiple processor cores maintains a dedicated cache while maintaining coherency with the non-cache shared memory.

Abstract: A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.

Abstract: An integrated circuit includes a plurality of tiles, and a plurality of interface modules coupled to the switches of a subset of the tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles. At least some of the interface modules are configured to multiplex data from one or more parallel communication links of the switch to an multiplexed communication link having reduced parallelization, and mediate between a network protocol of the switch and a communication protocol of the multiplexed communication link.

Abstract: A distributed processing system is described that employs “application-based” specialization. In particular, the distributed processing system is constructed as a collection of computing nodes in which each computing node performs a particular processing role within the operation of the overall distributed processing system. Each of the computing nodes includes an operating system, such as the Linux operating system, and includes a plug-in software module to provide a distributed memory operating system that employs the role-based computing techniques. An administration node maintains a database that defines a plurality of application roles. Each role is associated with a software application, and specifies a set of software components necessary for execution of the software application. The administration node deploys the software components to the application nodes in accordance with the application roles associates with each of the application nodes.

Abstract: A system and method which provides for efficient data transmission between multiple microprocessors in a computer system is disclosed. A physical data path is divided into one or more data queues which may be virtual connection queues. The virtual connection queues are configured to adaptively split or merge based on traffic conditions therein.

Abstract: A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and a module manager for managing its own server module, the module manager has an ID determiner for informing each processor of a processor ID, each processor has a processing unit and an SMP virtual connecting unit for instructing ones of wiring lines of the SMP coupling device through which a packet received from the processing unit is to be transmitted, and an ID converter for converting the processor ID and informing it to the virtual connecting unit is provided within the firmware.

Abstract: A single instruction multiple data (SIMD) processor having a plurality of processing elements and including: a splitting unit for splitting an address of the read-only parameter data in the data memory into a first part and a second part at a bit position corresponding to the number of the processor elements; and a comparing unit for comparing the number of shifting, on a ring bus, of the read-only parameter data, which is taken from the internal memory at the address in accordance with the first part, with a difference between an own processor element position and a portion of the global address of the read-only parameter data to be accessed, the portion designating a position in the ring of the processor element in which the read-only parameter data to be accessed is stored and corresponding to the second part, to cause the other processor elements to take the read-only parameter data.

Abstract: A processing system comprises a plurality of processors (12) and communication means (20) arranged to carry messages between the processors, wherein each of the processors (12) has an operating instruction memory field (32, 34, 36) arranged to hold stored operating instructions including a re-routing target address. Each processor is arranged to receive a message (38) including operating instructions including a target address.

Abstract: A processing system includes a group of processing units (“PUs”) arranged in a daisy chain configuration or a sequence capable of parallel processing. The processing system, in one embodiment, includes PUs, a demultiplexer (“demux”), and a multiplexer (“mux”). The PUs are connected or linked in a sequence or a daisy chain configuration wherein a first PU is located at the beginning of the sequence and a last digital PU is located at the end of the sequence. Each PU is configured to read an input data packet from a packet stream during a designated reading time frame. If the time frame is outside of the designated reading time frame, a PU allows a packet stream to pass through. The demux forwards a packet stream to the first digital processing unit. The mux receives a packet steam from the last digital processing unit.