Abstract: An image forming device includes a plurality of input units, a plurality of processing units, and a plurality of output units which are arranged to perform image-data processing. The image forming device includes a processing operation executing unit configured to instruct a processing operation of each of a predetermined input unit, a predetermined processing unit, and a predetermined output unit. A controlled unit reporting unit is configured in the processing operation executing unit to notify a controlled unit of processing to be performed, to each of the predetermined input unit, the predetermined processing unit, and the predetermined output unit.

Abstract: In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties.

Abstract: A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Abstract: Instructions executed by a plurality of processors including a specific processor and the other processors connected to the specific processor are stored in an instruction storage memory. The instructions stored in the instruction storage memory are transferred to and retained in an instruction execution memory, and when an instruction is executed by one of the plurality of processors, a required instruction is retrieved by the processor. A leading address of a position where the required instruction of the other processors is retained in the instruction execution memory is stored in an address storage memory. A memory control circuit coordinates access to the instruction execution memory by the plurality of processors and controls access to the address storage memory by the specific processor.

Abstract: Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during system boot in a links-based multi-processor system. Some embodiments synchronize data block by block through memory rather than piece by piece through registers by allowing a System Bootstrap Processor (“SBSP”) to directly access synchronization data in local memory of each of one or more Application Processors. These and other embodiments are described in greater detail below.

Abstract: A device comprises a programmable communication interface and a processor. The programmable communication interface communicates data via a set of signals. The processor configures the programmable communication interface to communicate the data in accordance with a programmed override state for at least one of the signals and actual states for the remaining signals. The programmable communication interface may be configured, for example, to programmably treat an overridden signal as asserted or de-asserted regardless of actual voltages present on one or more electrical connectors associated with the overridden signal. As a result, incorrectly wired electrical connectors of the programmable communication interface may be programmably overridden. Consequently, a technician need not manually rewire the programmable communication interface.

Abstract: A signal processing device adapted for simultaneous processing of at least two process threads in a multi-processing manner is disclosed. In one embodiment, the device comprises a plurality of functional units capable of executing word- or subword-level operations on data. The device further comprises means for interconnecting the plurality of functional units, the means for interconnecting supporting a plurality of dynamically switchable interconnect arrangements, and at least one of the interconnect arrangements interconnects the plurality of functional units into at least two non-overlapping processing units each with a pre-determined topology. The device further comprises at least two control modules each assigned to one of the processing units.

Abstract: A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy.

Abstract: A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a first instruction set, a second processor core including a plurality of second functional units which execute a second instruction set, and a coarse grained array including a plurality of third functional units which execute a portion of instructions of the first instruction set and/or the second instruction set, instead of the first processor core and/or the second processor core.

Abstract: A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by a context of execution. In some embodiments, each of the plurality of processing stages may be bound to a processing core of the multi-core processor. In other embodiments include one or more processing stages with a point-to-point communication mechanism that operates in shared memory.

Abstract: A computer-readable medium may include one or more instructions for providing sub-images, one or more instructions for receiving selection of a plurality of sub-images, one or more instructions for constructing a first image, the first image being a unified image including the selected plurality of sub-images, one or more instructions for comparing at the selected plurality of sub-images with previously selected sub-images, and one or more instructions for providing access to at least one of a device, a service, or a function when the selected plurality of sub-images match the previously selected sub-images.

Abstract: A processor array system which is able to perform load balancing among PEs at high speed is provided. When an instruction code 113, “MVLR”, is sent from a control processor 110, in a PE having a mask register MR being in operation setting, in case wherein the direction register F is ON, if a counter and transfer result storing buffer T is greater than or equal to M, a value of T?M is stored in T, and if T is less than M, content of a first transport register L of a PE whose PE number counted from the left inside a PE block is T, is selected by a first selector LS to be stored to in to a transfer result buffer T and the mask register is set to non-operation. On the other hand, in case wherein the direction register F is OFF, if T is less than or equal to ?M, a value of T+M is stored in T, and if T is greater than ?M, content of R of a PE whose PE number is ?T, counted from the right inside the PE block, is selected by a second selector RS to be stored in T, and MR is set to non-operation.

Abstract: An integrated circuit for implementing the secure hash algorithm is provided. According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller further includes an address control module and a finite state machine.

Abstract: There is provided a reconfigurable device that includes a plurality of processing blocks (13), wherein operation logic of each processing block is changeable, and a routing matrix (15) for configuring paths that connect the plurality of the processing blocks. Each processing block (13) includes a logic operation unit (21) whose logic is determined by configuration data (17) and a storage unit (40) for storing processing results of the logic operation unit. Each storage unit (40) includes a plurality of storage elements (31r), input means (32) for selecting one of the plurality of storage elements (31r) based on the configuration data (17) to store the output of the logic operation unit (21), and output means (33) for connecting the plurality of storage elements (31r) to the routing matrix (15).

Abstract: Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip.

Abstract: A multiprocessing method and a multiprocessor system capable of reducing time lost due to sequential waiting when procedures (program units) having dependencies are executed in which an order of execution of a plurality of program units in a sequential execution program and dependencies of the plurality of program units are registered, the execution states of the plurality of program units are managed based on the registered dependencies, executable program units are determined, and are assigned to server processors sequentially and executed are disclosed.

Abstract: A fault-tolerant self-optimizing multi-processor system is disclosed that includes a plurality of redundant network switching units and a plurality of processors electrically coupled to the network switching units. Each processor comprises a local memory, local storage, multiple network interfaces and a routing agent (RA). The RAs form a unidirectional virtual ring (UVR) network using the redundant network switching units. The UVR network may coordinate all of the processors for data matching, failure detection/recovery and system management functions. Once data is matched via the UVR network, application programs communicate directly via the network switching units, thus fully exploiting the hardware redundancy. Each of the RAs may implement a tuple space daemon responsible for data matching and delivery, forwarding unsatisfied data requests to a downstream processor or dropping expired tuples from UVR circulation.

Abstract: A computer system including a plurality of physical processors (CPs) having physical processor performances (PCPs), a plurality of logical processors (LCPs), a plurality of logical partitions (LPARs) where each partition includes one or more of the logical processors (LCPs), and a system assist processor having a control element. The control element controls the virtualization of the physical processors (CPs), the logical partitions (LPARs) and the logical processors (LCPs) and allocates the physical processor performances (PCPs) to the logical partitions (LPARs). The control element operates to exclusively bind logical processors (LCPs) to the physical processors (CPs). For a logical processor (LCP) exclusively bound to a physical processor (CP), the logical processor (LCP) has exclusive use of the underlying physical processor (CP) and no other logical processor (LCP) can be dispatched on the underlying physical processor (CP) even if the underlying physical processor (CP) is otherwise available.

Abstract: A master device for managing a communications link to slave devices (for example in the context of a Wireless USB cluster), wherein the master device is configured to facilitate avoidance of unnecessary waking of the slave devices.

Abstract: A buffer device that transfers data and is shared by a plurality of CPU cores arranged in a symmetrically inverted manner about a predetermined reference line, each CPU core breaking up a data block into a plurality of data lines and outputting the data lines via a plurality of ports, includes a plurality of line buffers that correspond to the data lines and are connected to the ports in the CPU cores, wherein the line buffers are paired into line buffer groups, and the line buffers in each buffer group are arranged symmetrically about the reference line.

Abstract: A system and method which provides for efficient data transmission between multiple microprocessors in a computer system is disclosed. A physical data path is divided into one or more data queues which may be virtual connection queues. The virtual connection queues are configured to adaptively split or merge based on traffic conditions therein.

Abstract: An asynchronous communicating part executes an asynchronous communication between a first device and a second device. A first process executing part executes a processing in the first device by use of the asynchronous communication as a trigger. A second process executing part executes a processing in the second device by use of the asynchronous communication as a trigger. A trigger signal sending part sends a trigger signal from the first device to the second device. A response signal replying part replies a response signal from the second device to the first device when the second device receives the trigger signal. Thus, the first process executing part and the second process executing part execute the processing in the first device and the second device using the asynchronous communication as the trigger, so that the processing in the first device and the processing in the second device are synchronized.

Abstract: A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.

Abstract: In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific 5 processor without using a locking mechanism specific to the resources required for assignment.

Abstract: A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

Abstract: Methods and apparatus provide for a multiprocessor system including: a plurality of sub-processors operatively coupled to one another over a ring bus, whereby data may be transmitted over one or more paths on the ring bus between pairs of the sub-processors; and a plurality of programmable delay circuits, each associated with at least one of the sub-processors, and each being operable to alter a delay of data transfer at least one of into and out of its associated sub-processor in order to alter one or more latencies associated with the paths on the ring bus between pairs of the sub-processors.

Abstract: Authoring a plurality of digital image records, each digital image record corresponding to a separate customer order, in a digital image record authoring system including a dedicated computer, including scanning a plurality of images corresponding to a separate customer order from a scanner into a plurality of digital images, the scanner being connected to the dedicated computer by a first interface bus, processing the plurality of digital images and combining the processed plurality of digital images into a record image, and writing the record image by an image-recorder to a medium, the image-recorder being connected to the dedicated computer by a second interface bus, wherein the scanning is repeated, prior to completion of the writing of the previous record image, to scan a new plurality of images corresponding to a new customer order from the scanner into a new plurality of digital images.

Abstract: An array of universal digital blocks include programmable logic device sections that have uncommitted user programmable logic functions and structural datapath sections that include dedicated and highly configurable arithmetic operators. A routing channel matrix programmably connects to different programmable logic device sections and datapath sections in the different universal digital blocks.

Abstract: In order to detect objects using a processor element for use in a network of processor elements which are connected to one another, the processor element comprises a processor, at least one interface for coupling to further processor elements of the network and an oscillator having a connection for coupling to an electrode outside the processor element.

Abstract: The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a GSM telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing. In the preferred embodiment, the configuration and reconfiguration occurs to adaptively optimize the performance of the particular activity over time, such as to increase the speed of channel acquisition, increase throughput rates, increase perceived voice and media quality, and decrease the rate of dropped communication sessions.

Abstract: An image processing apparatus is disclosed that includes an image processing unit section and an information processing unit section. The image processing unit section includes an image scanner that performs an image processing function and a SDK application that expands and controls the function of the image processing apparatus. The information processing unit section includes an operations panel that selectively performs operations between a basic application and the SDK application and a MFP service that transmits an instruction signal to the SDK application so as to control the image scanner in accordance with the operation on the operations panel. The information processing unit section confirms the corresponding relationship between the MFP service and the SDK application when the image processing apparatus performs a starting process and makes the SDK application correspond to the MFP service in accordance with the confirmation results.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging net work is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is stored in a corresponding one of the memory blocks. In a read-modify-write operation, each byte of the data value is read from the corresponding memory block, and is provided to the corresponding ALU. Similarly, each byte of a modify data value is provided to a corresponding ALU on a memory data bus. Each ALU combines the read byte with the modify byte to create a write byte. Because the write bytes are all generated locally within the ALUs, long signal delay paths are avoided. Each ALU also generates two possible carry bits in parallel, and then uses the actual received carry bit to select from the two possible carry bits.

Abstract: A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared memories. This sequencer/synchronizer controls multi-threading access to shared memory.

Abstract: A reconfigurable multiprocessor system including a number of processing units and components enabling executing sequential code collectively at processing units and enabling changing the architectural configuration of the processing units.

Abstract: The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second processing units. Each of the first and second processing units has a respective first output data bus. The first output data bus of the first processing unit is coupled to the second processing unit, and the first output data bus of the second processing unit is coupled to the first processing unit. At least the first processing unit of the first processing book and the second processing unit of the second processing book each have a respective second output data bus.

Abstract: A first storing unit stores therein a chain indivisibility instruction. A detecting unit detects a change of first data that is distributed in a node computer. A first designating unit designates, when the detecting unit detects the change in the first data, an indivisibility instruction corresponding to the first data from which the change is detected, by referring to the first storing unit. A first executing unit executes the indivisibility instruction designated by the first designating unit.

Abstract: A fast pattern processor having an internal function bus and an external function bus. In one embodiment, a fast pattern processor includes: (1) an internal function bus, (2) an external function bus, (3) a context memory having a block buffer and a argument signature register wherein the block buffer includes processing blocks associated with a protocol data unit (PDU), (4) a pattern processing engine, associated with the context memory, that performs pattern matching and (5) a function interface system having (5A) a controller arbitration subsystem and (5B) a dispatch subsystem.

Abstract: A control system with a plurality of devices connected through a network may be started up by connecting a control system setting device including a computer accessible to profile data which describe characteristics of these devices and to program parts for programs executed by these devices. The profile data are prepared individually for the devices, and at least some of them include program part data that specify program parts for at least some of the devices. A memory device stores a control system setting program for creating programs executable by at least some of the devices.

Abstract: The present invention relates generally to interfacing a processor with at least one coprocessor. One embodiment relates to a processor having a set of broadcast specifiers which it uses to selectively broadcast an operand that is being written to a register within the processor to a coprocessor communication bus. Each broadcast specifier may therefore include a broadcast indicator corresponding to each general purpose register of the processor. An alternate embodiment may also use the concept of broadcast regions where each broadcast region may have a corresponding broadcast specifier where one broadcast specifier may correspond to multiple broadcast regions. Alternatively, in one embodiment, the processor may use broadcast regions independent of the broadcast specifiers where the coprocessor is able to alter its functionality in response to the current broadcast region.

Abstract: A system and method of designing an accelerator for a processor-based system. The accelerator design problem is partitioned into a data communicate module design problem and a data compute core module design problem. The hardware design of the data communicate module is achieved through a predetermined communication template which is customized for the particular application. The communication template has individual configurable communication components and a programmable control flow path. The components of the communicate template include a host bus interface, a memory bus interface, a direct memory access, a local memory and a control module. The combination of the communication components in a single configurable communication template and their optimized interconnections increase the speed of data transfer and data control processes in the accelerator.

Abstract: A system and method for automatically identifying a desirable reconfiguration of computer system resources, using a perceptron to determine whether one resource configuration will likely be more efficient or more effective than a second configuration. An iterative solver identifies possible configurations or reconfigurations of the resources. A possible configuration is applied to the perceptron, which determines whether the new configuration is more attractive than an existing or baseline configuration, in terms of a predetermined objective function (e.g., cost, performance, resource utilization, throughput). If the new configuration improves the objective function, the new configuration may be automatically or manually applied through a dynamic reconfiguration operation.

Abstract: A system for automating an operating parameter list process includes a web-based interface for accessing OPL data. Databases are provided for storing updated OPL parameter values for use in resolving the OPL process with respect to a particular operation cycle. The OPL data is provided in a format that is accessed and modified by various parties, with updates and notifications provided accordingly. Access to past OPL cycles is also provided.

Abstract: Systems and methods that allow for performing a single transaction that both instructs a device to perform an operation and return the resulting data to a processor without the processor having to send a separate request for the result. In accordance with the systems and methods, a bus controller generates a system bus operation that sends (to the device) a thread identifier and a data request formulated in one thread by a processor that context switches to a second thread.

Abstract: A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communication paths and/or the I/O paths. Each processor is provided with a local memory which can be accessed by the local processor as well as by the other processors via the communications paths. This allows for efficient data movement from one processor's local memory to another processor's local memory, such as commonly done during signal processing corner turning operations. The configurable signal processing logic may be configured to host one or more signal processing functions to allow data to be processed prior to its deposit into local memory.

Abstract: Disclosed is a computer processor (300) comprising a plurality of processing units (FU_n) and communication means (302) by which the plurality of processing units are interconnected. The communication means is dynamically configurable based on a computer program to be processed such that the processing units can selectively be arranged in at least first and second distinct configurations. The first distinct configuration (eg. FIG. 5) has a larger number of the processing units arranged in parallel than the second distinct configuration (eg. FIG. 6), and the second distinct configuration has a deeper pipeline depth than the first distinct configuration.

Abstract: A peripheral component interconnect (PCI) device comprising a bus interface coupled to a component interconnect bus, a plurality of configuration space register sets, and virtual multiple-function logic. Each set of configuration space registers is associated with a function. The virtual multiple-function logic is coupled to the bus interface and the configuration space register sets. The virtual multiple-function logic provides access to a plurality of configuration space registers for a plurality of functions. The virtual multiple-function logic also enables a plurality of functions to share the bus interface and other internal logic.