Abstract: A data processing module includes: a data converter having a TranslateData interface for receiving input data and sending output data, a Property interface for sending and receiving parameter data composed of a character string parameter for Property control, and Open/Close interface for initializing the environment and the state, a query interface for obtaining entries of the internal interfaces of the Open/Close interface, the TranslateData interface, and the Property interface, an API interface for dynamically obtaining by the query interface the four kinds of interfaces of the Open, Close, Property, and TranslateData, and a callback interface designated by the Property interface.

Abstract: In accordance with embodiments, there are provided mechanisms and methods for providing interceptors between producer(s) and consumer(s) of content in a remote portal system. These mechanisms and methods for providing interceptors between producer(s) and consumer(s) of content can enable embodiments to provide improved functionality and/or flexibility to systems comprising remote portals. The ability of embodiments to provide improved functionality and/or flexibility can enable end users, systems programmers and so forth to obtain greater value from remote portal installations.

Abstract: Certain embodiments of the invention may be found in a method and system for processing messages. Aspects of the method may comprise receiving at least one signal on a chip that controls switching from a core processor to a DSP. At least a first bus that couples the core processor to a message processor and at least a first clock signal that clocks the core processor may be switched. At least a second bus that couples the DSP to the message processor and at least a second clock signal that clocks the DSP may be switched. When a loss of clock signal from the core processor or the DSP to the message processor is detected, a third clock signal for clocking the message processor may be generated. The message processor switch significantly reduces the amount of bandwidth utilized for transfer of data between the core processor and the DSP and provides incremental redundancy (IR) without high hardware cost and software MIPS, thereby providing significant improvement in system performance.

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: A multi-processing system-on-chip including a cluster of processors having respective CPUs is operated by: defining a master CPU within the respective CPUs to coordinate operation of said multi-processing system, running on the CPU a cluster manager agent. The cluster manager agent is adapted to dynamically migrate software processes between the CPUs of said plurality and change power settings therein.

Abstract: A device comprises a programmable communication interface and a processor. The programmable communication interface communicates data via a set of signals. The processor configures the programmable communication interface to communicate the data in accordance with a programmed override state for at least one of the signals and actual states for the remaining signals. The programmable communication interface may be configured, for example, to programmably treat an overridden signal as asserted or de-asserted regardless of actual voltages present on one or more electrical connectors associated with the overridden signal. As a result, incorrectly wired electrical connectors of the programmable communication interface may be programmably overridden. Consequently, a technician need not manually rewire the programmable communication interface.

Abstract: A modular avionics system includes several cabinets arranged at various locations in an aircraft and interconnected in a network. The cabinets are used for controlling or processing signals from and to sensors, actuators and other systems of the aircraft. The system includes parallel processors, for example transputers. The cabinets comprise at least two core processor modules (CPM1, CPM2) and at least two input/output modules (IOM1, IOM2). The input/output modules (IOM1, IOM2) serve as interfaces to the systems to be controlled, and serve for the control and intermediate storage of the data flowing into and out of the cabinet. Each core processor module (CPM1, CPM2) communicates independently with each IOM module and CPM module by way of links; and in each core processor a number of independent system programs works under the control of an operating system.

Abstract: The invention relates to a multiprocessor system on an electronic chip (300) comprising at least two computing tiles, each of the computing tiles comprising a generalist processor, and means for access to a communication network (320), the said computing tiles being connected together via the said communication network, the said multiprocessor system being characterized in that: a generalist processor using an instruction set which defines all the operations to be executed by the said processor, the generalist processors have one and the same instruction set; at least one of the computing tiles also comprises an accelerator coupled to the generalist processor accelerating computing tasks of the said generalist processor.

Abstract: An integrated circuit (100) is disclosed that comprises a plurality of data processing stages (110) and a data communication network comprising a plurality of data communication paths between the data processing stages (110). Each data processing stage (110) comprises a hardware layer (160) for processing data received through a data communication path and a software layer (120) arranged to communicate with the software layers of selected other data processing stages for controlling the synchronization of the data communication between the data processing stage (110) and the selected other data processing stages in response to dynamically assigned communication relationships between data processing stage (110) and the respective selected other data processing stages.

Abstract: A multiprocessor computer system having a plurality of processing elements comprises one or more core-level hierarchical shared semaphore registers, wherein each core-level hierarchical shared semaphore register is coupled to a different processor core. Each hierarchical shared semaphore register is writable to each of a plurality of streams executing on the coupled processor core. One or more chip-level hierarchical shared semaphore registers are also coupled to plurality of processor cores, each chip-level hierarchical shared semaphore register writable to each of the plurality of processor cores.

Abstract: A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.

Abstract: In a configuration provided with, for example, sixty four pieces of processor cores, an on-chip-memory, a bus commonly connected thereto, and others, the processor cores are operated by a power supply with low voltage and a clock with low frequency, and the bus is operated by a power supply with high voltage and a clock with high frequency. Each of the processor cores is provided with a bus interface and a frequency divider in order to absorb a power supply voltage difference and a frequency difference between the bus and each of them. The frequency divider generates the clock with low frequency from the clock with high frequency, and the bus interface is provided with a level shifting function, a data width converting function, a hand shaking function between the bus and the bus interface, and the like.

Abstract: A single channel or multi-channel system that requires the execution time of a pipeline stage to be extended to a time longer than the time interval between two consecutive input data. Each processor in the system has an input and output port connected to a “bypass switch” (or multiplexer). Input date is sent either to a processor, for processing, or to a processor output port, in which case no processing is performed, through a register using at least one clock cycle to move date from register input to register output. For a single channel requiring an execution time twice the time interval between two consecutive input data, two processors are interconnected by the bypass switch. Data flows from the first processor at the input of the system, through the bypass switches of the interconnected processors, to the output. The bypass switches are configures with respect to the processors such that the system data rate is independent of processor number.

Abstract: A multiprocessor system according to an embodiment comprises a plurality of processors, an execution control unit to control processing by the plurality of processors and data transfer between the plurality of processors; and an internal data storage unit to store data dependence information indicating status of the data transfer. If control flow of processing by a processor is fixed after a preceding data transfer is registered for execution and another data transfer to a similar destination as the preceding data transfer is necessary, the execution control unit cancels the preceding data transfer based on the data dependence information.

Abstract: Methods, apparatus, and products are disclosed for configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks, the compute nodes in the operational group connected together for data communications through a global combining network, that include: partitioning the compute nodes in the operational group into a plurality of non-overlapping subgroups; designating one compute node from each of the non-overlapping subgroups as a master node; and assigning, to the compute nodes in each of the non-overlapping subgroups, class routing instructions that organize the compute nodes in that non-overlapping subgroup as a collective network such that the master node is a physical root.

Abstract: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.

Abstract: The present invention provides a control pipeline architecture and a pipeline processing system thereof, which is applicable to digital and analog integrated circuit (IC) design flow for convenient hardware implementation. In which, a closed loop control pipeline architecture includes a plurality of control units, and each of the control units connected in series connection with one another to form a closed loop architecture to link an output of one control unit to an input of one next control unit; and an open loop control pipeline architecture included a plurality of control units, each of the control units connected in series connection with one another to form an open loop architecture to link an output of one control unit to an input of one next control unit.

Abstract: A multiprocessor system is provided, comprising a baseboard, for arranging peripheral equipments; and a plurality of processor modules, each equipped with a processor and a board-to-board connector; wherein the plurality of processor modules are stacked up, with board-to-board connectors being electrically connected between the processor modules and between the processor modules and the baseboard; the processors communicate with the peripheral equipments in accordance with a specific bus specification; and the operations of the plurality of processor modules are coordinated by routes provided between the processor modules and between the processor modules and the baseboard.

Abstract: A method for implementing a stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processors via a local interconnection means (“interconnect”), and communicatively coupling the cluster to an optical circuit switch (OCS), via optical external links (“links”). The OCS is communicatively coupled to another cluster of processors via the links. The method also includes generating a stream computation graph including kernels and data streams, and mapping the graph to the SCP system, which includes assigning the kernels to the clusters and respective nodes, assigning data stream traffic between the kernels to the interconnection when the data stream is between nodes in the same cluster, and assigning traffic between the kernels to the links when the data stream is between nodes in different clusters.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: A technique that improves both processor performance and associated data bandwidth through user-defined interfaces that can be added to a configurable and extensible microprocessor core. These interfaces can be used to communicate status or control information and to achieve synchronization between the processor and any external device including other processors. These interfaces can also be used to achieve data transfer at the rate of one data element per interface in every clock cycle. This technique makes it possible to design multiprocessor SOC systems with high-speed data transfer between processors without using the memory subsystem. Such a system and design methodology offers a complete shift from the standard bus-based architecture and allows designers to treat processors more like true computational units, so that designers can more effectively utilize programmable solutions rather than design dedicated hardware.

Abstract: A system including a CPU including logic for executing code from a location and at a time determined by an external entity, a data cache and a CPU management entity (CME) including logic for receiving data one unit at a time from an external data feeder. The data unit being arbitrarily defined mutually between the data feeder and the CME. The CME being coupled to the CPU. The CME including logic to provide the received data unit, a corresponding context information and a corresponding code address to the CPU, wherein the CPU includes logic for notifying the CME of a completed execution.

Abstract: Circuit arrangement having a chip card controller with connections which can be used to access the chip card controller in accordance with the ISO standard and which are connected or can be connected to an ISO interface. The connections include at least one first connection, which can be connected to the ISO interface via a switch device. In addition, the circuit arrangement includes a further controller with at least one controller connection which is coupled to the switch device such that the first connection of the chip card controller can be connected to the controller connection via the switch device. The switch device can be switched between a first and a second state, where in the first state the first connection of the chip card controller is decoupled from the controller connection and is connected to the ISO interface, and where in the second state the first connection of the chip card controller is decoupled from the ISO interface and is connected to the controller connection.

Abstract: In general, techniques for secure communicating over a virtual IPMB of a mainframe computing system are described herein. More specifically, the mainframe computing system comprises a plurality of independent computing cells communicatively coupled together by a network interconnect and that form a plurality of partitions. Each partition is a logical association of one or more of the cells to define a single execution environment. Each cell further executes a virtual intelligent platform management interface (IPMI) protocol to define and configure a respective logical intelligent platform management bus (IPMB) for each of the partitions. Each of the IPMBs logically interconnects with each of the other cells included within the same partition, and each is defined for communication of IMPI messages over the network interconnect. The cells securely communicate the IPMI messages between each of the one or more other cells of each partition via the respective logical IPMB of each partition.

Abstract: The present invention relates to a method for selecting a node in a network system and a system thereof. The method performs a writing operation on a majority of the nodes included in at least one cell selected by dividing a network area including a plurality of nodes existing on a large-capacity cluster into a plurality of cells and performs a reading work on the majority of the nodes included in the cells selected by selecting predetermined cells of the divided cells. The present invention minimizes the accessibility of the network by binding the adjacent nodes to form the cells and access to each cell and optimizes hierarchy for the network access by selecting the node for each cell, thereby making it possible to minimize the network access cost.

Abstract: A device for soft decoding contains a set of operational elements, each being capable of performing one of several different functions. The operational elements may be dynamically configured with input and output connections to registers, memory locations, and other operational elements to perform various steps in a soft decoding scheme. In many cases, the operational elements may be configured to operate in a pipeline mode where many sequences of operations may be performed in parallel. Some embodiments may be reconfigured at each clock cycle to perform different steps during a decoding operation. The device may be used to perform several different soft decoding schemes with the flexibility of a programmable processor but the throughput of a hardware implementation.

Abstract: Aspects for reducing the time-to-market concerns for embedded system design are described. The aspects include providing an infrastructure to support a plurality of heterogeneous processing nodes as a reconfigurable network. Further included is utilizing the infrastructure to customize at least one of the heterogeneous processing nodes according to individualized design needs to achieve a desired embedded system signal processing engine.

Abstract: Provided are a multi-processor system and a multi-processing method in the multi-processor system. The multi-processor system comprises a plurality of processors each including a data core and a processing core; and switches connecting the data core to the processing core in each of the processors as a combination of a data core-processing core pair. Therefore, the multi-processor system may be useful to remove any overhead for communications and make programming easy and simple.

Abstract: Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, each of a plurality of the IP blocks including at least one computer processor, each such computer processor implementing a plurality of hardware threads of execution; low latency, high bandwidth application messaging interconnects; memory communications controllers; network interface controllers; and routers; each of the IP blocks adapted to a router through a separate one of the low latency, high bandwidth application messaging interconnects, a separate one of the memory communications controllers, and a separate one of the network interface controllers; each application messaging interconnect abstracting into an architected state of each processor, for manipulation by computer programs executing on the processor, hardware inter-thread communications among the hardware threads of execution; each memory communications controller controlling communication between an IP block and memory; each network interface contro

Abstract: An integrated circuit with selectable input/output includes a first processor configured to execute instructions, an input/output interface configured to receive and transmit standard input/output communications, an inter-processor interface configured to process interprocessor communications with a second processor, and selection circuitry coupled to both the input/output interface and the inter-processor interface and configured to select between the input/output interface and the inter-processor interface.

Abstract: A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses.

Abstract: A multiprocessor system can directly transmit storage-state information in a multilink architecture. The multiprocessor system includes a first processor; a multiport semiconductor memory device coupled to the first processor; a nonvolatile semiconductor memory device; and a second processor coupled with the multiport semiconductor memory device and the nonvolatile semiconductor memory device in a multilink architecture, storing data, having been written in a shared memory area of the multiport semiconductor memory device by the first processor, in the nonvolatile semiconductor memory device, and directly transmitting storage-state information on whether the storing of the data in the nonvolatile semiconductor memory device has been completed, in response to a request of the first processor, without passing it through the multiport semiconductor memory device.

Abstract: In one embodiment, the present invention includes an apparatus having a first interface to process data for communication according to at least first and second protocols, a second interface to process data for communication according to at least the first and second protocols, and a common buffer coupled to the first and second interfaces to temporarily store the data. In another embodiment, a passive interposer includes at least one interconnect. The passive interposer can be coupled to an unpopulated socket of a system to route signals from a first processor to a device coupled to the unpopulated socket. Other embodiments are described and claimed.

Abstract: One aspect relates to a computer system including a first data processing unit, a second data processing unit and a data transmission/memory device. The data transmission/memory can transmit sets of data from the first data processing unit to the second data processing unit. The data transmission/memory device includes a first memory region and a second memory region.

Abstract: Introduced is an end-point bridge that relays an end point—formed by an external bus in a device tree managed by a first processor unit and an end point formed by an external bus in a device tree managed by a second processor unit. A conversion unit in the end-point bridge replaces a requestor ID contained in an access request packet, for example, which has reached the end point, to the ID of the end point from the ID of a host bridge. The ID of the host bridge is stored in a memory in a manner that the ID of the host bridge is associated with a tag of the packet, and is used to return the requestor ID when a response packet to the request reaches the end point.

Abstract: A chip having an intelligent fabric may include a soft application processor, a reconfigurable hardware intelligent processor, a partitioned memory storage, and an interface to an external reconfigurable communication processor. The reconfigurable hardware intelligent processor may be configured to implement a distributed reconfigurable processor, and to provide cognitive control for at least one of allocation, reallocation, and performance monitoring.

Abstract: A data processor system is described comprising a first and a second data processor unit (PU1, PU2). The first data processor unit (PU1) has a data source (SW1, IP11, IP 12) for providing data units for transmission to the second data processor unit (PU2) and a retry buffer (RBUF) for temporarily storing transmitted data units. It is provided with a data selector (RSEL) for selecting data units from the data source or from the retry buffer, and a controller (RCTRL) for controlling the data selector, as well as an output (T1x) for providing data selected for transmissions. The second data processor unit (PU2) has an input (R1x) for receiving the transmitted data and an output (PU20) for further transmitting the received data to a third data processor unit. It also has an input buffer (IBUF) coupled to the input, for temporarily storing the received data.

Abstract: A method and device for data processing having at least three identical or similar execution units, wherein at least one comparator exists and at least two execution units are grouped such that the output signals of the at least two execution units are connected with the at least one comparator and compared.

Abstract: A system and method for performing dynamic request routing based on broadcast source request information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.

Abstract: A system and method are provided for implementing a two-tier full-graph interconnect architecture. In order to implement a two-tier full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the two-tier full-graph interconnect architecture. Data is then transmitted from one processor to another within the two-tier full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor chip identifier associated with a target processor to which the data is to be transmitted.

Abstract: A system and method for performing dynamic request routing based on broadcast depth queue information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide queue depth information to each of the other processor chips in the system. The queue depth information identifies a number of requests or amount of data in each of the queues of a processor chip that originated the heartbeat signal. The queue depth information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.

Abstract: An interface to on-chip memory is described, which provides for using on-chip memory by a RISC superscalar processor, enhanced with methods which execute vector operations by treating the vectors as “streams”, which are fed through one or two function units in a pipelined manner. The interface provides concurrent multiple streams, while at the same time serving “conventional” requests from the host RISC superscalar processor.

Abstract: Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of each 8-bit barrier read register contained in the processors, and a 1-bit barrier write register of another processor is connected, via a wiring block, to a second bit of each 8-bit barrier read register contained in the processors. For example, a processor writes information to its own barrier write register, thereby notifying synchronization stand-by to the other processors and reads its own barrier read register, thereby recognizing whether the other processors are in synchronization stand-by or not. Therefore, a special dedicated instruction is not required along barrier synchronization processing, and the processing can be made at a high speed.

Abstract: A computing architecture comprises a plurality of processing elements to perform data processing calculations, a plurality of memory elements to store the data processing results, and a reconfigurable interconnect network to couple the processing elements to the memory elements. The reconfigurable interconnect network includes a switching element, a control element, a plurality of processor interface units, a plurality of memory interface units, and a plurality of application control units. In various embodiments, the processing elements and the interconnect network may be implemented in a field-programmable gate array.

Abstract: A dynamic reconfigurable circuit including a plurality of processing elements each provided with an arithmetic data input port, a configuration data input port and an output port, a data network that is coupled to the arithmetic data input ports and the output ports of the plurality of processing elements, a configuration memory that is coupled via a configuration path to the configuration data input port of a first processor element being at least one of the plurality of processing elements, and an immediate value network that is independent from the data network and that is coupled to the configuration data input port of a second processor element being at least one of the plurality of processing elements. An internal register of a third processor element is coupled to the immediate value network so that data stored in the internal register can be outputted to the immediate value network.

Abstract: Data transmission efficiency for structured data can be improved by representing structured data using immutable blocks. The contents of the immutable blocks can include data and/or pointers to immutable blocks. An immutable data block cannot be altered after creation of the block. When data represented as immutable blocks is transmitted from one processor to another processor, the transmitter sends block contents for blocks that have not previously been defined at the receiver, and sends block IDs (as opposed to block contents) for blocks that have previously been defined at the receiver. The systematic use of block IDs instead of block contents in transmission where possible can significantly reduce transmission bandwidth requirements.

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract: An exemplary computer monitoring system includes a central processing unit (CPU) connected to a computer, a first microprocessor, a second microprocessor, and a select switch connected to a terminal device. The CPU is connected to the select switch via the first microprocessor and the second microprocessor respectively for transmitting data. When one of the first and second microprocessors is halted, the other one of the first and second microprocessors is selected by the select switch under the control of the CPU. The CPU sends a reset signal to the halted microprocessor to reset it. A monitoring method using the computer monitoring system for improving stability and reliability of the computer monitoring system is disclosed.

Abstract: An atomic compare and swap operation that can be implemented in processor system having first and second processors that have different sized memory transfer capabilities. The first processor notifies the second processor to perform a compare and swap operation on an address in main memory. The address has a size less than or equal to a maximum memory transfer size for the second processor and greater than a maximum memory transfer size for the first processor. The second processor atomically performs the compare and swap operation and notifies the first processor of the success or failure of the compare and swap operation.

Abstract: Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system units as domains and clusters of domains which have both software and hardware isolation from each other. Clusters can share dynamically definable ranges of memory with each other. The domain filter has software-loadable registers on the system units and in the global routers to set the parameters of the domains and clusters. The registers label individual inter-system transactions on the routers as invalid for system units not in the same domain or cluster as the originating unit.