Abstract: A processor is provided with a datapath and control logic, where the datapath and/or the control logic are constituted with basis execution blocks (BEB). Each BEB includes an addressable storage and an arithmetic logic unit (ALU) selectably coupled to each other in a manner that allows instruction execution and/or control decisions to be effectuated through storage read/write operations against the addressable storage and ALU operations performed by the ALU. In one embodiment, the addressable storage of each BEB is a cache memory. In another embodiment, the read, write and ALU operations are hierarchically organized.

Abstract: A controller for executing instructions has one the order of five addressing modes and can allow executing of processes concurrently in multiple modes. A specific embodiment can effectively run legacy code written for the Z80 micoprocessor without requiring recompiling of code. An optional embodiment includes autonomous Multiply/Accumulator Engine (MAC) optimized to perform sum-of-products (SOP) operations with little controller overhead, making the invention capable of more effectively handling a number of processing tasks, particularly tasks related to digital signal processing (DSP).

Abstract: A method and circuit for digital signal processing. The disclosed method and circuit uses a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory. The beginning and ending of instructions may occur across memory word boundaries. Instructions may contain variable numbers of instruction fragments that cause a particular operation to be performed. The disclosed circuit has a set of three data buses over which data may be exchanged with a register bank and three data memories. Data buses include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Additionally, the disclosed circuit has a register bank that is accessible by at least two processing units. The disclosed circuit further includes an instruction fetch unit that receives instructions of variable length stored in an instruction memory.

Abstract: A system, such as an AMBA based system, wherein an interrupt controller is coupled directly to a processor, thereby providing that the processor can access the interrupt controller without having to access a system bus. Specifically, the interrupt controller may be coupled to a port of the processor, such as a tightly coupled memory (TCM) port or a coprocessor port of the processor. The interrupt controller may be coupled to the TCM port along with SRAM.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus. In response to the active signal on the address increment disable line, the bus master inhibits changing the address for the duration of the data transfer. The module also drives an active signal on an expansion address off boundary line in the control bus when an internal expansion address of the module is not aligned with a natural boundary of a data bus of the internal communication bus to allow the bus master to adjust the width of the data transfer.

Abstract: A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.

Abstract: A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. The instructions may contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. The DSP includes multiple data buses, and in particular three data buses. The DSP may also use a register bank that has registers accessible by at least two processing units, allowing multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. an instruction fetch unit that receives instructions of variable length stored in an instruction memory. An instruction memory may advantageously be separate from the three data memories.

Abstract: The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories.

Abstract: A graphics processor includes a plurality of interrelated functional modules and at least one register associated with each of the functional modules. The plurality of interrelated functional modules are interconnected by a data pipeline for conveying data, and each register is configured to control a function of its associated functional module. The graphics processor also includes a control bus interconnecting each of the registers for conveying instructions, and an instruction controller for decoding instructions for use with the graphics processor. The control bus and the data pipeline are physically separate, and the instruction controller includes a register setting unit adapted to set the registers via the control bus in accordance with a decoded instruction. This enables the function of each of the functional modules to be configured in response to each instruction.

Abstract: A master processor, such as a processor embedded in a network interface card, is coupled to a memory via a memory data bus. The master processor generates addresses for the memory and controls the reading and writing of the memory at addressed locations. A slave processor, such as an optional encryption engine, has a data input/output bus connected to the memory data bus. The master processor also controls the reading and writing of data to/from the slave processor via the memory data bus. The master processor effects data transfers from the memory to the slave processor over the data bus by generating a series of memory addresses to read the data from the memory onto the data bus. As each data word appears on the data bus, it is written into the slave processor.

Abstract: A memory device includes an address pipeline configured to receive a write address at a first time and to provide the write address to a memory array at a second time, corresponding to a time when write data associated with the write address is available to be written to the array. The address pipeline may include a series of registers arranged to receive the write address and to provide the write address to the memory array. In addition, the memory device may include a comparator coupled to the address pipeline. The comparator is configured to compare the write address to another address (e.g., a read address) received at the memory device. A bypass path to the array may be provided for read addresses received at the memory device. A data pipeline is configured to receive data destined for the memory device and to provide the data to the memory array. The data pipeline may include a data bypass path which does not include the memory array.

Abstract: An apparatus for and method of reducing the power consumed by a microprocessor core are disclosed. The apparatus and method reduce power by not loading operands into the core's data-path when they are already there. The apparatus has a core circuit for implementing a microprocessor core, the core circuit including at least one data bus, a plurality of operand storage circuits, at least one operating circuit, and a control circuit. The data buses are configured to transmit a plurality of operands. The operand storage circuits are connected to the data buses, are configured to receive a plurality of load commands and in accordance therewith to load the operands, and are configured to output the operands. The operating circuits are connected to the operand storage circuits and are configured to receive the operands and in accordance therewith to generate a result signal.

Abstract: An arbitrator provided to a processor element requests the utilization of a bus sends a bus request signal and a bus request value according to a priority level of the processor element to the bus, determines the priority of utilizing the bus in accordance with utilizing situation of the bus and the priority level of the processor element. Since a common bus arbitrating circuit connected to the bus watches the bus and determines a processor element to utilize the bus according to the utilizing situation of the bus and the priority level of the processor elements requesting the utilization of the bus, the bus arbitration can be performed with high speed, and an increase of communication speed between the processor elements through a single bus can be realized.

Abstract: A microcomputer for feeding source data necessary for operations without any delay while retaining the consistency on instruction lines between the ordinary single operations and the SIMD (Single Instruction Multiple Data) type parallel operations. The microcomputer comprises: a first memory and a second memory adapted to be individually fed with a common address from the address generating unit; a first execution unit coupled to the first memory and the second memory; and a second execution unit coupled to the first memory and the second memory. The second execution unit is mounted together with the central processing unit, the first memory, the second memory and the first execution unit on a common semiconductor substrate.

Abstract: An apparatus and method for improving processor performance during multithreaded processing based on the use of a banked shadowed register file for minimizing thread switch overhead.

Abstract: The present invention provides an audio signal processor and method of operation thereof that enables efficient digital signal processing. Fast multiply-accumulate (MAC) and vector processing capabilities are implemented in a RISC architecture giving the high speed capabilities of a digital signal processing system the speed and efficiency of a RISC processor.

Abstract: Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions of a typical computer program do not require reading operands from the memory, the probability is high that at least one of any three program instructions to be executed at the same time need not fetch an operand from memory. The two memory ports are thus connected at any given time with the two of the three pipelines which are processing instructions that require memory access, the pipeline without access to the memory processing an instruction that does not need it. To do so, the added third pipeline need not have all the same resources as the other two pipelines, so its stages are made to have a reduced capability in order to save space and reduce power consumption.

Abstract: The invention relates to a microprocessor having a plurality of components which are selected from registers (14, 16), arithmetic logic units (30, 32), memory (36, 38), input/output circuits and other similar components where the plurality of components are interconnected in a manner which allows connection between some of the components to be varied under program control.

Abstract: Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions of a typical computer program do not require reading operands from the memory, the probability is high that at least one of any three program instructions to be executed at the same time need not fetch an operand from memory. The two memory ports are thus connected at any given time with the two of the three pipelines which are processing instructions that require memory access, the pipeline without access to the memory processing an instruction that does not need it. To do so, the added third pipeline need not have all the same resources as the other two pipelines, so its stages are made to have a reduced capability in order to save space and reduce power consumption.

Abstract: For use in a processor having a result bus of insufficient width to convey all results of a given multiple-result instruction concurrently, a system for, and method of, writing back the results of the multiple-result instruction. In one embodiment, the system includes: (1) multi-result node creation circuitry that creates a multi-result node having at least first and second results for the multiple-result instruction and (2) node transmission circuitry, coupled to the multi-result node creation circuitry, that transmits the first and second results of said multi-result node sequentially over the result bus.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: In a multiprocessor system including numbers of processors which realizes hierarchical interprocessor communication and enables high-speed interprocessor communication, each processing element is composed of a plurality of processors physically sharing the same register file, and in the processing element, interprocessor communication is conducted by sharing the register. Every several processing elements are connected to the same local bus and the local buses are connected to each other by a bridge and a global bus. Between processing elements located at a short distance from each other, communication is conducted through one local bus, while between processing elements located at a long distance from each other, communication is conducted through a plurality of local buses and global buses.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: A single chip microcomputer comprises a central processing unit (CPU) 2, a on-chip RAM 3, a on-chip ROM 5, a first bus DBUS for connecting the CPU, RAM, and ROM with one another and transferring data between them, a second bus ABUS for passing address data corresponding to the data passed through the first bus, a third bus SDBUS for connecting the CPU 2 with the RAM 3 and transferring data between them, the number of bits of the third bus SDBUS being larger than that of the first bus DBUS, and a fourth bus BABUS for connecting the CPU 2 with the RAM 3 and passing address data corresponding to the data passed through the third bus SDBUS. The CPU 2 has a data memory RF serving as general purpose registers for providing internal data to the third bus SDBUS, and a bank specifying register BP for holding positional data of a mapping region in the RAM 3 where the contents of the data memory RF are mapped and providing the positional data to the fourth bus BABUS.

Abstract: A 32-bit RISC processor is disclosed. The bit length of the instruction set is fixed to 16 bits. SLIL and SLIH instructions that cause the address space of 4 Gbytes to be limited to upper 2 Mbytes and that execute a long type register branch instruction are provided. Thus, a register branch instruction can be executed with three instructions rather than five instructions unlike with a related art reference.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A data processor including: a CPU (1) for performing a wait operation upon input of a wait signal (10) to its wait terminal (9); a wait/wait cancel instruction setting register (11) to which the CPU (1) sets a wait instruction and a wait cancel instruction; and a wait controller (12) for outputting a wait signal to the wait terminal (9) of the CPU (1) in accordance with the setting of the register (11), wherein the inventive data processor allows a wait state to be set and canceled as programmed independently of address space constraints.

Abstract: A branch instruction format has different respective field lengths for conditional branch instructions and unconditional branch instructions. A conditional branch instruction has a first bit length and a first area for a displacement designating an address to be jumped, wherein the first area has a second bit length that is smaller than the first bit length. An unconditional branch instruction also has the first bit length, and a second area for a displacement designating an address to be jumped, wherein the second area has a third bit length that is different from the first and second bit lengths.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: Disclosed is a method and apparatus for accessing data in a computer system after a failed data operation in which I/O process state information is unknown. The failed data operation may cause data inconsistency among multiple devices associated with a shadow set for storing data. The disclosed system includes techniques for allowing continued data accesses while simultaneously re-establishing data consistency among members of the shadow set.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when additional time is needed to participate in the data transfer. If either the source module, destination module or both modules require more time, the bus master, in response to an active stretch bus access signal or signals for the module or modules, automatically extends the bus access cycle until all modules requiring additional time signal over the internal communication bus that they are ready to proceed with the data transfer. Consequently, the source module, destination module, or both modules can re-time a bus access cycle to accommodate the characteristics of that particular module. When the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus.

Abstract: A first memory of a large storage capacity is connected to a DQ pad for inputting and outputting an information signal through a bus interface unit. A first bidirectional transfer circuit and a second bidirectional transfer circuit for bidirectionally transmitting an information signal are provided between a high-speed memory and the memory of the large storage capacity. The first bidirectional transfer circuit is connected with the large storage capacity memory through a common bus, and the high-speed memory is interconnected with the second transfer circuit through a fifth bus. This second bidirectional transfer circuit is connected to an instruction register and a data register through a sixth bus. A processor is arranged in proximity to this instruction register and the data register, so that the processor processes an instruction from the instruction register and data from the data register and stores a processing result in the data register again.

Abstract: The present invention discloses a system and method for compressing data transmitted over a bus between a bus device, such as a CPU or an I/O device, and a memory subsystem. The data is compressed into data tokens and the tokens are stored in and retrieved from the memory subsystem. The CPU may also contain a token-generating circuit. Content addressable memory is employed to compare the data against expected bit patterns for generating the data tokens. Upon encountering a match, the content addressable memory returns the data token associated with the matching bit pattern. Both the bus device and memory subsystem may have the capability to compress data into tokens and re-expand data when necessary. A method is also employed for indicating to a device receiving data whether the data is a token or not.

Abstract: A protocol and internal link system of a micro-controller in which components, interconnected by a parallel BUS link, exchange during a transaction successive messages on a plurality of clock cycles. A master transmitting component transmits, on a current clock cycle, to an addressee slave receiver component, an instruction message, encoded on N+p bits, and comprising a main field, N bits, and an auxiliary field, p bits, comprising an operation code, a signature identifying master and slave component and their transaction. A proof of transmission message and an acknowledgement message are transmitted from the master component to the slave component and vice versa on the following clock cycle. These steps are repeated on at least one subsequent clock cycle.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: An application-specific single chip digital processor having flexible design expansion capability with minimal impact on the performance of a processor core. The processor core has an ALU and a register file (accumulators). The output of the ALU is connected to a multiplexer whose output is connected to the input of the register file. The output of the register file connects to one input of the ALU. A function unit, separate from the core, has an input connected to the output of the register file and an output connected to another input to the multiplexer. The core operates with a predefined instruction set. The function unit, which may be redesigned depending on the application, operates with a reserved (uncommitted) instruction set under control of the core.

Abstract: A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as a slave processor in the aforementioned master/slave multi-processor computer system the slave processor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is in effect native to the slave processor.

Abstract: A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Similarly a type of peripheral bus used can be changed simply by replacing the printed circuit board containing the peripheral controller. High-density connectors connect the circuit boards. Some embodiments of the invention use a single backplane. Other embodiments place peripheral slots on a second, passive backplane.

Abstract: A counterflow pipeline is provided which includes an instruction pipeline having a plurality of stages for transmitting instruction packets in a first direction and a result pipeline having a plurality of stages for transmitting result packets in a second direction opposite the first direction. Each of the result pipeline stages corresponds to an instruction pipeline stage, the associated instruction and result pipeline stages being part of a counterflow pipeline stage. Arbitration logic coupled between the instruction and result pipelines facilitates the movement of instruction and result packets in the stages of the instruction pipeline and result pipeline, respectively, using a four-phase level signaling protocol. The arbitration logic prevents instruction and result packets from passing each other in their respective pipelines by inhibiting them from being simultaneously released from adjacent counterflow pipeline stages. Thus, any necessary interaction between the two data packets may take place.

Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.

Abstract: A processor having a pipelining structure, in particular with a superscalar architecture, includes a configurable logic unit, an instruction memory, a decoder unit, an interface device, a programmable structure buffer, an integer/address instruction buffer and a multiplex-controlled s-paradigm unit linking contents of an integer register file to a functional unit with programmable structures and having a large number of data links connected by multiplexers. The s-paradigm unit has a programmable hardware structure for dynamic reconfiguration/programming while the program is running.

Abstract: A memory request protocol allows a memory request to be withdrawn or "cancelled" without penalty so no memory resource is wasted in doing so during an assigned "cancel window". When the memory card starts to process a command from the memory controller, for a predefined number of cycles a period of time is available where the memory card can't accept another command due to a resource conflict. This provides an opportunity to re-balance requests to the memory controller in this period of time or "cancel window".

Abstract: An object is to compatibly improve processing speed and storage capacity of semiconductor memory that the operation portion can use. Each of units (10a, 10b) each having an operation portion (11) and a memory portion (12) is formed of a single semiconductor chip. A data signal is separately stored in the two memory portions (12) in a bit-sliced form and each of the two operation portions (11) can use the 32-bit-wide data signal stored in the entirety of the two memory portions (12) through interconnections (22, 23). That is to say, each operation portion (11) can use a storage capacity twice larger than the capacity that can be ensured in a single semiconductor chip. Provided as interconnections for coupling the semiconductor chips are only the interconnections (22, 23) for transferring data signals from the two memory portions to the two operation portions (11).

Abstract: A bus switch providing versatile data path routing between a first group of busses associated with a disk array controller and a second group of busses associated with the individual disk drives within the disk array. The bus switch comprises a plurality of bus multiplexers, equal in number to the number of drive busses. Each bus multiplexer includes a plurality of inputs, each input being connected to a corresponding one of the controller busses. The multiplexers are responsive to select and enable signals to connect selected controller busses to selected drive busses. The bus switch additionally includes a plurality of bus multiplexers for directing data from the drive busses to the controller busses. A parity generator comprising an exclusive-OR circuit is integrated with the bus switch. The output of the parity generator is also provided to each of the multiplexers and can be directed thereby to any of the controller or drive busses.

Abstract: To improve the efficiency of delayed transactions in bus-to-bus bridge systems which include at least one interface to a PCI bus, a bridge system is disclosed including at least a primary interface and an interface to a secondary subsystem for interconnecting a primary PCI bus system and the secondary subsystem. The system comprises a delayed transaction mechanism for enabling a transaction source attached to the primary PCI bus system to effect delayed transactions with a target in the secondary subsystem. This system has a programmable delay transaction timer which provides a degree of flexibility in the configuration of PCI systems. This flexibility can be exploited to provide considerable efficiency gains, albeit at the expense of some deviation of the strict requirements of the PCI Specification.

Abstract: A special purpose reduced instruction set central processing unit (RISC CPU) for controlling digital audio/video decoding. The instruction set includes flow control instructions which incorporate immediate values, used to jump over a small number of instructions, and other instructions used for larger jumps. Also, instructions obtain data from the video decoder of the ASIC in a streamlined fashion, using video decoder addresses hard-coded into the RISC CPU. Further instructions perform manipulations of individual bits of registers used as state/status flags. The RISC CPU includes watchdog functions for monitoring the delivery of data to the RISC CPU from other functional units or from memory, so that the RISC CPU can execute instructions while delivery of data from memory or other functional units is pending, unless that data is necessary for program execution, in which case, program execution stalls until the data arrives.

Abstract: A transmit scheduler and method of operation are provided for an asynchronous transfer mode network. The transmit scheduler is operable to write data to and read data from a scheduler table and a virtual channel identifier ("VCI") table in order to schedule cells for virtual channels. The transmit scheduler calculates a location in the scheduler table in which to schedule a cell for a current virtual channel and determines whether a cell for a prior virtual channel is scheduled in the calculated location in the scheduler table. The transmit scheduler then schedules the cell for the current virtual channel at the calculated location in the scheduler table. If a cell for a prior virtual channel was scheduled in the calculated location in the scheduler table, the transmit scheduler writes a pointer into a next pointer field of a record for the current virtual channel in the VCI table, where the pointer provides a link to a record for the prior virtual channel in the VCI table.

Abstract: A processor to coprocessor interface supporting multiple coprocessors utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor and coprocessor on a bidirectional shared bus either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.