Abstract: The present invention relates to a register file in a microprocessor and operating system thereof for performing a data transfer between register cells within a register file. The register file has a plurality of register cells and an internal common bus that can directly transfer data between register cells by binding together control units for feedback transmission in each register cell to perform a direct data transfer between register cells. Each of the registers cell includes a repeater cell, a data input control unit, a data transfer control unit and a feedback transmission control unit.

Abstract: A computer system comprising a microprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network port data and instruction cache and I/O interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes.

Abstract: A buffer circuit of a decentralized peripheral module. The buffer circuit has three input and three output signal storage areas, which can be selectively connected to a bus interface or a module interface via a selection circuit. Thus the process signal transfer from an intelligent unit arranged on the module to a unit of a higher level than the module and vice-versa can be completely separated.