Abstract: An integrated touchscreen can include light emitting diodes or organic light emitting diodes (LEDs/OLEDs), display chiplets and touch chiplets disposed in a visible area of the integrated touch screen. For example, the LEDs/OLEDs, display chiplets and touch chiplets can be placed on a substrate by a micro-transfer tool. The integrated touchscreen can also include electrodes disposed in the visible area of the integrated touch screen. The electrodes can be capable of providing display functionality via the one or more display chiplets during display operation (e.g., operating as cathode terminals of the LEDs during the display operation) and capable of providing touch functionality via the touch chiplets during touch operation (e.g., touch node electrodes can be formed from groups of the electrodes and sensed). In some examples, the touch node electrodes can be formed and coupled to touch chiplets via the display chiplets.

Abstract: Systems and methods for executing compiled code having parallel code fragments is provided. One method includes storing executable code having a plurality of parallel code fragments, each of the plurality of parallel code fragments representing alternative executable paths through a code stream. The method further includes determining a code level supported by a processor executable at a computing system, the processor executable supporting a hosted computing environment. The method also includes translating the executable code into machine-readable code executable by a processor of the computing system. Translating the executable code includes selecting a code fragment from among the plurality of parallel code fragments for execution based on the code level supported by the processor executable. The method includes executing the machine-readable code within the hosted computing environment.

Abstract: Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.

Abstract: Embodiments are described for recovery, via a sideband management bus, of firmware of a device such as an FPGA (Field Programmable Gate Array) card installed within an IHS (Information Handling System). A remote access controller of the IHS generates a security key for the device and transmits it to the device. The remote access controller requests the device to report the current version of the firmware in use by the device. The response from the device is authenticated based on the security key. If the current firmware version reported by the device is consistent with the master firmware version, the device is halted and the current firmware of the device is replaced with the master firmware. The device is initialized based on the master firmware used to update the device firmware.

Abstract: The data storage method includes selecting one of a plurality of blocks in a flash memory as an active block; dividing the active block into a plurality of virtual blocks; selecting and accessing one of the virtual blocks; and maintaining a mapping table corresponding to the selected virtual block. The mapping table records mapping information between a plurality of logical addresses and a plurality of physical addresses of the selected virtual block.

Abstract: The present invention is directed to a memory array including one or more memory layers, each of which includes a first plurality of memory cells and a second plurality of memory cells arranged in alternated odd and even columns, respectively; multiple odd horizontal lines with each connected to a respective odd column of the first plurality of memory cells; multiple even horizontal lines with each connected to a respective even column of the second plurality of memory cells; multiple transverse lines with each connected to one of the first plurality of memory cells and a respective one of the second plurality of memory cells disposed adjacent thereto along a row direction; and multiple vertical lines with each connected to a respective one of the multiple transverse lines. The odd horizontal lines collectively form fingers of a first comb structure and the even horizontal lines collectively form fingers of a second comb structure.

Abstract: An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.

Abstract: An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

Abstract: An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a respective region of a first portion of the programmable logic regions, and each of the first portion of the plurality of regions transmits configuration data to a first set of adjacent regions of the first portion of regions. The integrated circuit may also include a second plurality of routers, and each of the second plurality of routers is coupled to a respective region of a second portion of the regions. Each of the second portion of the regions transmits the configuration data to a second set of adjacent regions of the first portion of regions. The integrated circuit may also include a voltage regulator that distributes a voltage to each of the regions.

Abstract: A field device for determining or monitoring a physical or chemical, process variable, comprising: a sensor, which works according to a defined measuring principle; and a control/evaluation unit. The control/evaluation unit is realized on a partially dynamically reconfigurable FPGA component, which is constructed from a plurality of FPGA blocks units. Each FPGA block unit comprises a plurality of logic blocks. Global resources or global function blocks are associated with each FPGA block unit or groups of FPGA block units. At least a first section and a second section are provided on the FPGA-component. The sections comprise FPGA block units and corresponding global resources global function blocks. In each section a digital measuring path comprising a plurality of software based and/or hardware based, function modules, is partially dynamically reconfigurable.

Abstract: Provided is a data processing apparatus including a reconfigurable circuit that has a dynamically-reconfigurable circuit configuration to execute data processing with the reconfigured circuit configuration, a loading processor that loads reconfiguration data to a reconfiguration memory based on set loading information, a reconfiguration processor that reconfigures the circuit configuration with the reconfiguration data loaded to the reconfiguration memory in response to a request from the reconfigurable circuit, and a controller that executes a process of setting the loading information with respect to the loading processor while inhibiting the reconfiguration by invalidating the request, and validates the request after terminating the setting process to permit the reconfiguration.

Abstract: Techniques are described for efficient reordering of data and performing data exchanges within a register file or memory, or in general, any device storing data that is accessible through a set of addressable locations. An address translator is placed in the path of all or a selected set of address busses to a storage device to provide a programmable and selectable means of translating the storage device addresses. An effect of this translation is that the data stored in one pattern may be accessed and stored in another pattern or accessed, processed and stored in another pattern. The address translation operation may be carried out in a single cycle, does not involve the physical movement of data in swap operations, allows data to effectively be ordered more efficiently for algorithmic processing and therefore saves power.

Abstract: Application code is analyzed to determine if a hardware library could accelerate its execution. In particular, application code can be analyzed to identify calls to application programming interfaces (APIs) or other functions that have a hardware library implementation. The code can be analyzed to identify the frequency of such calls. Information from the hardware library can indicate characteristics of the library, such as its size, power consumption and FPGA resource usage. Information about the execution pattern of the application code also can be useful. This information, along with information about other concurrent processes using the FPGA resources, can be used to select a hardware library to implement functions called in the application code.

Abstract: A consumer system receives capabilities metadata from a producer system that includes resource class metrics for a resource class included in the producer system. Next, the consumer system creates a rule that corresponds to one of the consumer system's managed entities. The rule includes one or more prescriptions that reference the resource class metrics and specify a periodicity, which informs the producer system as to a time interval for which to send prescription results that includes metric information pertaining to the resource class metrics. The consumer system sends the rule to the producer system and, in turn, the consumer system receives the prescription results from the producer system at the specified periodicity and applies the metric information to the managed entity.

Abstract: A method of an aspect, which may be performed responsive to one or more structure access instructions, includes changing a state of a portion of a structure of a processor to a sequestered state. In the sequestered state, components of the processor are not able to access the portion of the structure but are able to access one or more other portions of the structure. Non-architecturally visible data in the portion of the structure is modified, while the portion of the structure is in the sequestered state. The state of the portion of the structure is then changed from the sequestered state to a non-sequestered state, after the non-architecturally visible data in the portion of the structure has been modified. Other methods, apparatus, systems, and instructions are also disclosed.

Abstract: A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity.

Abstract: A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data.

Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.

Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.

Abstract: A method and apparatus for updating firmware of terminals in a mobile broadcast system including a Broadcast Service Distribution/Adaptation fragment (BSDA) and a Broadcast service Subscription Management (BSM). The method includes requesting creation of a content fragment, by the BSM, by transmitting a firmware package file for a firmware update of the terminals to the BSDA; creating a content fragment including the firmware package file and broadcasting the created content fragment to the terminals by the BSDA; detecting the firmware package file from the received content fragment; and performing the firmware update using the firmware package file.

Abstract: In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks. The resulting combination allows for data packets to undergo a processing sequence having the flexibility of software programmability with the high-performance of dedicated hardware. For example, a multi-threaded processor can control the high-level tasks of a processing sequence, while the computationally intensive events (e.g., signal processing filters, matrix operations, etc.) are handled by dedicated hardware blocks.

Abstract: A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.

Abstract: Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory including configuration information about an operation of a function unit, and a distributed routing configuration memory including configuration information about routing. The distributed operation configuration memory may be activated according to a predicate signal.

Abstract: A computer system employs a network that between a data programming system and one or more superconducting programmable devices of a superconducting processor chip. Routers on the network, such as first-, second- and third-stage routers direct communications with the superconducting programmable devices. A superconducting memory register may load data signals received from a first-stage router into corresponding superconducting programmable devices. The system may employ additional superconducting chips, first-, second- or third-stage routers.

Abstract: The multi-cycle programmable processor emulates the features of a conventional microprocessor. Processor hardware functional units include a program counter (instruction pointer), an arithmetic and logic unit, an accumulator, an instruction register, a 2×1 multiplexer, 2×4 decoder, 1×2 decoder, an AND gate and an OR gate. Additionally, a controller modeled by a finite state machine (FSM) is operably connected to the microprocessor functional units and has a plurality of states that defines the operation of the microprocessor functional units. Each control state of the FSM implements the transfer of information between the registers of the datapath. The execution sequences through three states: an instruction fetch; an instruction decode; and instruction execute. The controller issues the required signals to the various hardware components to execute the instruction needed in three clock cycles.

Abstract: A method may include recognizing, by a PEP, a connection failure to a PDP, establishing a reconnection, initiating, by the PEP, a fast state synchronization based on a client-open message of the common open policy service for policy provisioning (COPS-PR) protocol, receiving, by the PEP, an acceptance for the fast state synchronization based on a null decision message of the COPS-PR protocol, and transmitting, by the PEP, differential state information to the PDP.

Abstract: An image forming apparatus includes: plural processing units which execute plural processing functions that are different from each other; an execution-in-progress information acquiring unit which acquires execution-in-progress function information that is information about a first processing unit which is executing processing, of the plural processing units; a discrimination unit which discriminates a second processing unit that cannot execute processing when the first processing unit indicated by the execution-in-progress function information acquired by the execution-in-progress information acquiring unit is executing processing, from among the plural processing units; and an executability information generating unit which generates inexecutable function information that is information about the second processing unit, based on a result of determination by the discrimination unit.

Abstract: A programmable filter processor which is adaptable to different filtering algorithms, a plurality of different software algorithms being executable, the programmable filter processor including a logic unit which includes a plurality of pipeline stages; a first memory in which the software algorithms are stored; a second memory in which raw data and parameters for the different filter algorithms are stored; and an address generating unit which is controllable via a program counter, the address generating unit being developed to generate control commands for the second memory and the logic unit.

Abstract: A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

Abstract: A reconfigurable FADEC includes a reconfigurable CPU configured for performing digital computing functions. A reconfigurable MSPD communicates with the CPU and is configured for performing analog I/O functions. A data bus is coupled to the CPU and the MSPD. The data bus is configured for connecting the CPU and the MSPD to an external connector.

Abstract: An integrated circuit can include a processor system configured to execute program code. The processor system can be hard-wired and include a processor hardware resource. The IC also can include a programmable circuitry configurable to implement different physical circuits. The programmable circuitry can be coupled to the processor system. The programmable circuitry can be configurable to share usage of the processor hardware resource of the processor system. The processor system further can control aspects of the programmable circuitry such as power on and/or off and also configuration of the programmable circuitry to implement one or more different physical circuits therein.

Abstract: An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus.

Abstract: A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.

Abstract: A method of extending a processor system within an integrated circuit (IC) can include executing program code within the processor system implemented within the IC, wherein the IC includes a programmable fabric. The processor system further can be coupled to the programmable fabric. A process can be performed using a process-specific circuit implemented within the programmable fabric in lieu of using the processor system. A result of the process from the process-specific circuit can be made available to the processor system.

Abstract: A method for configuring programmable logic in an IC to implement instances of a relocatable circuit includes, for each instance, assigning a respective portion of an address space of a processor to the instance, configuring a respective interface circuit for translating the transactions accessing the respective portion of the address space into a fixed address space of the relocatable circuit, and selecting a respective region within an array of programmable logic and interconnect resources of the IC. The processor accesses the address space with read and write transactions issued on an interface bus. The relocatable circuit is independent of the address space assigned to the instances. Each region is configurable to implement an instance. The programmable logic and interconnect resources are configured to implement the instances and to couple each instance to the interface bus of the processor via the respective interface circuit, using a single copy of configuration data for the relocatable circuit.

Abstract: An image processing apparatus which applies processes to input image data is disclosed. The image processing apparatus includes a first processing section which applies processes to the image data by a specific calculating device, and a second processing section which applies processes to the image data by a general-purpose calculating program. The input image data are multilevel image data. The first processing section includes an image data binarizing unit for forming binary image data from the multilevel image data, and a multilevel image data processing section for applying a calculation process to the multilevel image data. The second processing section includes a binary image data processing section for applying a calculation process to the binary image data formed by the image data binarizing unit.

Abstract: A central processing unit (processor) having multiple cores and a method for controlling the performance of the processor. The processor includes a first storage location configured to store a first threshold associated with a first boost performance state (P-State). The processor also includes logic circuitry configured to increase performance of active processor cores when an inactive processor core count meets or exceeds the first threshold. The processor may also include a second storage location configured to store a second threshold associated with a second boost P-State. The logic circuitry may be configured to compare the inactive processor core count to the first and second thresholds, select one of the first and second boost P-States and increase performance of active processor cores based on the selected boost P-State.

Abstract: A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The co-processor further comprises a common infrastructure that is common across all of the different personalities, such as an instruction decode infrastructure, memory management infrastructure, system interface infrastructure, and/or scalar processing unit (that has a base set of instructions). Thus, the personality of the co-processor can be dynamically modified (by reconfiguring one or more application engines of the co-processor), while the common infrastructure of the co-processor remains consistent across the various personalities.

Abstract: The multi-cycle programmable processor emulates the features of a conventional microprocessor. Processor hardware functional units include a program counter (instruction pointer), an arithmetic and logic unit, an accumulator, an instruction register, a 2×1 multiplexer, 2×4 decoder, 1×2 decoder, an AND gate and an OR gate. Additionally, a controller modeled by a finite state machine (FSM) is operably connected to the microprocessor functional units and has a plurality of states that defines the operation of the microprocessor functional units. Each control state of the FSM implements the transfer of information between the registers of the datapath. The execution sequences through three states: an instruction fetch; an instruction decode; and instruction execute. The controller issues the required signals to the various hardware components to execute the instruction needed in three clock cycles.

Abstract: Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.

Abstract: Logic circuits of a digital device may be biased to operate over specific external clock frequency ranges by programming a desired clock oscillator frequency range into a configuration memory of the digital device. In addition, clock source selection may also be programmed into the configuration register. Bias circuits are then configured so that the internal logic of the digital device will operate over the desired clock oscillator frequency range. Non-volatile memory may be used to store the contents of the configuration memory so as to retain the configuration during power down of the digital device. The non-volatile memory may be programmable fuse links, electrically erasable and programmable memory (EEPROM), FLASH memory, etc.

Abstract: Task definitions are used by a task scheduler and prioritizer to allocate task operation to a plurality of processing units. The task definition is an electronic record that specifies researching needed by, and other characteristics of, a task to be executed. Resources include types of processing nodes desired to execute the task, needed amount or rate of processing cycles, amount of memory capacity, number of registers, input/output ports, buffer sizes, etc. Characteristics of a task include maximum latency tome, frequency of execution of a task, communication ports, and other characteristics. An exemplary task definition language and syntax is described that uses constructs including other of attempted scheduling operations, percentage or amount of resources desired by different operations, handling of multiple executable images or modules, overlays, port aliases and other features.

Abstract: A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, an interface circuit maps virtual addresses from the host system to physical addresses of the DRAM integrated circuits in a linear manner. In a further embodiment, the interface circuit maps one or more banks of virtual addresses from the host system to a single one of the DRAM integrated circuits.

Abstract: An internal buffer is provided for a DRP core. A selector SEL switches input/output destination of the DRP core between external memory and an internal buffer. Control software executed by a CPU core receives information a pipeline of configurations for a sequence of target processing and generates combinations as to whether the processing result is transferred between the configurations via the external memory or via the internal buffer as transfer manners. Next, for each manner, bandwidth and performance of the external memory used by the DRP core in the manner are calculated. The manner of the best performance satisfying a previously specified bandwidth restriction is selected among the manners and the selector SEL is switched in accordance with the manner.

Abstract: An integrated circuit chip having plural processors with a shared field programmable gate array (FPGA) unit, a design structure thereof, and method for allocating the shared FPGA unit. A method includes storing a plurality of data that define a plurality of configurations of a field programmable gate array (FPGA), wherein the FPGA is arranged in the execution pipeline of at least one processor; selecting one of the plurality of data; and programming the FPGA based on the selected one of the plurality of data.

Abstract: A data processing device comprises a state manager for determining a logic number of configurational information to be used in a next state, the logic number representing information on a mutual relationship between items of configurational information included in an object code, based on a present operational state, a group of candidates for a state to transit to next, and an event signal issued from arithmetic units, a configuration number converter for outputting a real number corresponding to the logic number determined by the state manager, the configuration number converter having conversion information for converting the logic number into a real number representing a location where the corresponding configurational information is actually stored, and a configurational information storage for storing the configurational information and indicating configurational information corresponding to the real number output from the configuration number converter, to the arithmetic units and an interconnector.

Abstract: From source code specification of each of a plurality of threads, those variables of a data structure referenced by the thread are determined. For each thread, a respective adaptation of the source code specification of the data structure is generated. Each adaptation includes only variables of the data structure that are referenced in the respective thread. The source code specifications of the threads are compiled into respective object code segments using the respective adaptations of the data structures. Each object code segment requires memory space for the data structure for only those variables included in the respective adaptation. The source code specification of the data structure describes a network packet, and the respective object code segments are configured to operate on the respective portions of the network packet stored in separate memories while executing on respective processors.

Abstract: Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle that instruction. A content addressable memory may be used to determine the execution path when fed the instruction's operational code, or an arbiter and multiplexer may resolve conflicts if multiple instruction decode blocks recognize the same instruction. The execution path may be dynamically reconfigured, activated or deactivated as needed, such as to extend an instruction set, to optimize instructions for a particular application program, to implement a peripheral device, to provide parallel computing, and/or based on power consumption and/or processing power needs. Security may be provided by having the reconfigurable execution path loaded from an extension file that is associated with metadata, including security information.

Abstract: A cell element field for data processing having function cells for execution of algebraic and/or logic functions and memory cells for receiving, storing and/or outputting information is described. A control connection may lead from the function cells to the memory cells.