Abstract: A computing device including a motherboard. The motherboard is coupled to a memory socket, a power rail, and a regulator controller. The memory socket is able to couple to a circuit board that includes memory circuitry. The power rail provides a high-voltage power signal to power circuitry on the circuit board. The power rail provides the high-voltage power signal through the memory socket. The regulator controller provides a control signal to power circuitry on the circuit board. The control signal includes a pulse width modulation signal. An output voltage of the power circuitry on the circuit board may be controlled by the control signal.

Abstract: A wearable device and a method of providing user interaction with the wearable device is provided. The method includes receiving one or more signals from at least one of one or more pressure sensors and one or more vibration sensors, obtaining information related to at least one of an orientation of the wearable device on a user hand and a hand on which the wearable device being worn based on the one or more signals received, and performing one or more functions based on the obtained information.

Abstract: In an example implementation according to aspects of the present disclosure, a method may include receiving, on a touch sensitive mat of a computing system, a touch input associated with a first event type. The method further includes determining whether to transform the touch input associated with the first event type to a different event type, and sending, to an application, the touch input associated with an event type based according to the determination.

Abstract: An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, present invention eliminates a need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing an area and a power consumption of the online monitoring unit significantly and improving an energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, a time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by process-voltage-temperature (PVT) variations, thus enabling a minimization of a timing margin and ensuring a higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.

Abstract: Technology related to activating a peer-to-peer communication channel is disclosed. In one example of the disclosed technology, a method can be used to initiate peer-to-peer communications between a transmitting device and a receiving device over an inactive first communication channel. The method can include determining an address associated with a second communication channel of the receiving device. A packet addressed to the receiving device can be transmitted over the second communication channel to cause the receiving device to begin a sequence to activate the first communication channel. Communication can be initiated over the first communication channel from the transmitting device to the receiving device at a different address associated with the first communication channel.

Abstract: An information storage system and an information storage method allow necessary information to be stored in the proper amount with a simple operation for people to share the information. The system includes an input unit including a plurality of press-type switches each of which accepts input for an on-signal or an off-signal and a data server storing pieces of identification information each identifying a corresponding one of the switches and messages in association with each other and outputs, in response to input accepted by each of the switches, a corresponding one of the messages. The input unit transmits an on-signal or an off-signal and a piece of identification information to the data server. The data server receives the on-signal or the off-signal and the piece of identification information and extracts and outputs a message associated with the piece of identification information received together with the on-signal.

Abstract: Devices, systems and methods are disclosed for readying a device from hibernation with reduced user-perceived latency. For example, data likely to be accessed may be selected as preload data that is loaded into volatile memory prior to the device resuming system interactivity (e.g., being responsive to user input), thus “anticipating” user demand by loading memory pages that the user will likely request. The device may determine additional data to add to the preload data based on processes running on the device and virtual memory areas (VMAs) associated with the processes, may weight the processes and may intelligently determine the data so that the device more rapidly reaches system interactivity.

Abstract: Disclosed are various embodiments for a timeout management application. Latency data for executing services is obtained. The used service capacity is calculated. If the service capacity is outside of a predefined range, the timeout of a selected service is reconfigured.

Abstract: A USB power-delivery device includes a clock signal generator which stops generation of a clock signal for a dual-role port (DRP) while the USB power-delivery device operates in a low power mode until an attach event occurs, and starts the generation of the clock signal for the DRP after the attach event occurs.

Abstract: A motor control device avoids the difficulties associated with safely controlling a motor using a second calculation unit when a first calculation unit malfunctions. A motor control device monitors a malfunction of a first microcomputer and a malfunction of a first CPU of the first microcomputer and performs a determination based on a result of a second external communication functional unit. When the determination is normal, the process proceeds determine that the first CPU is normal and a second CPU malfunctions. Therefore, it is possible to continue processing using the first CPU in this case.

Abstract: A voltage scaling system can scale a supply voltage while preventing processor access of system components that are rendered unstable from the scaling. A processor receives an instruction to scale a system supply voltage to a target supply voltage. The processor executes the instruction and enters into a sleep mode. The processor can send, to a controller that saves power, an indication that the processor is in the sleep mode. When the processor is in the sleep mode, the processor becomes inactive and cannot access any components, e.g., Flash memory data, of the voltage scaling system. The controller can configure a voltage regulator to scale the system supply voltage to the target supply voltage. Once the target supply voltage is reached, the voltage regulator sends an interrupt to the processor, thereby waking up the processor from the sleep mode.

Abstract: It is proposed a method for verifying configuration changes in a Self-Organizing Network comprising a plurality of verification areas, in which each verification areas at least one network element is installed. The method comprises observing 701 a configuration change within a verification area affecting one or more network elements; computing 702 a virtual temperature value for the affected network elements, wherein the virtual temperature value indicates a stability state of the network element; distributing 703 the computed virtual temperature value; receiving 703 the computed virtual temperature value; triggering 704 a verification mechanism 500; and evaluating 705 the virtual temperature value of the given verification area.

Abstract: To eliminate the adverse effects of power swings in a large scale computing system during the life cycle of an application or job, control of several operating characteristics for the collective group of processors is provided. By providing certain levels of coordination for the many processors utilized in large scale computing systems, significant and abrupt changes in power needs can be avoided. In certain circumstances, this may involve limiting the transition between several C-States of the processors involved and the overall power transitions for a large scale system are not detrimental and do not create issues for the data center or local power utility. Some cases will require stepped transitions between C-States, while other cases will include both stepped and modulated transitions. Other cases will incorporate random wait times at the various transitions in order to spread the power consumption involved.

Abstract: A method and computing device configured to send and receive traffic over a virtual private network (VPN) connection, the computing device having a processor; and a communications subsystem, where the method determines that a first trigger had been met, wherein the first trigger is dynamically configured based on at least one factor at the computing device; monitors whether data traffic exists over the VPN connection for a first time period; and if no data traffic exists over the VPN connection for the first time period, disconnects the VPN connection.

Abstract: An electronic device and a method for changing modes according to external devices connected through a universal serial bus (USB) and controlling the strength of signals communicated according to changed modes are provided. The method includes detecting a connection with an external device corresponding to booting of the electronic device, determining a mode of the electronic device according to the detected connection with the external device, varying a characteristic setting of an input output (IO) buffer to a certain strength corresponding to the determined mode, and communicating a signal at a strength corresponding to the varied setting.

Abstract: A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects attributes of the data signal on the link to determine the link status and operate the retimer in accordance with the determined link status. By combining and reducing host and device system states into a few retimer states, the retimer circuit is largely simplified and yet still serves its purpose. The retimer includes a controller that employs a state machine to interpret the monitored and detected signals to determine the link state and operate the retimer in an operating state corresponding to the determined link state. The approach enables the retimer to restore signal integrity and forward what ever it receives in both downstream and upstream directions of the link without frequency alteration.

Abstract: A device includes a reception unit configured to receive, from outside the device, a usage request to use one of a plurality of hardware resources of the device; and a selection unit configured to select a combination of the plurality of hardware resources to which power is to be supplied, according to a state of the device. The selection unit restricts a selection of a combination, in which power is not supplied to the one of the plurality of hardware resources relevant to the usage request received from the reception unit, among the combinations of the plurality of hardware resources.

Abstract: A power supply system includes a first energy storage, a second energy storage, a power transmission circuit, and circuitry. The circuitry is configured to acquire a remaining capacity and a temperature of the second energy storage. The circuitry is configured to determine a target remaining capacity range of the second energy storage in accordance with the temperature. The circuitry is configured to control the power transmission circuit to control power transmission among the electric load, the first energy storage, and the second energy storage such that the remaining capacity of the second energy storage is within the target remaining capacity range.

Abstract: A multi-core microprocessor is organized into a plurality of resource-associated domains including core domains, group domains, and a global domain. Each domain relates to either local resources, group resources, or global resources that are respectively used by a single core, a group of cores, or all the cores. Each core has its own independently settable target operating state selected from a plurality of possible target operating states that designate configurations for the local resources, group resources, and global resources. Each core is provided with coordination logic configured to implement or request implementation of the core's target operating state, but only to the extent that implementation of the target operating state would not reduce performance of any other core below its own target operating state.

Abstract: A system includes at least one controlled device that is controlled based on control information output from an external device, and an image forming apparatus that forms an image on a recording material and communicate with the external device and the controlled device, wherein the image forming apparatus includes a transceiver that receives the control information from the external device and transmits the control information to the controlled device, and a transmission controller that stops the transmission of the control information by the transceiver or changes contents of the control information to be transmitted by the transceiver.

Abstract: Devices, systems and methods are disclosed for limiting a number of hibernations based on a finite lifetime expectancy of nonvolatile memory. As the nonvolatile memory has a finite lifetime expectancy, a device may determine cumulative thresholds and associated session thresholds and may limit a frequency that the device hibernates. For example, the device may determine a cumulative number of hibernations and associate the cumulative number of hibernations with a cumulative threshold. The device may determine a session threshold corresponding to the cumulative threshold and may limit a number of hibernations using the session threshold. For example, the device may enter a hibernation state up to the session threshold and thereafter may enter a suspended state instead.

Abstract: A DC power supply for preventing output from being misconnected to a power supply and its LED lamp and control system, comprise a DC power supply and an anti-misconnection module. The DC power supply comprises a positive output terminal and a negative output terminal. The anti-misconnection module comprises a positive access terminal and a negative access terminal which are electrically connected to the positive and negative output terminals of the DC power supply respectively, a NMOS transistor controlling on-off of the negative access terminal, a load access unit performing a turn-on operation of the NMOS transistor, a forward-blocking unit performing a turn-off operation of the NMOS transistor, and a backward access unit performing a turn-off operation of the NMOS transistor.

Abstract: As disclosed herein, a method, executed by a computer, includes comparing a current power consumption profile for a computing task with an historical power consumption profile, receiving a request for a computing resource, granting the request if the historical power consumption profile does not suggest a pending peak in the current power consumption profile or the historical power consumption profile indicates persistent consumption at a higher power level, and denying the request for the computing resource if the historical power consumption profile suggests a pending peak in the current power consumption profile and the historical power consumption profile indicates temporary consumption at the higher power level. Denying the request may include initiating an allocation timeout and subsequently ending the allocation timeout in response to a drop in a power consumption below a selected level. A computer system and computer program product corresponding to the method are also disclosed herein.

Abstract: A nonvolatile queue manager queues entries of host data from one or more host channels to one or more write buffers for storage in one or more nonvolatile memory devices of a nonvolatile memory array. The nonvolatile queue manager compares a number of the entries queued to one or more nonvolatile memory holdup power write thresholds based on detecting a power loss event. The nonvolatile queue manager tracks one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds. The nonvolatile queue manager initiates a mitigation action on a subsequent restoration of power to handle the one or more locations in the nonvolatile memory array targeted by one or more of the entries extending beyond the one or more nonvolatile memory holdup power write thresholds.

Abstract: A processor includes logic to generate a wakeup code value for a deep sleep state in which the processor is powered down, store the wakeup code value to a first location in a power domain in which power is maintained in the deep sleep state, store the wakeup code value to a second location in a non-volatile memory device, and initiate entry into the deep sleep state. The processor also includes logic to begin execution of a wakeup sequence upon waking up from the deep sleep state. The wakeup sequence includes a determination of whether a value read from the second location and a value read from the first location match. If they do not match, the processor triggers an exception handling sequence, which may include a secure boot sequence. If they match, the processor continues executing the wakeup sequence without executing a secure boot sequence.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: The present disclosure relates to a method and system for securing a performance state change of one or more processors. A disclosed method includes detecting a request to change a current performance state of a processor to a target performance state, and adjusting an operating level tolerance range of the current performance state to include operating levels associated with a transition from the current performance state to the target performance state. A disclosed system includes an operating system module operative to transmit a request for a performance state change of at least one processing core. The system includes performance state control logic operative to change the performance state of the at least one processing core based on the request.

Abstract: According to one embodiment, a memory system is connectable to a host including a first memory. The memory system includes a non-volatile second memory, a volatile third memory, and a controller. The controller uses the third memory as a work memory, and executes data transfer between the host and the second memory. The controller receives a first command to change a power mode from the host. The controller transfers first data to the first memory and transfers second data to the second memory in response to the receipt of the first command. The controller transmits a response of completion of data transfer. The first data and the second data are included in third data. The third data is data in the third memory.

Abstract: In some embodiments, a system includes a memory testing circuit configured to perform a test to determine whether a portion of a memory is operational at a specified amount of time after a power-up request by performing operations. The operations may include sending a power-up request to the portion. The operations may further include sending, at the specified amount of time after the power-up request, a write request for a write operation at the portion. The operations may further include sending a read request that requests a read operation for data written by the write operation. The operations may further include determining, based on data received in response to the read request, whether the portion correctly performed the read operation and the write operation.

Abstract: A serial point-to-point link interface to enable communication between a processor and a device, the high speed serial point-to-point link interface including a transmitter to transmit serial data, a receiver to deserialize serial data, and control logic to implement a protocol stack. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is maintained, and a second off state, in which the supply voltage is not to be provided to the device. The protocol stack provides a default recovery time to allow the device to begin a transition from the first off state to the active state prior to accessing the device. The protocol stack further provides for accessing the device prior to expiration of the default recovery time to complete the transition based on a device-advertised recovery time.

Abstract: A battery monitoring unit includes a control IC, a CPU, and a load circuit. In the inside of the battery monitoring unit, the control IC and the CPU each of which is a control circuit are connected to a unit internal ground that is common thereto. The load circuit is connected to a power ground different from the unit internal ground. In the inside of the battery monitoring unit, the power ground and the unit internal ground are connected with each other via a diode. The unit internal ground and the power ground are connected to an external ground that is common thereto via an electric wire extending from a first ground terminal and an electric wire extending from a second ground terminal, respectively.

Abstract: Described herein are systems and methods that reduce power consumption for an electronics device including a display. The systems and methods alter video information in a display area and reduce power for a display device when a graphics item is enlarged and the enlargement threatens to increase perceived luminance for the graphics item or increase aggregate luminance for the display area. Altering the video information reduces the luminance of video information in at least the graphics item when enlarged. This may offset perceived luminance gained by human visual processing when an item increases in size. If the graphics item is smaller than the display area after enlargement, then other video information in the display area may also be altered to conserve power.

Abstract: A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.

Abstract: An electronic device includes a first processor; and a second processor; and a third processor. The second processor is configured to detect an event, select one of the first and third processors to perform one or more operations associated with the event, and cause the selected processor to perform the one or more operations.

Abstract: A method is provided for managing power consumption within a multi-core microprocessor. An operating system issues an operating system instruction to transition a recipient core to a targeted power and/or performance state that is one of many possible states into which a microprocessor can place a core. Each core of the microprocessor has its own target state, and different cores may have different target states. After receiving the instruction, the recipient core implements any settings associated with its target core state that wouldn't affect resources shared with other cores. The recipient core also initiates an inter-core discovery process to determine a target multi-core state of all the cores sharing the resource. The target multi-core state reflects one or more settings that match the settings of the recipient core's target core state as much as possible without lowering a performance of any resource-sharing core below that core's own target core state.

Abstract: A power supply controller system includes a power supply portion, arithmetic processing portions, and first and second monitoring circuits configured to monitor an integrity of power supply of the power supply portion. The first monitoring circuit instructs a second arithmetic processing portion to stop an operation thereof when a first watchdog timer is not reset for a predetermined period of time. The second monitoring circuit instructs a first arithmetic processing portion to stop an operation thereof when a second watchdog timer is not reset for a predetermined period of time. The first monitoring circuit further includes a third watchdog timer periodically reset by any one of the first arithmetic processing portion and the second arithmetic processing portion and instructs another arithmetic processing portion to stop an operation thereof when the third watchdog timer is not reset for a predetermined period of time.

Abstract: In a wearable terminal, a controller determines whether a direction of a display surface detected by a detector is within a first angle range. In a case where a latest direction of the display surface is out of the first angle range, the controller puts the display in a sleep state, but otherwise the controller puts the display in an active state. Furthermore, the controller specifies a second angle range from the second reference direction. The controller switches the display from the sleep state to the active state in a case the controller determines that the plurality of directions of the display surface detected in the first period and that the direction of the display surface newly detected by the detector is out of the second angle range. In the second display control, the display is switched from the sleep state to the active state even when the newly detected direction of the display surface is out of the first angle range.

Abstract: An image forming apparatus includes a fixing portion, a temperature detection portion, a power supply portion, a control portion, a photovoltaic module and a power storage/supply portion which stores power from the photovoltaic module and which performs power supply to the temperature detection portion when power supply from the power supply portion to the temperature detection portion is stopped. The control portion detects, when a return condition is satisfied, the temperature of the fixing portion based on the output of the temperature detection portion, and as a temperature on return is higher, the control portion starts fixing return processing at later timing whereas as the temperature on return is lower, the control portion starts the fixing return processing at earlier timing.

Abstract: Systems and methods for operating based on recovered waste heat are described. In one example, the method includes receiving recovered waste heat power and operating at least one system component of a recovered waste heat based computing device based on the recovered waste heat power, where the at least one system component is coupled to a non-volatile memory of the recovered waste heat based computing device. The method further includes preserving operational states of the at least one system component in the non-volatile memory based on a current power level associated with the recovered waste heat power.

Abstract: An apparatus and method for reducing power consumption of a portable terminal are provided. More particularly, an apparatus and method for reducing power consumption generated in an idle state in order to solve a power consumption problem in a portable terminal are provided. The apparatus includes a state determination unit which is configured independently from an application processor for controlling applications and which wakes up when entering an idle mode to allow the application processor to sleep, and thereafter determines a state of the portable terminal, and if it is determined that the portable terminal escapes from the idle mode, allows the application processor to wake up.

Abstract: A control system includes a housing engaged to a mounting surface, a sensor contained within the housing, a microcontroller unit connected to the sensor, a server in communication with the sensor, and a terminal device in communication with the server. The system starts in an idle mode with the microcontroller having low power consumption. A gesture by a user associated with the mounting surface switches or toggles the operating mode of the control system into a ready mode. In the ready mode, the microcontroller has higher power consumption so as to connect the sensor to the server, and gestures by the user associated with the mounting surface can control the terminal device. The system alerts the switch in operating mode and filters background environment so only gestures are interpreted for switching operation mode or for issuing commands of the terminal device.

Abstract: Technology for concurrently powering equipment from multiple power sources, and the control thereof is disclosed. One example implementation of the technology includes a first power supply that powers equipment from a first power source and a second power supply that also powers the equipment from a second power source while the equipment is being powered by the first power supply. A target direct current (DC) output voltage of at least one of the power supplies is changed, thereby changing a ratio of the power being drawn from the first power supply to the power being drawn from the second power supply.

Abstract: A data storage system includes a host having a write buffer, a memory region, a submission queue and a driver therein. The driver is configured to: (i) transfer data from the write buffer to the memory region in response to a write command, (ii) generate a write command completion notice; and (iii) send at least an address of the data in the memory region to the submission queue. The host may also be configured to transfer the address to a storage device external to the host, and the storage device may use the address during an operation to transfer the data in the memory region to the storage device.

Abstract: Methods and mechanisms for improved performance in a system with power management are described. A system includes a data storage device configured to store data and a display control unit configured to retrieve data from the data storage device. The data storage device may be placed in a reduced power state that results in increased latencies for accessing data within the device. The display control unit is configured to monitor an amount of data available for processing within the display control unit. In response to determining the amount of data has fallen to a threshold level, and in anticipation of a forthcoming data access request, the display control unit conveys an indication that prevents the data storage device from entering or remaining in the reduced power state. Subsequently, the display control unit conveys a request for data to the data storage device which will not be in the reduced power state.

Abstract: The present disclosure provides a technology for suitably generating a post-system-resume screen. An information processor includes: a mode control section adapted to select power saving mode as an operation mode; and a screen control section adapted to generate a display screen, in which when a user logs in after the mode control section switches the mode from power saving mode to normal mode, the screen control section generates a display screen to match the user who has logged in.

Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having multiple host resources, information regarding respective power states of the host resources. The data are selectively directed from the peripheral device to the host resources responsively to the respective power states.

Abstract: A remote override system may comprise a remote device and a local device. The remote device may include a remote device computer having a remote device processor and a remote device communication interface, and an outgoing override signal handler capable of sending an override signal by way of the remote device communication interface. The local device may include a local device computer having a local device processor and a local device communication interface, and an incoming override signal handler capable of receiving the override signal by way of the local device communication interface. The override signal may be capable of causing override of a power saving mode at the local device.

Abstract: Embodiments of the present disclosure provide a monitoring report generation method where the method includes: receiving a monitoring parameter broadcast by a base station; monitoring energy of each discovery resource in a resource pool within a discovery time domain; determining a busy resource and an idle resource; and generating a monitoring report when a proportion of the busy resource or the idle resource in a predetermined quantity of consecutive discovery time domains meets a reporting condition corresponding to the busy resource or the idle resource, and sending the monitoring report to the base station. This resolves a problem in the related technology that: because D2D user equipment cannot accurately obtain a quantity of resource collision times in a cell, the base station cannot accurately learn a resource status in the cell, and it is ensured that the base station can accurately learn the resource status in the cell.

Abstract: A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.

Abstract: In one embodiment, a method includes a server receiving activity data from a plurality of computing devices, wherein the activity data is associated with running a particular application; identifying, based on the activity data, a pattern of execution related to executing one or more sequences of instructions associated with running the particular application; determining, based on the pattern of execution, a clocking policy for running the particular application, wherein the clocking policy is configured to modify a clock speed of one or more processors of a particular computing device while running the particular application; and sending the clocking policy to the particular computing device.