By Shutdown Of Only Part Of System Patents (Class 713/324)
  • Patent number: 10819607
    Abstract: A method includes obtaining component utilization data for multiple components of a compute node during at least one previous execution of a workload. The method further includes using the component utilization data to identify a first component having a utilization level that is less than a threshold utilization level during the at least one previous execution of the workload, wherein the first component is one of the multiple components of the compute node. The method still further includes, during a subsequent execution of the workload on the compute node, throttling the first component to prevent the first component from exceeding the threshold utilization level.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: October 27, 2020
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Srihari V. Angaluri, Gary D. Cudak, Ajay Dholakia, Chulho Kim
  • Patent number: 10819870
    Abstract: An image processing apparatus includes an image-data processor, an interface, a power source, and a controller. The controller selects a first mode, a second mode, or a third mode as a power supply mode. In the first mode, electric power is supplied from the power source to the image-data processor and the interface. In the second mode, supply of the electric power from the power source to the image-data processor and the interface is in a stopped state. In the third mode, the electric power is supplied from the power source to the interface, but supply of the electric power to the image-data processor is in a stopped state. The controller switches the power supply mode from the second mode to the third mode in response to receiving a power supply request from an external device via the interface in the second mode.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 27, 2020
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Naoki Abe, Hajime Usami
  • Patent number: 10809896
    Abstract: A display apparatus and a method of controlling a display apparatus are provided. The display apparatus includes a display configured to display a screen including a plurality of objects, an input device configured to receive a predefined user command while the screen is displayed, and at least one processor configured to, in response to the predefined user command being input, enter a setting mode for selecting an always-on display object, in response to at least one of the plurality of objects being selected by user input during the setting mode, set a selected object to an always-on display object, and in response to a mode of the display apparatus being changed to a standby mode, control the display to display the selected object on a monochrome background screen.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hun-seop Jeong, Keun-seob Kim, Jin-woo Song, Hong-uk Woo
  • Patent number: 10804800
    Abstract: To provide a power supplying control apparatus, a power supplying apparatus, and a power supplying control method which control power supply appropriately. A power supplying apparatus according to the present embodiment is equipped with a plurality of ports corresponding to a USB (Universal Serial Bus) PD (Power Delivery) standard, a plurality of electric power supplying circuits which are provided corresponding to the ports and supply power to power receiving devices coupled to the ports, and a controller which holds a table of power profiles to which power receiving capabilities for each power receiving device are set, and controls the electric power supplying circuits, based on the table in such a manner that total supply power supplied from the electric power supplying circuits does not exceed a prescribed value.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 13, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kiichi Muto
  • Patent number: 10782758
    Abstract: A framework for system power control of a dual-port non-volatile memory storage device is provided. The electronic system includes a storage device, two hosts and a control circuit within each of the two hosts. Each host filters signals for shortly turning off a power supply of the storage device during a process of boot and reboot of the host. When one of the hosts enters a turn-off state, it is detected whether another one of the hosts is running, and the one of the hosts does not control the power supply if the another one of the hosts is running. Two control signals of the two hosts control the power supply of the storage device through an AND gate.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 22, 2020
    Assignee: Wistron Corporation
    Inventors: Syu-Siang Lee, Zh-Wei Zhang
  • Patent number: 10769072
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive, in a read/modify/write (RMW) pipeline, a cache access request from a requestor, wherein the cache request comprises a cache set identifier associated with requested data in the cache set, determine whether the cache set associated with the cache set identifier is in an inaccessible invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to terminate the cache access request. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 8, 2020
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Prasoonkumar Surti, Kamal Sinha, Kiran C. Veernapu, Balaji Vembu
  • Patent number: 10755020
    Abstract: Computing assemblies, such as blade servers, can comprise a plurality of modular computing elements coupled onto an associated circuit board assembly. Assemblies and systems having enhanced individual computing module placement and arrangement are discussed herein, as well as example systems and operations to manufacture such assemblies. In one example, a method includes executing a performance test on a plurality of computing modules to determine at least variability in power consumption across the plurality of computing modules, and binning the plurality of computing modules according to graduated levels of the variability in power consumption. The method also includes selecting from among the graduated levels for placement in an assembly of ones of the computing modules in a progressively lower power consumption arrangement with relation to an airflow of the assembly.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 25, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Andres Felipe Hernandez Mojica, William Paul Hovis, Garrett Douglas Blankenburg
  • Patent number: 10721557
    Abstract: The disclosure relates to a microphone assembly including a multibit analog-to-digital converter configured to generate N-bit samples representative of a microphone signal. The microphone assembly also includes a first digital-to-digital converter configured to generate a corresponding M-bit digital signal based on N-bit digital samples, wherein N and M are positive integers and N>M. The microphone assembly may include a data interface configured to repeatedly receive samples of the M-bit digital signal and write bits of the M-bit digital signal to a data frame.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 21, 2020
    Assignee: Knowles Electronics, LLC
    Inventors: Andrzej Pawlowski, Kasper Strange, Kim Spetzler Berthelsen, Henrik Thomsen
  • Patent number: 10713059
    Abstract: A compute unit configured to execute multiple threads in parallel is presented. The compute unit includes one or more single instruction multiple data (SIMD) units and a fetch and decode logic. The SIMD units have differing numbers of arithmetic logic units (ALUs), such that each SIMD unit can execute a different number of threads. The fetch and decode logic is in communication with each of the SIMD units, and is configured to assign the threads to the SIMD units for execution based on such differing numbers of ALUs.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: July 14, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Joseph L. Greathouse, Mitesh R. Meswani, Sooraj Puthoor, Dmitri Yudanov, James M. O'Connor
  • Patent number: 10707688
    Abstract: An electronic device and method are provided. The electronic device includes a first connector including first conductive pins arranged according to a first protocol, a second connector including second conductive pins arranged according to a second protocol and different in number, and a control circuit operatively coupled to the first and second connector. The control circuit detects coupling to an external device through the first connector by at least one of the first conductive pins, receives profile information including at least one of: a power supply device operatively coupled to the second connector and identification information for an external device, and sets a charging path within the electronic device between the first connector and the second connector using at least one of the first conductive pins and the at least one of the second conductive pins coupled to the power supply device.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: July 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ba-Da Kang
  • Patent number: 10705560
    Abstract: A sensor includes an analog front end having a circuit element responsive to a clock signal and a clock generating circuit configured to generate the clock signal having blanking time periods during which the clock signal is held at a constant level, wherein the circuit element is not operational during the blanking time periods. The blanking time periods correspond to time periods during which transitions of a common mode input voltage to the sensor are expected to occur.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 7, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventor: Craig S. Petrie
  • Patent number: 10705592
    Abstract: A system includes a management device and nodes that execute plural jobs in parallel. When a total electric-power consumption of the nodes reaches a threshold, the management device extracts a first job of the largest electric-power consumption from among the plural jobs, based on information about an electric-power consumption of each node and information about the plural jobs that are executed in parallel by the nodes. The management device reduces the electric-power consumption of a first node that executes the first job when a remaining execution time of the first job, which indicates a period of time from a current time until a scheduled end time of the first job, is longer than or equal to a predetermined time, and reduces the electric-power consumption of a second node that does not execute the first job, when the remaining execution time of the first job is shorter than the predetermined time.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 7, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Lei Zhang
  • Patent number: 10701231
    Abstract: An information processing apparatus includes first and second power feed control portions and a storage processing portion. The first power feed control portion stops power feed to a nonvolatile first storage portion when reading or writing data from/to the first storage portion is completed. In a case where power feed to the first storage portion is stopped, the storage processing portion stores specific data among data stored in the first storage portion into a second storage portion. When an access request for accessing data in the first storage portion has been received: when access-target data specified in the access request is not stored in the second storage portion, the second power feed control portion resumes power feed to the first storage portion; and when the access-target data is stored in the second storage portion, does not resume the power feed to the first storage portion.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 30, 2020
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Takashi Toyoda
  • Patent number: 10691578
    Abstract: A system and method generates contextual information for a source model. An identification of one or more first model elements of interest within the source model may be received. One or more constraints on inputs of selected model elements also may be received. A scope of analysis regarding outputs of the first model elements may be specified. The contextual information may be derived automatically for the one or more first model elements. The contextual information may include one or more model elements, signals, or states that are contained with the scope of analysis while execution of the source model is limited by the one or more constraints. The derived contextual information may be provided to an output device.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: June 23, 2020
    Assignee: The MathWorks, Inc.
    Inventors: William J. Aldrich, Ebrahim Mehran Mestchian, Denizhan N. Alparslan
  • Patent number: 10691193
    Abstract: The disclosure is related to a method, an apparatus and a computer-readable medium for controlling a terminal. The method includes: obtaining a cover closing instruction where the cover closing instruction indicates that an upper cover and a lower cover of the terminal are closed; obtaining, in response to the cover closing instruction, a program running on the terminal; and determining an operation to be performed by the terminal based on the program running on the terminal, where the operation to be performed by the terminal includes any one of: shutdown, sleep, maintaining normal operation, or screen off.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Beijing Xiaomi Mobile Software Co., Ltd.
    Inventor: Ke Wu
  • Patent number: 10671438
    Abstract: A plurality of processing entities of a processor complex is maintained, wherein each processing entity has a local cache and the processor complex has a shared cache and a shared memory. One of the plurality of processing entities is allocated for execution of a critical task. In response to the allocating of one of the plurality of processing entities for the execution of the critical task, other processing entities of the plurality of processing entities are folded. The critical task utilizes the local cache of the other processing entities that are folded, the shared memory, and the shared cache, in addition to the local cache of the processing entity allocated for the execution of the critical task.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 10672451
    Abstract: A storage device and a refresh method thereof are provided. The storage device includes at least a first processing core configured to operate by receiving a first power from a host, a second processing core separate from the first processing core, at least a first three-dimensional (3D) flash memory, a power module and a retention management module supplied with a second power from the power module when the first power is not supplied from the host. The retention management module is configured to refresh a part of the first 3D flash memory using the second processing core. The retention management module is configured to be woken up at intervals of a first period to refresh the part of the first 3D flash memory.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Il Bang, Jun-Ho Jang, Dong Gi Lee
  • Patent number: 10649941
    Abstract: A method for managing two baseboard management controllers comprises connecting to a first baseboard management controller, sending an instruction to the first baseboard management controller, determining whether the instruction comprises a bridge parameter, when the instruction comprises the bridge parameter, sending the instruction to a second baseboard management controller through a bus, generating a response signal by the second baseboard management controller, and receiving the response signal by the first baseboard management controller and sending the response signal to an administration interface; otherwise, executing a corresponding operation according to the instruction by the first baseboard management controller and sending an operation result to the administration interface.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 12, 2020
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Xi-Lang Zhang, Guo-Xin Sun, Jia-Ling Hu, Li-Hong Huang
  • Patent number: 10650043
    Abstract: A KTV player in communication with at least one song server is configured to upload a song list of a song database to the song server, obtain a song playback list from the song server, obtain corresponding music scores and pitch curves from the song server according to the song playback list, obtain corresponding songs according to the song playback list, display the songs in sequence on a display, and display the corresponding music scores and pitch curves on the display synchronously with the songs. The song playback list is sent by a mobile terminal in communication with the song server.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 12, 2020
    Assignees: Fu Tai Hua Industry (Shenzhen) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Cheng-Xiang Liu
  • Patent number: 10627888
    Abstract: Embodiments are directed to a method of optimizing power consumption in an electrical device. The method includes receiving, by a processor, instructions to enter a wait state, and identifying, by the processor, a parameter associated with the instructions to enter a wait state. The method continues with initiating, by the processor, instructions to enter a low-power mode based on the parameter, initiating, by the processor, instructions to exit a low-power mode based on the parameter, and providing, via a user interface, a user with notice of a current state of the processor. The parameter includes runtime information, instructional information, and scheduled operations.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raymond M. Higgs, Luke M. Hopkins, Mushfiq Saleheen
  • Patent number: 10629165
    Abstract: According to various embodiments, a wearable device may be provided. The wearable device may include: a display panel having integrally formed a first display portion and a second display portion; and a driver circuit configured to control the first display portion with a first frequency and to control the second display portion with a second frequency.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: April 21, 2020
    Assignee: RAZER (ASIA-PACIFIC) PTE. LTD.
    Inventors: Chee Oei Chan, Jian Yao Lien, Kah Yong Lee, Joel Sze Wei Hong, Farrukh Raza Rizvi
  • Patent number: 10592775
    Abstract: An image processing method includes steps of receiving an image sequence; when at least one object appears in the image sequence, analyzing a moving trajectory of each object; extracting at least one characteristic point from each moving trajectory; classifying the at least one characteristic point of each moving trajectory within a predetermined time period into at least one cluster; and storing at least one characteristic parameter of each cluster.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: March 17, 2020
    Assignee: VIVOTEK INC.
    Inventors: Cheng-Chieh Liu, Chih-Yen Lin
  • Patent number: 10551434
    Abstract: A rechargeable power module (RPM) may include a rechargeable energy storage device such as a battery or capacitor, a charging circuit, a direct-current (DC) to DC converter, a low drop-out (LDO) voltage regulator and a controller. The charging circuit provides the rechargeable energy storage device with a charging current based on power requirements of device under test and the state of charge, or storage, of the energy storage device.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Woon Yoo, Ki-Jae Song, Soo-Yong Park
  • Patent number: 10503517
    Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Rinat Rappoport, Michael Mishaeli, Hisham Shafi, Oron Lenz, Jason W. Brandt, Stephen A. Fischer, Bret L. Toll, Inder M. Sodhi, Alon Naveh, Ganapati N. Srinivasa, Ashish V. Choubal, Scott D. Hahn, David A. Koufaty, Russel J. Fenger, Gaurav Khanna, Eugene Gorbatov, Mishali Naik, Andrew J. Herdrich, Abirami Prabhakaran, Sanjeev S. Sahagirdar, Paul Brett, Paolo Narvaez, Andrew D. Henroid, Dheeraj R. Subbareddy
  • Patent number: 10481674
    Abstract: Self-configured, power-aware circuitry configured to enhance power efficiency within integrated circuitry by self-calibrating the power consumption utilized within the integrated circuitry according to the requirements of an application program running within the integrated circuitry. The power consumption is self-calibrated within the integrated circuitry on a per application-based manner so that the integrated circuitry can be implemented with a plurality of various generalized functionalities, each of which may or may not be utilized while a specific application program is running within the integrated circuitry. Power consumption within the integrated circuitry is reduced by independently and dynamically controlling multiple power sections delineated within the integrated circuitry.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: November 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jayanta Bhadra, Wen Chen, Monica Farkash, Kuo-Kai Hsieh
  • Patent number: 10459525
    Abstract: A method of operating a touchless user interface on an electronic device is disclosed. The electronic device is configured to determine information regarding the position and/or movement of an input object. The method has the steps of: deciding that an engagement gesture has been performed; deciding that a related input gesture has been performed; and carrying out an operation on the device on the basis of the input gesture only if the engagement gesture has been recognized and if the input gesture is one of a subset of possible input gestures determined by the engagement gesture.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: October 29, 2019
    Assignee: ELLIPTIC LABORATORIES AS
    Inventors: Guenael Strutt, Joachim Bjørne, Geir Birkedal
  • Patent number: 10431161
    Abstract: A display device includes a plurality of latch circuits which latch gradation data that is used to drive a plurality of data lines, a plurality of D/A converters which convert gradation data that is latched to the plurality of latch circuits to a plurality of analog signals, a plurality of amplifiers which generate a plurality of gradation signals by respectively amplifying the plurality of analog signals output from the plurality of D/A converters, and an analysis circuit that analyzes gradation data that is latched to the plurality of latch circuits and reduces direct current that flows in at least one amplifier or at least one D/A converter according to an analysis result.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: October 1, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Tsuyoshi Tamura
  • Patent number: 10423559
    Abstract: A selectively upgradeable disaggregated server is generally described herein. An example modular server unit, the modular server unit includes a processor module coupled to an input/output (I/O) module via a connector. The processor module to communicate with the I/O module via the connector to store and retrieve data. The processor module is a separate hardware unit from the I/O module.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Sheshaprasad G Krishnapura, Vipul Lal, Mohan J Kumar, Shaji Kootaal Achuthan, Ty H. Tang
  • Patent number: 10409827
    Abstract: An integrated circuit may be provided with cryptocurrency mining capabilities. The integrated circuit may include control circuitry and a number of processing cores that complete a Secure Hash Algorithm 256 (SHA-256) function in parallel. Logic circuitry may be shared between multiple processing cores. Each processing core may perform sequential rounds of cryptographic hashing operations based on a hash input and message word inputs. The control circuitry may control the processing cores to complete the SHA-256 function over different search spaces. The shared logic circuitry may perform a subset of the sequential rounds for multiple processing cores. If desired, the shared logic circuitry may generate message word inputs for some of the sequential rounds across multiple processing cores. By sharing logic circuitry across cores, chip area consumption and power efficiency may be improved relative to scenarios where the cores are formed using only dedicated logic.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 10, 2019
    Assignee: 21, Inc.
    Inventors: Veerbhan Kheterpal, Daniel Firu, Nigel Drego
  • Patent number: 10401945
    Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: September 3, 2019
    Assignee: Apple Inc.
    Inventors: David J. Williamson, Gerard R. Williams, III, James N. Hardage, Jr., Richard F. Russo
  • Patent number: 10395069
    Abstract: A computer system detects that a mobile device of a user is in a location that exceeds a threshold distance from a second device of the user. Based on at least the detecting, the computer system switches the mobile device to stealth mode, wherein switching the mobile device to stealth mode includes determining an image that visually matches a surface directly below the mobile device, and displaying the image on at least one display of the mobile device. The computer system determines that the second device of the user is located within the threshold distance of the mobile device. Based on the determining, the computer system initiates one or more actions to alert the user as to the location of the mobile device.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: August 27, 2019
    Assignee: PAYPAL, INC.
    Inventor: Michael Charles Todasco
  • Patent number: 10386902
    Abstract: Methods and systems for supplying more power than a power limit to a powered device (PD) if the PD is capable of receiving power more than the power limit, and receiving power more than the power limit from a power sourcing equipment (PSE) if the PSE is capable of supplying power more than the power limit. The PD and the PSE operates in a power over Ethernet (PoE) environment. The system comprises a power receiving section and a power supply section. The power receiving section comprises a first power-receiving circuit and a second power-receiving circuit, where the first power-receiving circuit is used when receiving power up to the power limit, and the second power-receiving circuit is used when receiving power more than the power limit.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 20, 2019
    Assignee: PISMO LABS TECHNOLOGY LIMITED
    Inventors: Ming Pui Chong, Tik Yan Wong
  • Patent number: 10382427
    Abstract: The authentication of a client to multiple server resources with a single sign-on procedure using multiple factors is disclosed. One contemplated embodiment is a method in which a login session is initiated with the authentication system of a primary one of the multiple server resources. A first set of login credentials is transmitted thereto, and validated. A token is stored on the client indicating that the initial authentication was successful, which is then used to transition to a secondary one of the multiple resources. A second set of login credentials is also transmitted, and access to the secondary one of the multiple resources is granted on the basis of a validated token and second set of login credentials.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: August 13, 2019
    Assignee: SecureAuth Corporation
    Inventors: Mark V. Lambiase, Garret Florian Grajek, Jeffrey Chiwai Lo, Tommy Ching Hsiang Wu
  • Patent number: 10365706
    Abstract: Asymmetric power states on a communication link are disclosed. In one aspect, the communication link is a Peripheral Component Interconnect (PCI) express (PCIe) link. PCIe is a point-to-point communication link between two termini. Exemplary aspects of the present disclosure allow the two termini to be in different power states. By allowing the two termini to be in the different power states, an individual terminus may be put into a low-power state even though the other terminus is maintained at a higher-power state. The different power states are enabled by providing switches between a reference clock and respective termini such that the reference clock may selectively be provided to only one terminus of the communication link, allowing that terminus to remain in the higher-power state while the other terminus enters a low-power state that does not require the reference clock.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: July 30, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: William Bakshi, Nabeel Achlaug
  • Patent number: 10359824
    Abstract: A display apparatus including a display configured to display an image; a connecting section configured to connect with an external apparatus that includes at least one operating section and a charging section to be charged with power to be supplied to the operating section; a power supply configured to supply power to the external apparatus connected to the connecting section; and a controller configured to receive information about power used by at least one operating section of the external apparatus connected to the connecting section, determine a level of power supplied to the external apparatus according to the received power information and usage power of the display, and control the power supply to supply power having the determined level to the external apparatus.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ho-seong Seo
  • Patent number: 10338837
    Abstract: This disclosure relates to allocating memory resources of a computing device comprising non-volatile random access memory (NVRAM) and dynamic random access memory (DRAM). An exemplary method is performed for every independently executable component of an application and includes determining attributes of the component. The method also includes associating the component with a memory profile of a plurality of memory profiles based on the attributes, wherein each memory profile of the plurality of memory profiles specifies a number of banks of the NVRAM and a number of banks of the DRAM. The method also includes causing the computing device to generate an assignment of the component to banks of the NVRAM and DRAM based on the memory profile associated with the component so the computing device can execute the component using the banks of the NVRAM and DRAM based on the assignment.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Subrato Kumar De, Dexter Tamio Chun, Yanru Li, Bohuslav Rychlik, Richard Alan Stewart
  • Patent number: 10338665
    Abstract: A microcontroller that can be configured to selectively operate in a synchronous mode or an asynchronous mode, and a method of selectively switching the operating mode is described. The microcontroller can include a processor and a system controller. The processor can be configured to operate synchronously in a synchronous operating mode and asynchronously in an asynchronous operating mode. The processor can also be configured to generate a processor idle status signal indicative of the processor operating in a reduced power mode, and generate a programming signal. The system controller can be configured to generate an asynchronous mode signal based on the programming signal and the processor idle status signal, and provide the asynchronous mode signal to the processor to control the processor to selectively operate in the synchronous operating mode and in the asynchronous operating mode.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: July 2, 2019
    Assignee: Infineon Technologies AG
    Inventor: Prakash Kalanjeri Balasubramanian
  • Patent number: 10326834
    Abstract: Cloud services require the outward appearance of unlimited resources with flexible availability for varying demand. However, while on-demand allocation and deallocation of resources may seem efficient, there are significant cases where simply allocating and deallocating resources just in response to demand results in inefficiencies. As discussed herein, cloud services can be made more efficient by deallocating resources based on delays incurred between when resources are requested to be deallocated and reallocated and when they actually are deallocated and allocated, and for how long the resource would be returned to the cloud before needing to be reallocated. Deallocating resources more efficiently not only gives a direct performance improvement, but also indirect, since deallocated resources may not be available again when demand increases.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: June 18, 2019
    Assignee: AT&T Intellectual Property I, L.P.
    Inventor: Robert Todd Stephens
  • Patent number: 10282124
    Abstract: A mechanism is provided for opportunistic handling of freed data in data de-duplication. Responsive to receiving a request to store a file in a storage device, the file is mapped to a set of virtual blocks. For each virtual block in the set of virtual blocks: a hash value is computed, a determination is made as to whether the computed hash value appears within a previously-used information table as associated with an existing data block, and, responsive to the computed hash value appearing within a previously-used information table as associated with an existing data block, a data block entry and hash value associated with the existing data block is moved to a de-duplication information table. The virtual block is then stored as a reference to the existing data block.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Erik Rueger, Heiko H. Schloesser, Christof Schmitt
  • Patent number: 10250408
    Abstract: A communication device includes a plurality of controllers, a plurality of buses that transmit transmission information, and a gateway to which the plurality of buses are collectively connected. Each of the plurality of controllers has a pattern table that defines, for each piece of the transmission information, a transmission bus pattern, and controls the input and output of the transmission information according to the pattern table. Each of the plurality of controllers is connected to at least two buses, and outputs, to the gateway via all of the connected buses, check information for a confirmation of connections to the connected buses. The gateway determines an interrupted bus from which no check information is input, and outputs, to each of the plurality of controllers, a route switch instruction instructing use of a pattern table that does not include the interrupted bus(es).
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: April 2, 2019
    Assignee: DENSO CORPORATION
    Inventor: Hiroyuki Kawada
  • Patent number: 10241932
    Abstract: In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in the immediate previous memory address. For a write function, new data will only be written into the current memory address if it is different from the data in the immediate previous memory address. Similarly, for a read function, the data will only be read out of the current memory address if it is different from the data in the immediate previous memory address. Each row in the memory may have one associated status bit outside the memory. Data may only be written to or read from the current memory address when the status bit is set. Clock gating the memory ports may reduce the overall power consumption of the memory.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: March 26, 2019
    Assignee: INTEL CORPORATION
    Inventor: Sutirtha Deb
  • Patent number: 10209911
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for determining when a communications port is in a first low power state, determining that a coupled device entered a low power state and enabling a second low power state based on the determination that the device has entered the low power state, the second low power state to use less power than the first low power state.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: February 19, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jennifer Chin, Su Wei Lim, Poh Thiam Teoh, Ting Lok Song, Sun Zheng E, Say Cheong Gan
  • Patent number: 10194393
    Abstract: The invention provides for mobile radio communications device (10) for operation within a mobile radio communications network and arranged to employ one of a plurality of possible power saving modes, and arranged to send non-access stratum or access stratum signalling (14) to the network including an indication of at least one of the said plurality of possible power saving modes, and responsive to which indication the network (12) is arranged to return confirmation (16) of the power saving mode to be employed by the mobile radio communications device (10), the mobile radio communications device (10) further being arranged to receive the said confirmation (16) and to initiate operation of the confirmed power-saving mode (26; 38; 44).
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: January 29, 2019
    Assignee: NEC Corporation
    Inventors: Hayato Haneji, Iskren Ianev, Yannick Lair
  • Patent number: 10191597
    Abstract: This disclosure generally provides an input device modulates a reference voltage used to provide power to a plurality of power supplies and acquires, while modulating the reference voltage, first resulting signals from a plurality of sensor electrodes simultaneously at a central receiver. In input device also acquires second resulting signals from the sensor electrodes at a plurality of local receivers and mitigates an effect a grounding condition has on the second resulting signal using the first resulting signals.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 29, 2019
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Kasra Khazeni, Joseph Kurth Reynolds
  • Patent number: 10176043
    Abstract: Example implementations relate to a memory controller. For example, an apparatus includes a data storage device and a memory controller coupled to the data storage device. The memory controller is to perform, during a memory scrubbing operation, a corrective action to correct an error associated with a data block stored in the data storage device. The memory control is to determine, during the memory scrubbing operation, whether the corrective action is successful. In response to a determination that the corrective action is a failed corrective action, the memory controller is to fix a hardware failure of the data storage device based on a type of the hardware failure.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: January 8, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Chris Michael Brueggen, Lidia Warnes
  • Patent number: 10169030
    Abstract: A method, system and computer program product are provided for refreshing a software component without interruption. The method includes detecting when a current instance of the software component is inactive and activating a refresh process of the software component in parallel to the current instance, including starting a new instance of the software component. The method further includes monitoring a state of the current instance and, when the current instance ceases to be inactive, canceling the refresh process. The method includes determining that the refresh process is complete and switching from the current instance to the new instance of the software component.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ivo Claessens, Roy Janssen, Ramon L. H. Pisters, Frank Van Ham
  • Patent number: 10162541
    Abstract: An adaptive block cache management method and a DBMS applying the same are provided. A DB system according to an exemplary embodiment of the present disclosure includes: a cache configured to temporarily store DB data; a disk configured to permanently store the DB data; and a processor configured to determine whether to operate the cache according to a state of the DB system. Accordingly, a high-speed cache is adaptively managed according to a current state of a DBMS, such that a DB processing speed can be improved.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: December 25, 2018
    Assignee: Korea electronics technology institute
    Inventors: Jae Hoon An, Young Hwan Kim, Chang Won Park
  • Patent number: 10158585
    Abstract: Generally, this disclosure provides devices, methods and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: December 18, 2018
    Assignee: INTEL CORPORATION
    Inventors: Eliezer Tamir, Jesse C. Brandeburg, Anil Vasudevan
  • Patent number: 10152600
    Abstract: An embodiment: (a) receives a request for a measurement of a hypervisor from at least one computing node that is external to the at least one machine; (b) executes a previously measured measuring agent to measure the hypervisor, after the hypervisor is measured and booted, to generate a measurement while: (b)(i) the at least one machine is in virtual machine extension (VMX) root operation, and (b)(ii) the measuring agent is in a protected mode; (c) attest to the measurement, based on at least one encryption credential, to generate an attested measurement output; and (d) communicate the attested measurement output to the at least one computing node. The hypervisor does not include the at least one encryption credential while the measuring agent is measuring the booted hypervisor. Other embodiments are described herein.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Carlos V. Rozas, Vincent R. Scarlata
  • Patent number: RE48190
    Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: September 1, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fubito Igari