By Shutdown Of Only Part Of System Patents (Class 713/324)
  • Patent number: 10085111
    Abstract: A method of communicating with multiple other devices by a low energy device, the method including broadcasting advertisements from the low energy device to connect, the advertisements being broadcasted at a slow rate, receiving an event at the low energy device, responsive to receiving the event, broadcasting advertisements at a high rate for a selected period of time, and connecting and disconnecting with the multiple other devices to exchange information related to the event during the selected period of time.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: September 25, 2018
    Assignee: Honeywell International Inc.
    Inventors: Arun V. Mahasenan, Soumitri N. Kolavennu, Praveen Kumar Volam
  • Patent number: 10084484
    Abstract: A storage control apparatus obtains first-code attached data, each having target data to be written and first code information, which includes an error detection code based on the target data and information about a first write destination, attached to the target data. The storage control apparatus then obtains the target data by excluding the first code information from the first-code attached data eliminates duplication of the target data, generates second code information which includes an error detection code for the target data remaining and information about a second write destination, and writes second-code attached data including the second code information into a memory device.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: September 25, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Katsuhiko Nagashima
  • Patent number: 10073513
    Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: William C. Rash, Martin G. Dixon, Yazmin A. Santiago
  • Patent number: 10068108
    Abstract: An approach is provided for providing secure signing and utilization of distributed computations. A distributed computation authentication platform causes, at least in part, a signing of one or more computation closures of at least one functional flow. The distributed computation authentication platform also processes and/or facilitates a processing of the one or more signed computation closures to cause, at least in part, a transfer of the one or more signed computation closures among one or more levels, one or more nodes, or a combination thereof, wherein an execution of the one or more signed computation closures at the one or more levels, the one or more nodes, or a combination thereof is based, at least in part, on an authentication of the signed one or more computation closure.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: September 4, 2018
    Assignee: NOKIA TECHNOLOGIES OY
    Inventors: Sergey Boldyrev, Jari-Jukka Harald Kaaja, Hannu Ensio Laine, Jukka Honkola, Vesa-Veikko Luukkala, Ian Justin Oliver
  • Patent number: 10061655
    Abstract: The disclosed technology provides for off-loading dirty data from a volatile cache memory to multiple non-volatile memory devices responsive to detection of a power failure. The arrangement of the dirty data is describable by a cache image, which is reconstructed within the volatile memory from the non-volatile memory devices responsive to detection of power restoration following the power failure.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 28, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Shashank Nemawarkar, Balakrishnan Sundararaman, Mark Ish
  • Patent number: 10063999
    Abstract: A method, system, and/or apparatus for automatically tracking and sending electronic reminder messages to a mobile user using the user's mobile device as a function of the user's tracked location. This invention is particularly useful in the field of social media, such as for detecting and tracking the location of a user and her community for actuating reminders based upon the user's location and/or the location of members of the community. The method or implementing software application uses or relies upon location information available on the mobile device from any source, such as GPS, cell phone usage, WiFi triangulation, and/or other device applications.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: August 28, 2018
    Assignee: PUSHD, INC.
    Inventors: Ben Cherry, Abdur Chowdhury, Ophir Frieder, Eric Jensen, Matt Sanford
  • Patent number: 10049080
    Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 14, 2018
    Assignee: INTEL CORPORATION
    Inventors: Varghese George, Sanjeev S. Jahagirdar, Deborah T. Marr
  • Patent number: 10037159
    Abstract: A memory system includes a memory device including a plurality of blocks and a plurality of page buffers which respectively correspond to the blocks, wherein each of the blocks includes a plurality of pages in which data is stored, and a controller suitable for backing up data, which is stored in a memory included in the controller, in the page buffers when an operation mode is about to change to a power save mode.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 31, 2018
    Assignee: SK Hynix Inc.
    Inventors: Dong-Jae Shin, Jong-Ju Park, Young-Jin Park
  • Patent number: 10037073
    Abstract: A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 31, 2018
    Assignee: Apple Inc.
    Inventors: Edvin Catovic, Rajat Goel, Richard F. Russo, Matthew R. Johnson, Shingo Suzuki, Pradeep Kanapathipillai, Raghava Rao V. Denduluri, Pankaj Lnu
  • Patent number: 10013046
    Abstract: Systems, apparatuses, and methods for improved power management techniques. An apparatus may include a display control unit, a communication fabric, a memory controller, a memory cache, and a memory. When the memory is power-gated, and the display control unit needs to fetch pixel data, the display control unit may send a wake-up signal to the memory before sending a wake-up signal to the communication fabric. The display control unit may then issue the pixel fetch request later. Additionally, if the display control unit determines that the pixel data has a high probability of being cached, then the display control unit may not send a wake-up signal to the memory, and the display control unit may issue the request earlier. More generally, the display control unit may send wake-up signals to multiple components in a manner which accounts for the wake-up latency of each component.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 3, 2018
    Assignee: Apple Inc.
    Inventors: Peter F. Holland, Hao Chen, Sukalpa Biswas
  • Patent number: 10008285
    Abstract: A semiconductor device includes a flip-flop circuit that includes a first and a second latch coupled to the first latch. The first latch stores data in a first operating mode in which power is supplied to the first latch and is shut off in a second operating mode in which power is not supplied to the first latch. The second latch can store the data from the first latch during a transition from the first operating mode to the second operating mode. The first latch can be tested during a first period in the first operating mode. The second latch retains the data from the first latch during the first period and can be tested during a second period beginning in the first operating mode.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 26, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shuichi Kunie
  • Patent number: 10002405
    Abstract: A mechanism is described for facilitating smart optimization of unused graphics buffer memory in computing environments. A method of embodiments, as described herein, includes detecting a software application at a computing device, where the software application to place a request for a task capable of being executed by a processor of the computing device. The method may further include allocating a composition of buffers and facilitate allocation of physical memory to the buffers to be used to perform the task, where a first portion of the physical memory and a second portion of the physical memory are allocated to first one or more of the buffers and second one or more of the buffers, respectively.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Jason Barstow, Gary Smith
  • Patent number: 9985778
    Abstract: This specification describes an integrated circuit comprising: a single wire interface; a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency that is based on the detected voltage; and a digital system coupled with the single wire interface and the clock circuit. The digital system is configured to: receive a data signal from the single wire interface; power the digital system using a power signal from the single wire interface; and perform one or more operations clocked by the clock signal.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: May 29, 2018
    Assignee: Atmel Corporation
    Inventor: Albert S. Weiner
  • Patent number: 9973429
    Abstract: A data center interconnection (DCI) network may comprise a data center controller (DCC) managing a plurality of data centers (DCs) interconnected by a provider network managed by a network provider controller (NPC). The provider network may be an OpenFlow based software defined networking (SDN) transport network. The DCC may initiate a virtual network service (VNS) negotiation with the NPC to connect the DCs and may specify a network abstraction granularity level. The NPC may respond by computing paths through the provider network accordingly and providing the DCC with one or more virtual networks (VNs). The DCC may compute virtual paths through the VNs and send virtual network element (VNE) connection setup commands to the DCC. The DCC may convert the VNE connection setup commands into network element (NE) commands to setup connections in NEs of the provider network. The DCC and the NPC may perform fault monitoring, detection, and recovery.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: May 15, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Young Lee, Maarten Vissers, T. Benjamin Mack-Crane
  • Patent number: 9952792
    Abstract: Methods, systems, and computer readable media for storage device workload detection using power consumption are disclosed. One aspect of the subject matter described herein includes a storage device. The storage device includes non-volatile storage. The storage device further includes a device controller for controlling access to the non-volatile storage. A power management controller separate from the device controller senses an indication of power used by at least one of the non-volatile storage and the device controller, compares the sensed indication of power to at least one threshold, and, in response to a predetermined relationship between the sensed indication of power and the at least one threshold, signals the device controller of a workload state of the storage device.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: April 24, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Gadi Vishne, Nir Amir, Judah Gamliel Hahn
  • Patent number: 9936092
    Abstract: In an electronic apparatus of this invention, after a security function is canceled, it is determined whether the elapsed time from cancellation of the security function to detection of attachment of a device having a security function of security level higher than that of the canceled security function or the elapsed time until the operation of the attached device is enabled has exceeded a predetermined time. Upon determining that the elapsed time has exceeded the predetermined time, the electronic apparatus enables the canceled security function again.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 3, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Akihiro Matsumoto
  • Patent number: 9910480
    Abstract: Customers in a multi-tenant environment can obtain energy consumption information for a set of resources or other computing components used by those customers, including time-accurate accounting for various components of those resources utilized on behalf of the customer. A customer can also have the ability to specify how the resources are to be operated when used for the customer, in order to manage the amount of energy consumption. The accounting can be performed even when the resources are shared among multiple users or entities. Various hardware components or agents can be used to provide detailed energy consumption information for those components that is associated with a particular customer. The information can be used not only for accounting and monitoring purposes, but also to make dynamic adjustments based on various changes in usage, energy consumption, or other such factors.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: March 6, 2018
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Matthew David Klein, Michael David Marr
  • Patent number: 9910823
    Abstract: A stack processor using a non-volatile, ferroelectric random access memory (F-RAM) for both code and data space. The stack processor is operative in response to as many as 64 possible instructions based upon a 16 bit word. Each of the instructions in the 16 bit word comprises 3 five bit instructions and a 16th bit which is applicable to each of the 3 five bit instructions thereby making each instruction effectively 6 bits wide.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 6, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventor: Franck Fillere
  • Patent number: 9892668
    Abstract: Embodiments disclosed herein provide systems, methods, and software for dynamically managing power consumption of a device capable of operating on battery power, or other power. In particular, the size of the viewable area of the display may be dynamically controlled to reduce the number of activated pixels to reduce power consumption. The resizing of the viewable area of a screen may also reduce the number of applications running, thereby reducing power consumption. An indication of the amount of operation time, battery indicator, and/or energy left in the battery may be presented, based at least in part on the dynamic resize of the display.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: February 13, 2018
    Assignee: AVAYA INC.
    Inventors: Jitendra Singh Wadhwa, Ramanujan S. Kashi
  • Patent number: 9876920
    Abstract: An information processing apparatus remotely controls an image forming apparatus having an operating state changeable. The information processing apparatus includes a remote operation accepting portion to accept a user operation, and a remote control portion to remotely control the image forming apparatus on the basis of a remote operation accepted by the remote operation accepting portion. The remote control portion includes a motion detecting portion to detect a motion of the user, and a state maintaining portion to control the image forming apparatus not to change the operating state while a remote-operation motion for inputting a remote operation is detected by the motion detecting portion after a communication with the image forming apparatus has been established.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: January 23, 2018
    Assignee: KONICA MINOLTA, INC.
    Inventors: Kenji Matsuhara, Junichi Hase, Kazusei Takahashi, Kazuya Anezaki, Hirokazu Kubota
  • Patent number: 9860399
    Abstract: An image forming apparatus includes: a path establishing portion to establish a communication path with a remote operation device; an active device setting portion to set the remote operation device with which the communication path is established to be an active device; a process execution portion to execute a process in accordance with a remote operation received from the active device; and a standby device setting portion to, in response to a communication path being established with another remote operation device, set another remote operation device to be a standby device. The active device setting portion includes a sequential setting portion to, in response to detection of an end state in which no remote operation is received from the active device, set the standby device to be an active device.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: January 2, 2018
    Assignee: KONICA MINOLTA, INC.
    Inventors: Ryosuke Nishimura, Yoichi Kurumasa, Yoshiyuki Tamai, Mie Kawabata, Mitsutaka Morita
  • Patent number: 9851777
    Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: December 26, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Manish Arora, Indrani Paul, Yasuko Eckert, Nuwan S. Jayasena, Srilatha Manne, Madhu Saravana Sibi Govindan, William L. Bircher
  • Patent number: 9853821
    Abstract: A CPU of an image forming apparatus controls, according to establishment of a sleep change condition, a MAC/PHY in a network unit to change the image forming apparatus from a link-up state to a link-down state. The CPU controls the image forming apparatus to change from a normal mode to a deep sleep mode. A CPU of the network unit controls, according to the change of the image forming apparatus from the normal mode to the deep sleep mode, the MAC/PHY to change the link-down state of the image forming apparatus to the link-upstate. The CPU controls the MAC/PHY to transmit a MAC address necessary for causing the image forming apparatus to participate in VLAN to a switching hub.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: December 26, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroki Ito
  • Patent number: 9846466
    Abstract: A method of and device for providing voltages to USB ports using an independent electrical channel during a device sleep mode or a power-off mode.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: December 19, 2017
    Assignee: Flextronics AP, LLC
    Inventors: Bahman Sharifipour, Rowell Gapuz, Wei Li
  • Patent number: 9838556
    Abstract: An image processing apparatus includes circuitry to authenticate a first user, a display to display an initial screen to the first user, after the first user is authenticated, and a communication device to wirelessly communicate with a portable terminal device operated by the first user to control a display of the portable terminal device to display an additional initial screen based on display contents of the initial screen. The circuitry further determines whether at least one of the image processing apparatus and the portable terminal device is not in use. Based on a determination indicating that the at least one of the image processing apparatus and the portable terminal device is not in use, the circuitry determines whether any user is present at the image processing apparatus, using a detector that detects human presence at the image processing apparatus to generate a first determination result.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 5, 2017
    Assignee: Ricoh Company, Ltd.
    Inventor: Takuroh Fujioka
  • Patent number: 9824003
    Abstract: Methods and apparatus for dynamically resizing circular buffers are described wherein circular buffers are dynamically allocated arrays from a pool of arrays. The method comprises receiving either a request to add data to a circular buffer or to remove data from a circular buffer. If the request is an addition request and the circular buffer is full, an array from the pool is allocated to the circular buffer. If, however, the request is a removal request and removal of the data creates an empty array, an array is de-allocated from the circular buffer and returned to the pool. Any arrays that are not allocated to a circular buffer may be disabled to conserve power.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: November 21, 2017
    Assignee: Imagination Technologies Limited
    Inventors: Daniel Sanders, Hugh Jackson
  • Patent number: 9785214
    Abstract: A power adapter includes a primary side and a secondary side. The primary side rectifies an alternating current voltage. The secondary side is coupled to the primary side, provides a direct current voltage of a specific voltage level to a cable. The second side includes a sensing resistor, and a compensation circuit. The compensation circuit monitors a voltage level across the sensing resistor, and injects a current into the cable based on the voltage level across the sensing resistor.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 10, 2017
    Assignee: DELL PRODUCTS, LP
    Inventors: Merle J. Wood, III, Anson Liao, Jason Yu
  • Patent number: 9787098
    Abstract: An energy storage system (ESS) includes a battery pack, a power converter, a battery management system (BMS) configured to control and monitor, in real time, the battery pack, a load power controller coupled to the battery pack and an external power source, connected to loads, and an integrated controller configured to control an operation of each component, determine an exclusive supply initiation time based on energy management schedule information including the exclusive supply initiation time, an exclusive supply termination time, and power supply timing information, control power to be supplied to the loads exclusively using power of the battery pack at the exclusive supply initiation time, and, when a current residual charge amount of the battery pack is at least one residual charge amount in the power supply timing information, control power supply to one of the loads set to correspond to the residual charge amount to be cut.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: October 10, 2017
    Assignee: Korean Polytechnic University Industry Academic Cooperation Foundation
    Inventors: Jinku Choi, Chang-Woo Lee
  • Patent number: 9760161
    Abstract: A method and a system are applied to manage a plurality of power supplies. In both the method and the system, a board management controller is applied to detect a plurality of power supplies, so as to determine whether the power supplies are normally operated. When the power supplies are operated normally, the board management controller automatically checks whether an automatic power control means is activated. When the automatic power control means is not activated, the board management controller calculates a real-time residual maximum power value according to at least one of the normal-operated power supplies. Then, the board management controller resets a system power supply value of a management engine by the real-time residual maximum power value. Finally, the board management controller orders the complex programmable logic device relieve a thermal protection means, whereby the processor's operating frequency can be maintained at a normal operating frequency.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: September 12, 2017
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Yung-Ying Chen
  • Patent number: 9720483
    Abstract: A bus system includes a bus module which performs data transfer between a master module and a slave module and a detection module which detects transfer of transmission data from the master module to the bus module. When the bus module is shifted to a power saving mode and then is returned from the power saving mode, a power control module delays release of the power saving mode until a plurality of data transfer requests is detected. Accordingly, a power saving effect can be improved in the bus system.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: August 1, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeshi Hiraoka
  • Patent number: 9715265
    Abstract: Methods and apparatus for scheduling and controlling power management activities are disclosed. An example method includes detecting, by a computing device, playback of video content at a frame rate that is greater than a predetermined threshold frame rate. The example method further includes, in response to the detection of the playback of video content at the frame rate greater than the threshold frame rate, overriding a screen dimming operation of the computing device.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: July 25, 2017
    Assignee: Google Inc.
    Inventors: Ryan Cairns, Sameer Nanda, Benson Leung, David James
  • Patent number: 9703346
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for a Unified Extensible Firmware Interface (UEFI) with durable storage to provide memory write persistence, for example, in the event of power loss. The system may include a processor to host the firmware interface which may be configured to control access to system variables in a protected region of a volatile memory. The system may also include a power management circuit to provide power to the processor and further to provide a power loss indicator to the firmware interface. The system may also include a reserve energy storage module to provide power to the processor in response to the power loss indicator. The firmware interface is further configured to copy the system variables from the volatile memory to a non-volatile memory in response to the power loss indicator.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: July 11, 2017
    Assignee: INTEL CORPORATION
    Inventors: Giri P. Mudusuru, Vincent J. Zimmer, Karunakara Kotary, Ronald N. Story, Robert C. Swanson, Isaac W. Oram
  • Patent number: 9703356
    Abstract: A method and apparatus is provided wherein a server is powered by a battery connected to a charging circuit. The voltage output by the battery is monitored and when it falls below a threshold, a determination is made that the battery is being depleted. In response to the determination, the server is brought into a reduced power consumption state or a data saving state.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: July 11, 2017
    Assignee: Google Inc.
    Inventor: Shane R. Nay
  • Patent number: 9696379
    Abstract: A method is provided for maintaining system state in semiconductor device having a first chip and a second chip, which are physically conjoined to form a stacked structure, wherein the first chip includes functional circuitry, and the second chip includes control circuitry for capturing and restoring a microarchitecture state of the functional circuitry of the first chip. The method includes initializing a system state of the semiconductor device and entering a wait state for a state capture triggering event. In response to an occurrence of a state capture triggering event, state data representing a current system state of the functional circuitry on the first chip is captured. The captured state data is transferred to the second chip through a system state I/O (input/output) interface of the second chip under control of the control circuitry on the second chip. A copy of the captured state data is then stored in a memory.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas
  • Patent number: 9696827
    Abstract: A triggering method and a wireless handheld device provided in embodiments of the present invention relate to the field of electronic technologies. The touchscreen triggering method includes: detecting an input combination that is of a click frequency and/or click intensity and is received when a touchscreen is in a locked state; and when it is detected that the input combination that is of the click frequency and/or the click intensity and is received when the touchscreen is in the locked state matches a pre-stored input combination of a click frequency and/or click intensity, wherein the pre-stored input combination of the click frequency and/or the click intensity is corresponding to an operation, executing the operation corresponding to the matched pre-stored input combination of the click frequency and/or the click intensity.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: July 4, 2017
    Assignee: HUAWEI DEVICE CO., LTD.
    Inventor: Jing Tian
  • Patent number: 9672384
    Abstract: The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: June 6, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Seiji Goto, Jun Kamada, Taiji Tamiya
  • Patent number: 9674385
    Abstract: There is provided a further saving in power consumption which is achieved by establishing an optimal transition from an ordinary operation mode to a power consumption saving mode. A mode switching management part (11c) as a mode switching part, while a communication of a managing part (11a) as a communication part to a mobile terminal (20) is being established, maintains an ordinary operation mode and when the communication of the management part (11a) to the mobile terminal (20) terminates, switches from the ordinary operation mode to a power consumption saving mode before an elapse of a specified power consumption saving time period.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: June 6, 2017
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Masaya Okuda, Tsuyoshi Nitta, Satoshi Kawakami, Yuri Moritani, Yoshitaka Matsuki
  • Patent number: 9667068
    Abstract: A system, method, and computer program product are provided for merging two or more supply rails into a merged supply rail. The method comprises receiving two or more current measurement signals associated with two or more supply rails, selecting one supply rail from the two or more supply rails, based on the current measurement signals, and enabling the selected supply rail to source current into a merged supply rail.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: May 30, 2017
    Assignee: NVIDIA Corporation
    Inventors: Samuel Richard Duell, Gabriele Gorla, Yaoshun Jia, Qi Lin, Andrew Bell
  • Patent number: 9665520
    Abstract: The disclosure provides a motherboard including a first communication interface and a switch module. The first communication interface obtains a power signal from a second communication interface of a display, the switch module obtains the power signal, and the switch module controls a first power supply to power supply for the USB communication module. The disclosure also provides a computer control system including the motherboard. The motherboard and the computer control system control the computer to save energy via a display.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: May 30, 2017
    Assignee: ScienBiziP Consulting(Shenzhen)Co., Ltd.
    Inventor: Meng-Liang Yang
  • Patent number: 9641615
    Abstract: A distributed network of storage elements (DNSE) is provided in which the physical capacity of each drive is split into a set of equal sized logical splits which are individually protected within the DNSE using separate RAID groups. To reduce restoration latency, members of the RAID groups having a member in common on a given drive are spread within the DNSE to minimize the number of sets of drives within the DNSE that have RAID members in common. By causing the splits to be protected by RAID groups, restoration of the splits may occur in parallel involving multiple drives within the DNSE. By minimizing the overlap between RAID members on various drives, failure of a given drive will not require multiple reads from another drive in the DNSE. Likewise, spare splits are distributed to enable write recovery to be performed in parallel on multiple drives within the DNSE.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 2, 2017
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Edward Robins, Kevin E. Granlund, Seema Pai, Evgeny Malkevich, Stephen Richard Ives, Roii Raz, Barak Bejerano
  • Patent number: 9625969
    Abstract: A method for controlling a power consumption in a portable terminal and a portable terminal supporting the method are provided. The method includes receiving first data from at least one device, by a main processor; transmitting second data based on the received first data to a sub processor, by the main processor; receiving the second data from the main processor, and determining whether the main processor is in a sleep state, by the sub processor; and when it is determined that the main processor is in a sleep state, maintaining the sleep state of the main processor, receiving the first data from the at least one device, and controlling the at least one device based on the received first data and second data, by the sub processor.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: April 18, 2017
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hyeongseok Kim, Byoungtack Roh, Heesub Shin, Seungyoung Jeon
  • Patent number: 9626465
    Abstract: Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: April 18, 2017
    Assignee: Imagination Technologies Limited
    Inventors: Iain Singleton, Ashish Darbari, John Alexander Osborne Netterville
  • Patent number: 9612765
    Abstract: Context aware dynamic composition of migration plans may be provided. A request for application or image migration may be received. Target machines and associated configuration may be identified. Resources and a schedule may be allocated. An appropriate tooling for each migration action may be selected. An artificial intelligence aspect of the migration planning process may continuously replan migration based on monitored changes in the context of source or target environment.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Yunwu Huang, Jinho Hwang, Dennis A. Perpetua, Jr., Maja Vukovic, Christopher C. Young
  • Patent number: 9612767
    Abstract: Context aware dynamic composition of migration plans may be provided. A request for application or image migration may be received. Target machines and associated configuration may be identified. Resources and a schedule may be allocated. An appropriate tooling for each migration action may be selected. An artificial intelligence aspect of the migration planning process may continuously replan migration based on monitored changes in the context of source or target environment.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Yunwu Huang, Jinho Hwang, Dennis A. Perpetua, Jr., Maja Vukovic, Christopher C. Young
  • Patent number: 9606797
    Abstract: In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Aniruddha S. Vaidya, Anahita Shayesteh, Dong Hyuk Woo, Saikat Saharoy, Mani Azimi
  • Patent number: 9588888
    Abstract: A memory device and method for altering a performance characteristic of a memory array to increase a rate at which the memory device writes data in response to the memory device experiencing a demand for bandwidth above a threshold. The memory device may include a memory controller and a memory array, which may include memristive memory elements. To alter a performance characteristic, for example, the memristive memory elements may be written at sub-full resistive states which have a smaller difference between high and low resistive states, and/or the memory controller may disable a subset of memory elements and/or memory cells along a bit line and/or word line of the memory array. The subset of memory elements may be re-enable in response to the demand for bandwidth falling below the threshold, and data may be moved and/or rearranged within the memory device when the subset of memory elements is re-enabled. Altering the performance characteristic may increase a rate at which the memory device writes data.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: March 7, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Janice H. Nickel, Gilberto Ribeiro
  • Patent number: 9582281
    Abstract: A method of processing data comprising performing a sequence of operation instructions with variable operand size, wherein respective size codes for different source and destination operands are obtained and registered separately from performing the sequence of operation instructions, and the sequence of operation instructions is performed using operand sizes defined by the registered size codes, the operation instructions of the sequence not themselves containing size codes.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: February 28, 2017
    Assignee: NXP USA, INC.
    Inventor: Joachim Kruecken
  • Patent number: 9569278
    Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Varghese George, Sanjeev S. Jahagirdar, Deborah T. Marr
  • Patent number: RE46456
    Abstract: An image processing device including a first control unit to control a normal operating mode during which image processing is performed, a second control unit to control an energy-saving mode during which power consumption is lower than during the normal operating mode, an interrupt request receiver connected to an external device to receive an interrupt request from the external device, interrupt factor distributors to distribute the interrupt request received by the interrupt request receiver based on whether or not the interrupt request includes a predetermined interrupt factor, interrupt request notification units to notify the second control unit as well as the first control unit of the interrupt request in accordance with distribution results from the interrupt factor distributors, and job adjustors to control transfer of a job between the first control unit and the second control unit based on notification from the interrupt request notification units.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: June 27, 2017
    Assignee: RICOH COMPANY, LTD.
    Inventor: Katsuhiko Katoh
  • Patent number: RE47050
    Abstract: In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: September 18, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fubito Igari