By Shutdown Of Only Part Of System Patents (Class 713/324)
  • Patent number: 11547263
    Abstract: A robot cleaner comprising: a cleaner body including a controller, the cleaner body having a dust container accommodation part formed therein; a wheel unit mounted in the cleaner body, the wheel unit of which driving is controlled by the controller; and a dust container detachably coupled to the dust container accommodation part, wherein a first opening and a second opening are disposed at the same height in an inner wall of the dust container accommodation part, wherein the dust container includes: an entrance and an exit, disposed side by side along the circumference of the dust container, the entrance and the exit, respectively communicating with the first opening and the second opening when the dust container is accommodated in the dust container accommodation part; and a flow separating part extending downwardly inclined along the inner circumference of the dust container.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: January 10, 2023
    Assignee: LG ELECTRONICS INC.
    Inventors: Bohyun Nam, Inbo Shim, Jihoon Sung, Sojin Park, Seunghyun Song, Sangkyu Lee, Woochan Jun
  • Patent number: 11508282
    Abstract: A display control device includes a first display capable of color display, a first controller performing reset control of the first display, and a second controller having less throughput than the first controller. The first controller executes reset control on the first display in a case of a first operation mode in which the first controller is active. The second controller executes reset control on the first display in a case of a second operation mode in which the first controller is inactive or in a case of detection of the first controller not operating normally.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 22, 2022
    Assignee: Casio Computer Co., Ltd.
    Inventor: Shuhei Uchida
  • Patent number: 11493986
    Abstract: Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.
    Type: Grant
    Filed: December 22, 2019
    Date of Patent: November 8, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Bharat Kumar Rangarajan, Rajesh Arimilli, Srinivas Turaga
  • Patent number: 11476869
    Abstract: A deep neural network (DNN) module is disclosed that can dynamically partition neuron workload to reduce power consumption. The DNN module includes neurons and a group partitioner and scheduler unit. The group partitioner and scheduler unit divides a workload for the neurons into partitions in order to maximize the number of neurons that can simultaneously process the workload. The group partitioner and scheduler unit then assigns a group of neurons to each of the partitions. The groups of neurons in the DNN module process the workload in their assigned partition to generate a partial output value. The neurons in each group can then sum their partial output values to generate a final output value for the workload. The neurons can be powered down once the groups of neurons have completed processing their assigned workload to reduce power consumption.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: October 18, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Amol Ashok Ambardekar, Boris Bobrov, Chad Balling McBride, George Petre, Kent D. Cedola, Larry Marvin Wall
  • Patent number: 11477832
    Abstract: A user equipment (UE) may support establishing an E-UTRAN New Radio-Dual Connectivity (EN-DC) connection with a telecommunication network that involves both a Long-Term Evolution (LTE) connection and a fifth generation (5G) connection. However, the EN-DC connection may drain a battery of the UE more quickly than the LTE connection would alone. Accordingly, an EN-DC switcher executing on the UE can determine when the UE should use the LTE connection alone or use the EN-DC connection, for example based on factors that may indicate when a user of the UE is less likely to perceive improved throughput or other benefits of the EN-DC connection.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: October 18, 2022
    Assignee: T-Mobile USA, Inc.
    Inventors: Ming Shan Kwok, Wafik Abdel Shahid
  • Patent number: 11467652
    Abstract: A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: October 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byungchul Jeon, Jae Min Kim, Hyunseok Kim, Junho Huh
  • Patent number: 11442519
    Abstract: The present disclosure provides various embodiments of an external power supply and methods to enhance the output power delivered by an external power supply to a power consuming load. As described in more detail below, the embodiments disclosed herein enable an external power supply to deliver a higher than maximum output power for short periods of time when ambient temperatures within the external power supply are low. As the ambient temperature increases, the embodiments disclosed herein throttle (or incrementally reduce) the output power delivered by the external power supply until the maximum output power specified for the power supply is reached. Although not strictly limited to such, the external power supply may be a Universal Serial Bus (USB)-enabled AC/DC adapter, and more specifically, a USB Power Deliver (USB-PD) AC/DC adapter, in some embodiments.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: September 13, 2022
    Assignee: Dell Products L.P.
    Inventors: Wei Cheng Yu, Geroncio O. Tan, Merle Wood, III, Chi Che Wu, Tsung-Cheng Liao, Wen-Yung Chang
  • Patent number: 11422614
    Abstract: A semiconductor device comprises a central processing device, a first logical circuit, and a serial memory interface circuit. The first logical circuit has a first scan chain in which a first scan pattern is set, is configured to suppress a leakage current when the first scan pattern for power saving is set in the first scan chain. The serial memory interface circuit is configured to acquire the first scan pattern for power saving from an external storage device. The leakage current of the first logical circuit is suppressed by transferring the first scan pattern for power saving acquired by the serial memory interface circuit to the first logical circuit and setting the first scan pattern for power saving in the first scan chain under control of the central processing device.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 23, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yasuhiro Katayama, Daisuke Katori, Tatsuo Inoue, Michitomo Yamaguchi, Naoki Oshima, Shogo Masuda
  • Patent number: 11425189
    Abstract: A power profile library includes a plurality of power profiles with each power profile having a plurality of maximum clock speeds for respective processors. The maximum clock speeds of each power profile are selected to limit a maximum amount of heat per unit time generated by the processors in combination. A developer computer system selects sections of an eventual application for a consumer device and a target intent for each section. A power profile lookup uses the target intents to determine a power profile for each section.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: August 23, 2022
    Assignee: Magic Leap, Inc.
    Inventor: Gregory Michael Link
  • Patent number: 11416395
    Abstract: A computing system having at least one bus, a plurality of different memory components, and a processing device operatively coupled with the plurality of memory components through the at least one bus. The different memory components include first memory and second memory having different memory access speeds. The computing system further includes a memory virtualizer operatively to: store an address map between first addresses used by the processing device to access memory and second addresses used to access the first memory and the second memory; monitor usages of the first memory and the second memory; adjust the address map based on the usages to improve speed of the processing device in memory access involving the first memory and the second memory; and swap data content in the first memory and the second memory according to adjustments to the address map.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Anirban Ray, Parag R. Maharana, Gurpreet Anand
  • Patent number: 11409560
    Abstract: In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Krishnamurthy Jambur Sathyanarayana, Robert Valentine, Alexander Gendler, Shmuel Zobel, Gavri Berger, Ian M. Steiner, Nikhil Gupta, Eyal Hadas, Edo Hachamo, Sumesh Subramanian
  • Patent number: 11403624
    Abstract: A system and method for layered authorization to manage a payment wallet for in-vehicle payments that include executing a vehicle connect application that allows a user to interface with a vehicle through a portable device. The vehicle connect application includes the payment wallet that is configured to be used to provide in-vehicle payments. The system and method also include determining if a plurality of layered authentication processes are successfully completed. The system and method further include allowing access and usage of the payment wallet through the vehicle connect application to complete the in-vehicle payments based on determining the successful completion of the plurality of layered authentication processes.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: August 2, 2022
    Assignee: HONDA MOTOR CO., LTD.
    Inventor: Narendran Ravi
  • Patent number: 11397999
    Abstract: Examples relate to flexible datacenters or other power loads tolerant of intermittent operation and configured to use power received behind-the-meter. A system may include a set of computing systems powered by behind-the-meter power and a datacenter control system. The datacenter control system may be configured to monitor a set of conditions that includes behind-the-meter power availability at the set of computing systems and perform a weighted analysis using the set of monitored conditions. Based on the weighted analysis, the datacenter control system may be configured to modulate operating attributes of one or more computing systems of the set of computing systems. In some examples, the datacenter control system is a remote master control system in communication with a datacenter control system of a flexible datacenter housing the set of computing systems.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: July 26, 2022
    Assignee: LANCIUM LLC
    Inventors: Michael T. McNamara, Raymond E. Cline, Jr.
  • Patent number: 11368412
    Abstract: The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: June 21, 2022
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Surendra Anubolu, Sachin Prabhakarrao Kadu, Laxminarasimha Rao Kesiraju, Mohan V. Kalkunte
  • Patent number: 11347433
    Abstract: A method for performing sudden power off recovery (SPOR) management, an associated memory device and a controller thereof, and an associated electronic device are provided. The method may include: triggering writing an expansion block; regarding a target block, setting a page count and a start page number for being processed with binary search; at least according to the page count and the start page number, performing the binary search on the target block to find a first empty page within the target block; performing page-by-page search, starting from the first empty page in a backward direction within the target block, to find the last valid page within the target block; determining an abandonment range within the expansion block according to the last valid page and the first empty page; and performing dummy programming on all expansion pages within the abandonment range.
    Type: Grant
    Filed: April 12, 2020
    Date of Patent: May 31, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Sung-Yen Hsieh
  • Patent number: 11342851
    Abstract: A power supply with a DC-DC converter and a switching converter comprises an intermediate circuit and at least one output switching regulator. The intermediate circuit has an intermediate circuit voltage, and is connected to a supply voltage via the DC-DC converter. The at least one output switching regulator is connected to the intermediate circuit, and configured to supply, on the output side, a regulated output voltage.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: May 24, 2022
    Assignee: Siemens Aktiengesellschaft
    Inventor: Christian Augesky
  • Patent number: 11314318
    Abstract: A server system and a power-saving method thereof are provided. The power-saving method includes: enabling, by a programmable logic unit in a working mode, a power-on control unit to operate according to a working power; determining, by the power-on control unit in the working mode, whether a power-saving power-off signal is received, and when the power-saving power-off signal is received, controlling, by the power-on control unit, the server system to be powered off and switched from the working mode to a soft-off mode; operating, by the programmable logic unit, according to standby power to enable, in the soft-off mode, the power-on control unit to operate according to the standby power; and turning off, by a baseboard management control unit, the programmable logic unit according to the power-saving power-off signal when the power-on control unit operates according to the standby power, to turn off the power-on control unit.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 26, 2022
    Assignee: MITAC COMPUTING TECHNOLOGY CORPORATION
    Inventors: Cheng-Chun Chen, Jing-Chin Huang, Chih-Peng Chang
  • Patent number: 11307642
    Abstract: Embodiments of this application disclose a method for managing a power supply state of a memory and a chip, where the memory includes a plurality of storage areas, and the plurality of storage areas are separately powered by an independent power supply. The method includes: determining an occupancy condition of the plurality of storage areas by a program according to allocation address information of a segment, in the program, to be stored in the plurality of storage areas; and configuring a power supply state of the plurality of storage areas according to the occupancy condition of the plurality of storage areas by the program.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: April 19, 2022
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Nan Zou
  • Patent number: 11310626
    Abstract: A solution for managing vehicles both individually and as a group of associated vehicles is provided. A vehicle node can be located on each vehicle in the group and obtain and process data from a plurality of sensors also located on the vehicle. The vehicle node can be configured to communicate, either directly or indirectly, with a group system assigned to the group using a wireless communications solution. The group system can acquire monitoring data for all of the group of associated vehicles, which can be used to manage the group of associated vehicles and/or one or more individual vehicles in the group. The group system can be located on a vehicle traveling as part of the group of associated vehicles or at a fixed location.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: April 19, 2022
    Assignee: International Electronic Machines Corp.
    Inventors: Zahid F. Mian, Bruce P. McKenney, Robert W. Foss
  • Patent number: 11301248
    Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: April 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mujibur Rahman, Timothy David Anderson, Soujanya Narnur
  • Patent number: 11301481
    Abstract: An integrated circuit may be provided with cryptocurrency mining capabilities. The integrated circuit may include control circuitry and a number of processing cores that complete a Secure Hash Algorithm 256 (SHA-256) function in parallel. Logic circuitry may be shared between multiple processing cores. Each processing core may perform sequential rounds of cryptographic hashing operations based on a hash input and message word inputs. The control circuitry may control the processing cores to complete the SHA-256 function over different search spaces. The shared logic circuitry may perform a subset of the sequential rounds for multiple processing cores. If desired, the shared logic circuitry may generate message word inputs for some of the sequential rounds across multiple processing cores. By sharing logic circuitry across cores, chip area consumption and power efficiency may be improved relative to scenarios where the cores are formed using only dedicated logic.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 12, 2022
    Assignee: 21, Inc.
    Inventors: Veerbhan Kheterpal, Daniel Firu, Nigel Drego
  • Patent number: 11294714
    Abstract: The present disclosure provides a method and an apparatus for scheduling a task, a device and a medium. The method includes: obtaining a processing task to be executed from a task queue via a main thread bound to a processor, in which the processor is configured to execute the main thread, to execute the processing task; obtaining a newly triggered processing task; in response to determining that a priority of the newly triggered processing task is greater than or equal to a priority of the processing task executed on the main thread, assigning the newly triggered processing task to a standby thread; and dispatching and assigning a processor from at least one processor through the system kernel to execute the standby thread.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: April 5, 2022
    Assignee: Apollo Intelligent Driving Technology (Beijing) Co., Ltd.
    Inventors: Chao Zhang, Zhuo Chen, Weifeng Yao, Liming Xia, Jiankang Xin, Chengliang Deng
  • Patent number: 11294572
    Abstract: A data storage system may have a number of data storage devices that each have a non-volatile memory connected to different first and second memory buffers. A data storage device can consist of a non-volatile memory where a data sector is stored. A network controller can consist of a buffer module connected to a first memory buffer and a second memory buffer that receives a data read request from the host for the data sector and evaluates the first and second memory buffers as a destination for the data sector after the data sector arrives at the buffer module. The buffer module may choose the first memory buffer and store the data sector in the first memory buffer prior to providing the data sector to the host to satisfy the data read request from the first memory buffer.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 5, 2022
    Assignee: Seagate Technology, LLC
    Inventor: Thomas V. Spencer
  • Patent number: 11289133
    Abstract: There is provided an apparatus comprising power state determination circuitry to determine a power state of a processing circuit; and control circuitry to issue a control signal relating to an item of data stored in a first storage circuitry. When the power state of the processing circuit is a predetermined state, the control circuitry issues a further control signal to a second storage circuitry to indicate whether the item of data is to be retained by the second storage circuitry.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: March 29, 2022
    Assignee: Arm Limited
    Inventor: Alex James Waugh
  • Patent number: 11284387
    Abstract: An advanced wireless communication system, and a method for use at an advanced wireless communication system are disclosed that support direct communication to provide flexible resource pool sharing. The method comprises: measuring, at a first UE, utilization of at least one resource pool of a direct communication channel associated with a configured shared region; transmitting, by the first UE and to at least one second UE, sidelink control information (SCI) identifying a selected resource pool of the at least one resource pool; and transmitting, by the first UE and to the at least one second UE, data associated with the SCI in the selected resource pool.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: March 22, 2022
    Assignee: NEC CORPORATION
    Inventors: Huei-Ming Lin, Phong Nguyen
  • Patent number: 11279128
    Abstract: An image forming apparatus includes a print head, a main control unit, a head control unit, and a head unit power supply to generate a voltage to be supplied to the head control unit. The main control unit checks whether the main control unit is normally started up. The head control unit includes an operation checker to check whether the head control unit normally operates if the main control unit is normally started up and the head control unit is supplied with a check voltage, a head power supply generator to generate a voltage to be supplied to the print head if the head control unit normally operates, and a status detector to detect a status of the print head based on the voltage supplied to the print head, and control the voltage to be supplied to the head control unit depending on the status detected by the status detector.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: March 22, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hideya Tabeta
  • Patent number: 11281473
    Abstract: Apparatuses comprising processing circuitry, a first wakeup interrupt controller connected to the processing circuitry via a first interface, and a second wakeup interrupt controller connected to the processing circuitry via a second interface, and methods of operating such apparatuses, are disclosed. Prior to the processing circuitry entering a low power state, information defining at least one wakeup event is transferred from the processing circuitry to a selected wakeup interrupt controller. Whilst the processing circuitry is in the low power state, the selected wakeup interrupt controller receives event indications. If one of these event indications is a defined wakeup event, then the processing circuitry is caused to exit the low power state.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: March 22, 2022
    Assignee: Arm Limited
    Inventor: Peter Vrabel
  • Patent number: 11281391
    Abstract: The present disclosure relates to a method, a device, and a computer program for migrating a backup system. A method for migrating a backup system includes: storing a backup copy from a first backup system to a second backup system, wherein the first backup system is used to store historical backup copies of an application system, and the second backup system is used to store future backup copies of the application system; dividing the backup copy into multiple backup extents; receiving a backup request for backing up a data object in the application system; and backing up, based on a comparison between the data object and the multiple backup extents, the data object to the second backup system to form a backup copy corresponding to the data object.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Yuting Zhang, Kaikai Jia
  • Patent number: 11269677
    Abstract: Data Center (DC) server power management monitors resource utilization and energy consumption characteristics of an individual host server, and a Virtual Machine (VM) and the applications running inside any VM of DC servers. An analysis and learning module identifies trends and opportunities to optimize DC resources by releasing the underutilized host servers. It derives power metrics to measure the energy footprint of the VMs and the associated applications. It suggests optimal destination servers to migrate each of the VMs with corresponding applications from the underutilized host servers. The power consumption of these VMs with their applications on the power-efficient destination servers is less after the migration. Powering off the underutilized freed-up servers saves energy impacting the overall power consumption of the data center.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: March 8, 2022
    Assignee: Vigyanlabs Innovations Private Limited
    Inventors: Mousumi Paul, Sanjaya Ganesh, Srivatsa Krishnaswamy, Srinivas Varadarajan
  • Patent number: 11265142
    Abstract: The disclosure concerns a method of protecting a calculation on a first number and a second number, including the steps of: generating a third number including at least the bits of the second number, the number of bits of the third number being an integer multiple of a fourth number; dividing the third number into blocks each having the size of the fourth number; successively, for each block of the third number: performing a first operation with a first operator on the contents of a first register and of a second register, and then on the obtained intermediate result and the first number, and placing the result in a third register; and for each bit of the current block, performing a second operation by submitting the content of the third register to a second operator with a function of the rank of the current bit of the third number, and then to the first operator with the content of the first or of the second register according to state “0” or “1” of said bit, and placing the result in the first or second re
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 1, 2022
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Ibrahima Diop, Yanis Linge
  • Patent number: 11249900
    Abstract: Techniques for efficiently purging non-active blocks in an NVM region of an NVM device using virtblocks are provided. In one set of embodiments, a host system can maintain, in the NVM device, a pointer entry (i.e., virtblock entry) for each allocated data block of the NVM region, where page table entries of the NVM region that refer to the allocated data block include pointers to the pointer entry, and where the pointer entry includes a pointer to the allocated data block. The host system can further determine that a subset of the allocated data blocks of the NVM region are non-active blocks and can purge the non-active blocks from the NVM device to a mass storage device, where the purging comprises updating the pointer entry for each non-active block to point to a storage location of the non-active block on the mass storage device.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: February 15, 2022
    Assignee: VMWARE, INC.
    Inventors: Xavier Deguillard, Ishan Banerjee, Julien Freche, Kiran Tati, Preeti Agarwal, Rajesh Venkatasubramanian
  • Patent number: 11237756
    Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 1, 2022
    Assignee: Toshiba Memory Coiporation
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka
  • Patent number: 11216059
    Abstract: Dynamic tiering of datacenter power for workloads is disclosed. A power capacity, including redundant power capacity and granular power capacity values within a datacenter, is determined. An outage time duration requirement for the power capacity that was determined is evaluated, where the outage time duration requirement is a number of minutes. A hold time duration requirement for the power capacity is evaluated, where the hold time duration is a number of minutes. A number of allowable occurrences of power outage for the power capacity is evaluated. A power requirement metric, based on the outage time duration requirement, the hold time duration requirement, and the number of occurrences, is calculated. A power topology within the datacenter is modified based on the power requirement metric. The modifying provides dynamic power tiering within the datacenter. The dynamic tiering includes a variable service level agreement for power within the datacenter.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: January 4, 2022
    Inventors: Clark A. Jeria Frias, Karimulla Raja Shaikh, Shankar Ramamurthy
  • Patent number: 11209939
    Abstract: Aspects of the present invention relate to user interface control of a head-worn computer.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 28, 2021
    Assignee: Mentor Acquisition One, LLC
    Inventors: Nicholas Benjamin Pelis, Sean Tomas Mostajo O'Hara, Robert Michael Lohse, Andrew Carl Heisey
  • Patent number: 11189327
    Abstract: Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Randall J. Rooney
  • Patent number: 11146721
    Abstract: In a communication system comprising a first communication apparatus and a second communication apparatus, the first communication apparatus transmits a first notification for connection processing in short-range wireless communication during an operation in a first power mode, and transmits a second notification, different from the first notification, for the connection processing in the short-range wireless communication during an operation in a second power mode in which power is saved more than in the first power mode. The second communication apparatus starts, if the first notification is received, the connection processing at an arbitrary timing, and starts, if the second notification is received, the connection processing at a timing restricted as compared to the case in which the first notification is received.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: October 12, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kaori Ikeda, Toshiyuki Takagi
  • Patent number: 11126242
    Abstract: Disclosed techniques include time-varying power management within datacenters. A set of power policies for managing power within a datacenter is obtained. The set of policies varies over time. A priority is determined for a policy within the set of policies for managing the power within the datacenter. The policy within the set varies over time. A situation within the datacenter is identified where the situation matches that described in the policy within the set of policies. A power arrangement within the datacenter is modified based on the policy within the set of policies. The power arrangement within the datacenter applies to a section of the datacenter including one or more IT racks. The modifying includes powering a set of loads within the datacenter by a specific power source, changing a topology within the datacenter, powering down a portion of the datacenter, or changing a service level agreement support level.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 21, 2021
    Assignee: Virtual Power Systems, Inc.
    Inventors: Karimulla Raja Shaikh, Clark A. Jeria Frias, Martin P Leslie
  • Patent number: 11126546
    Abstract: This application provides a garbage data scrubbing method and a device, and relates to the field of terminals, to resolve a problem that delivering a discard message in a file system transaction affects a user foreground operation. The method includes: obtaining an IO busy/idle status of a terminal at a current moment, where the IO busy/idle status includes a busy state and an idle state (S301); and if the IO busy/idle status of the terminal at the current moment is the idle state, delivering a discard message to a storage device (S302), where the discard message includes an initial address and a size of to-be-scrubbed physical space in the storage device, and the discard message is used to unbind a mapping relationship between a physical address of the to-be-scrubbed physical space and a corresponding logical address.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 21, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chao Yu, Hao Chen, Bifeng Tong, Chengliang Zheng, Xiyu Zhou
  • Patent number: 11126254
    Abstract: Systems and methods, according to the present disclosure, determines a duration of the current queue of commands in the controller, executes all full commands capable of being executed prior to the beginning of a low power cycle. Commands that are not executed may be re-fetched when the device enters a power mode. In an alternate embodiment, a portion of a command that is executable prior to the beginning of a low power cycle is executed, with the un-executed portion of the command being stored on the device, in an “always on” or AON memory. This un-executed portion is fetched and executed when the device enters the power mode.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: September 21, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 11126247
    Abstract: A method for updating a power mode parameter combination, includes identifying a current hardware combination of a client host; loading and executing a current application program; loading a default profile according to the current application program to update a current power mode parameter combination of the current hardware combination; receiving a user-defined parameter combination to update the current power mode parameter combination of the current hardware combination; correlating the current application program, the current hardware combination and the updated current power mode parameter combination to generate a current profile as an updated default profile; and transmitting the current profile to a server as a candidate profile.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 21, 2021
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Ching-Hung Chao, Hou-Yuan Lin, Mou-Ming Ma, Chun-Kun Lan, Po-Chang Tseng, Hung-Yen Chen, Chun-Yu Wang, Yih-Neng Lin
  • Patent number: 11112849
    Abstract: A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 7, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Partha Sarathy Murali, Suryanarayana Varma Nallaparaju, Kriyangbhai Vinodbhai Shah, Venkata Rao Gunturu, Subba Reddy Kallam, Mani Kumar Kothamasu
  • Patent number: 11115930
    Abstract: A controlling method for an electronic device is provided, including the following steps: receiving a feedback signal; determining a signal strength value of the feedback signal; obtaining a first threshold value and a second threshold value; comparing the signal strength value with the first threshold value and the second threshold value, where the first threshold value is less than the second threshold value; controlling a screen to operate in a first mode when the signal strength value is greater than the second threshold value; comparing the signal strength value with a predetermined value when the signal strength value is greater than the first threshold value but not greater than the second threshold value, and adjusting the first threshold value to be the signal strength value when the signal strength value is greater than the predetermined value.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 7, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventor: Kun-Hsin Chiang
  • Patent number: 11094488
    Abstract: According to one embodiment, a port connection circuit includes a controller includes a first port configured to selectively switch to an input state or to an output state, a second port configured to output a switch control signal, a third port configured to detect an event, an input contact connected to or disconnected from an output contact of an external connector and connected to the third port, a switch connected between the input contact and the first port, and a switch control circuit configured to close or open the switch based on a voltage of the input contact.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: August 17, 2021
    Assignee: TOSHIBA CLIENT SOLUTIONS CO., LTD.
    Inventor: Motoaki Ando
  • Patent number: 11086388
    Abstract: A memory controller, an application processor, and a method of operating the memory controller can control performance and power consumption of an input/output device. The method includes allowing the memory device to enter a power down mode after an idle state is maintained for a first time period corresponding to a first setting value which is currently set, allowing the memory device to enter from the power down mode into an active state when access to the memory device occurs, determining a maintenance time of the power down mode to change the first setting value to a second setting value, based on a result obtained by monitoring a driving pattern of the memory device, and when the idle state is maintained for a second time period different from the first time period, allowing the memory device to enter the power down mode, based on the second setting value.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 10, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Joon Kang, Tae-Hun Kim
  • Patent number: 11048438
    Abstract: In some aspects, the present disclosure provides a method for managing data communication rates of a memory device. The method includes receiving an input/output (I/O) operation to be performed by the memory device, detecting a temperature of the memory device, and determining whether the detected temperature satisfies a threshold condition. The threshold condition is satisfied if the detected temperature is above a first temperature threshold or below a second temperature threshold. If the threshold condition is satisfied, selecting a gear from a plurality of gears based on a ranking of the plurality of gears at the detected temperature, wherein each gear of the plurality of gears correspond to a respective one of a plurality of data rates used by the memory device for performing I/O operations, and serving, to the memory device, the I/O operation with an indication to perform the I/O operation using the selected gear.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 29, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Madhu Yashwanth Boenapalli, Sai Praneeth Sreeram, Surendra Paravada, Venu Madhav Mokkapati
  • Patent number: 11048319
    Abstract: A data processing device communicating with a memory device via a memory interface includes: at least one data processor configured to generate first data; a data converter configured to generate second data written to the memory device from the first data; and a controller configured to enable the data converter to generate the second data having a size less than that of the first data.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Gu Kang, Se-Hyoung Kim
  • Patent number: 11036270
    Abstract: Systems and methods for providing power to a home entertainment integrated circuit chip are disclosed. The home entertainment integrated circuit chip can operate in at least two power control modes: “power on” mode and “standby” mode. In power on mode, power is supplied to IC core module from a main power supply. The power supplied to the IC core module is isolated from power supplied to a standby island. Accordingly, during the second mode power is applied only to the standby power island through a regulator internal to the integrated circuit chip. The regulator is coupled to an external peripheral input/output (I/O) power supply that is independent of the main power supply.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: June 15, 2021
    Assignee: Entropic Communications, LLC
    Inventor: Branislav Petrovic
  • Patent number: 11039004
    Abstract: A processor-based personal electronic device (such as a smartphone) is programmed to automatically respond to data sent by various sensors from which the user's activity may be inferred. One or more alarms on the device may be temporarily disabled when sensor data indicates that the user is asleep. One or more of the sensors may be worn by the user and remote from the device. A wireless communication link may be used by the device to obtain remote sensor data. Data from on-board sensors in the device—such as motion sensors, location sensors, ambient light sensors, and the like—may also be used to deduce the user's current activity. User data (such as calendar entries) may also be used to determine likely user activity and set alarms accordingly. Biometric data from a second, nearby person may also be used to automatically select certain alarm modes on a first person's device.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: June 15, 2021
    Assignee: Apple Inc.
    Inventors: Shannon M. Ma, Devrim Varoglu, Mohammad Bidabadi, Paolo D. Concha
  • Patent number: 11036273
    Abstract: There are provided a memory system and an operating method thereof. A memory system includes a plurality of memory devices for performing operations, a power consumption profile table storing section for storing a power consumption profile table of power consumption values with respect to times when the memory devices perform the operations, and a processor for deriving a total power consumption value for the plurality of memory devices based on the power consumption profile table, and determining whether to release or hold a queued command based on the derived total power consumption value.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Dong Sop Lee, In Jae Yoo, Dong Yeob Chun
  • Patent number: 11032772
    Abstract: A wireless communication device (UE) may include a paging subsystem that performs paging-monitoring as part of wireless communications of the wireless communication device. The UE may place wireless communication system resources not required during paging-monitoring into either a low-power state or a power-down state, and those system resources may remain in one of those respective states during paging-monitoring. The wireless communication system resources not required during the paging-monitoring may include at least a wireless communications protocol stack used during the wireless communications of the UE, and at least system resources used for performing uplink related tasks independently of wireless communication system resources used for performing downlink related tasks.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: June 8, 2021
    Assignee: Apple Inc.
    Inventors: Moustafa M. Elsayed, Tarik Tabet