Abstract: A provenance method, system, and non-transitory computer readable medium for a plurality of eidetic systems having logs, include crawling the logs of each node of a plurality of nodes of the eidetic systems to cluster segments across the logs of temporally correlated events into clustered segments and analyzing the correlated segments to interleave an order of processes in the logs and assign a probability to the order of the processes occurring.

Abstract: The present invention provides a control method of a receiver. The control method includes the steps of: when the receiver enters a sleep/standby mode, continually detecting an auxiliary signal from an auxiliary channel to generate a detection result; and if the detection result indicates that the auxiliary signal has a preamble or a specific pattern, generating a wake-up control signal to wake up the receiver before successfully receiving the auxiliary signal having a wake-up command.

Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. In a first phase of a plurality of phases in each assignment period of an assignment stage after a synchronization stage, the first slave device is configured to control the alert handshake control line to a second voltage level via the alert handshake pin. In the phases of each of the assignment periods except for the first phase, a first slave device of the slave devices is configured to control the alert handshake control line to communicate with the slave devices via the alert handshake pin. The first phase corresponds to a first slave device.

Abstract: A system synchronization method includes: connecting synchronization modules of a plurality of devices together through a synchronization bus. The synchronization modules include a signal generation module, a switch control module, a synchronization bus monitoring module, and a switch S1. A signal output terminal of the signal generation module is connected to a first terminal of the switch S1, and a timing overflow terminal of the signal generation module is connected to the switch control module configured to control the switch S1. The switch control module is connected to the synchronization bus monitoring module. A second terminal of the switch S1 is connected to the switch control module and the synchronization bus monitoring module. The system synchronization method has the advantages of simple structure, low cost, high reliability, and good practicability.

Abstract: A computer-implemented method according to one embodiment includes compiling log data from all nodes of a cluster, retrieving a timestamp table stored within the cluster, optimizing the timestamp table, and adjusting the log data from all the nodes of a cluster, utilizing the timestamp table.

Abstract: A content production management system within a distributed studio environment includes a command interface module and a command queue management module. The command interface module is configured to render a user interface for a set of content production entities associated with a set of content production volumes within the distributed studio environment. The command queue management module, upon execution of software instructions, is configured to perform the operations of receiving, from the command interface module, a command targeting a target content production entity, assigning a synchronized execution time to the command, enqueueing the command into a command queue associated with the target content production entity according to the synchronized execution time, and enabling the target content production entity to execute the command from the command queue according to the synchronized execution time.

Abstract: An electrical system is provided. The electrical system comprises a first phase lock circuit embedded within a first chip for receiving a first periodic signal having a first frequency. The electrical system comprises a first buffering circuit embedded within the first chip for receiving a second periodic signal having the first frequency, wherein the first buffering circuit is configured to provide a third periodic signal having the first frequency to an output terminal of the first chip.

Abstract: A parallel process apparatus connecting electronic controllers via buses includes: a process request acceptance section that accepts process requests to the electronic controllers; and a process execution section that, while multiple process requests are simultaneously accepted, arbitrates the multiple process requests being accepted, and parallelizes multiple processes in accordance with the multiple process requests.

Abstract: Enforcing memory operand types using protection keys is generally described herein. A processor system to provide sandbox execution support for protection key rights attacks includes a processor core to execute a task associated with an untrusted application and execute the task using a designated page of a memory; and a memory management unit to designate the page of the memory to support execution of the untrusted application.

Abstract: An electronic device comprises a first processor, a second processor and a communication interface. The first processor operates according to a first clock, and comprises a first time-stamp counter to count the first clock to obtain a first count value. The second processor operates according to a second clock, and comprises a second time-stamp counter to count the second clock to obtain a second count value. The communication interface is coupled between the first processor and the second processor. The first processor periodically sends the first count value to the second processor through the communication interface. When the second processor receives the first count value, the second processor adds a preset deviation value to the first count value to obtain a synchronization value, resets the second count value, and the sum of the synchronization value and the second count value is read by the second processor.

Abstract: A synchronizing system including a generation unit for generating a synchronizing pulse from data of an independent clock, the synchronizing pulse being generated in a periodic manner, transmission links to transmit the synchronizing pulse to all the computation units, and in each of the computation units, a control element to compare the synchronizing pulse that has been received to a pulse generated by an internal clock of the computation unit and to detect a compliance or a lack of compliance, a scheduler of each of the computation units activating a sequence of partitions when the synchronizing pulse is received, and this only if the control element has detected a compliance. The synchronizing system is configured to synchronize the computation units in a reliable and accurate manner and to increase the operating safety of these computation units.

Abstract: A distributed database processing system for a database composed of data records organized into tables which processes unique index atoms consistently and concurrently. Each attempt to insert a new key value into such a unique index atom in any given node is routed to a unique index atom chairman for processing. The chairman determines whether the request will be granted. If the request is not granted, the requesting unique index atom continues to try to submit the insert. If the request is granted, the requesting unique index atom modifies the content thereof and broadcasts a replicated given unique index atom all other nodes that contain the replicated unique index atom.

Abstract: In the conventional semiconductor device, it is impossible for two CPUs to operate memories to be debugged at synchronous timings. According to one embodiment, the operation verifying program analyzes the operation verifying command received by the first semiconductor device 10 from the external device 31 by its own device (S32), transfers the operation verifying command to the second semiconductor device 20 (S31, S41), also analyzes the operation verifying command in the second semiconductor device 20 (S42), outputs the trigger signal (S34, S44) to the first semiconductor device 10 from the second semiconductor device 20 based on the result of the analysis, writes the memory setting values included in the operation verifying command to the memories in the respective semiconductor device (S35, S45) based on the trigger signal, and restarts the device operation based on the written memory setting values.

Abstract: A method for timing procedures in a microscope system, which has a plurality of microscope modules configured to carry out various processes, provision is made for a clock signal to be provided to all microscope modules by a central clock generator and for the clock signal to be modulated by a clock modulation circuit in order to produce a defined clock-pulse number. The microscope modules define a start time for carrying out a process by way of the clock-pulse number, carrying out the process as soon as the clock-pulse number is reached. Moreover, a corresponding microscope system is described.

Abstract: Methods and computer-readable media are disclosed herein for generating asynchronous runtime compatible applications from non-asynchronous applications. In embodiments, source code for the application that is not compatible with asynchronous processing is examined. The source code is parsed in order to identify unsafe functions that will cause failures of the application when processed in an asynchronous runtime. The source code corresponding to those unsafe functions is modified by adding asynchronous functions and commands to the source code and restructuring the source code. The modified source code may then be provided to an asynchronous runtime environment as the application is now compatible with asynchronous processing.

Abstract: There is provided a technique of time delivery in a computing system comprising a system call interface (SCI) located in a kernel space and operatively connected to a time client located in a user space. The technique comprises: using a time agent component located in the user space to measure data indicative of delay in a system time delivery and to derive therefrom a system time delivery error TES2C; using TES2C to enable correction of system time; and sending by the SCI the corrected system time in response to a “Read Clock RT” (RCRT) call received from the time client. The method can further comprise: measuring data indicative of delays in the system time delivery for RCRT calls with different priorities; and in response to a system time request received from the time client, providing the time client with system time corrected per TES2C corresponding to the recognized priority thereof.

Abstract: Methods and apparatus for synchronization of time between independently operable processors. Time synchronization between independently operable processors is complicated by a variety of factors. For example, neither independently operable processor controls the other processor's task scheduling, power, or clocking. In one exemplary embodiment, a processor can initiates a time synchronization process by disabling power state machines and transacting timestamps for a commonly observed event. In one such embodiment, timestamps may be transferred via inter-processor communication (IPC) mechanisms (e.g., transfer descriptors (TDs), and completion descriptors (CDs)). Both processors may thereafter coordinate in time synchronization efforts (e.g., speeding up or slowing down their respective clocks, etc.).

Abstract: A computer comprising one or more processors and memory may implement an atomic compare and swap (CAS) operation on multiple data elements. Each data element has a corresponding descriptor which includes a new value and a reference to a controlling descriptor for the CAS operation. The controlling descriptor includes a status value which indicates whether the CAS operation is in progress or has completed. The operation first allocates memory locations of the data elements by writing addresses of respective descriptors to the memory locations using CAS instructions. The operation then writes successful status to the status value of the controlling descriptor to indicate that the respective memory locations are no longer allocated. The operation then returns an indicator of successful completion without atomically updating the memory locations with the new values. Extensions are further described to implement CAS operations in non-volatile random access memories.

Abstract: A signal driver includes a first driver, a second driver, an on-timing control circuit, and an off-timing control circuit. The first driver is configured to generate a first driving pulse signal by inverting and driving an input pulse signal. The second driver is configured to generate a second driving pulse signal by inverting and driving the first driving pulse signal. The on-timing control circuit is configured to pull-up drive or pull-down drive the first driving pulse signal based on a first on-timing control signal, a second on-timing control signal, and the input pulse signal. The off-timing control circuit is configured to pull-up drive or pull-down drive the second driving pulse signal based on a first off-timing control signal, a second off-timing control signal, and the first driving pulse signal.

Abstract: A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.

Abstract: A signal generation circuit generates a first synchronization signal by delaying a first input signal in synchronization with a first division clock signal, and generates a second synchronization signal by delaying a second input signal in synchronization with a second division clock signal. The signal generation circuit adjusts pulse widths of the first and second synchronization signals based on an on-control signal and an off-control signal. The signal generation circuit includes a retiming circuit configured to generate an output signal by retiming a preliminary output signal, generated from the first and second synchronization signals, based on the first and second division clock signals.

Abstract: A management apparatus transmits information of a manager control task to each agent service, manages an execution result of processing executed in each network device, which is a processing target, for each of the sub-tasks generated at each agent service based on the manager control task, and transmits a response indicating whether execution of a sub-task is permitted based on an inquiry from each agent service to control the number of sub-tasks executed in parallel in the same time slot.

Abstract: An information terminal is used with a wrist information device. The information terminal includes a position measurement module, communication circuit, a memory, and a processor. The position measurement module obtains position information. The communication circuit communicates with the wrist information device. The processor obtains information about an operation of a clock function input into the wrist information device during establishment of connection of the communication, obtains the position information from the position measurement module, and stores, in the memory, the position information and the information about the operation of the clock function in association with each other.

Abstract: A computer comprising one or more processors and memory may implement an atomic compare and swap (CAS) operation on multiple data elements. Each data element has a corresponding descriptor which includes a new value and a reference to a controlling descriptor for the CAS operation. The controlling descriptor includes a status value which indicates whether the CAS operation is in progress or has completed. The operation first allocates memory locations of the data elements by writing addresses of respective descriptors to the memory locations using CAS instructions. The operation then writes successful status to the status value of the controlling descriptor to indicate that the respective memory locations are no longer allocated. The operation then returns an indicator of successful completion without atomically updating the memory locations with the new values. Extensions are further described to implement CAS operations in non-volatile random access memories.

Abstract: The invention relates to a computer implemented method of generating multiple programs to deliver a computerised function, each program to be executed in a processing unit of a computer comprising a plurality of processing units each having instruction storage for holding a local program, an execution unit for executing the local program and data storage for holding data, a switching fabric connected to an output interface of each processing unit and connectable to an input interface of each processing unit by switching circuitry controllable by each processing unit, and a synchronisation module operable to generate a synchronisation signal, the method comprising: generating a local program for each processing unit comprising a sequence of executable instructions; determining for each processing unit a relative time of execution of instructions of each local program whereby a local program allocated to one processing unit is scheduled to execute with a predetermined delay relative to a synchronisation signal

Abstract: Technology for an electronic circuit is described. The electronic circuit can include one or more timed general-purpose input/output (GPIO) pins and a controller. The controller can receive touch sensor data pulses from a plurality of touch sensor integrated circuits (ICs) that are each communicatively coupled to the electronic circuit. A first touch sensor data pulse received from a first touch sensor IC in the plurality of touch sensor ICs can be time synchronized with a second touch sensor data pulse received from a second touch sensor IC in the plurality of touch sensor ICs using the one or more timed GPIO pins. The controller can combine the touch sensor data pulses received time synchronously from each of the plurality of touch sensor ICs to produce joint touch sensor data. The controller can perform joint processing of the joint touch sensor data.

Abstract: A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.

Abstract: An information processing apparatus includes: a processor performs a scheduling process of scheduling a job for nodes and including: calculating, when one node executes a first job, a job execution end time when execution of the first job is completed by referring an execution history in which an execution time of a job is recorded; acquiring, from a load management node that manages a load of a metadata-process execution node which performing metadata processing to access metadata of a file among the nodes, the load of the metadata-process execution node at the job execution end time; and generating, when the load is equal to or more than a threshold, schedule data to cause a staging execution node which performs the metadata processing produced by staging, at the job execution end time, the metadata processing based on staging to a file having an execution result of the first job.

Abstract: An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first plurality of logic tiles generates the tile clock using (i) the first external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the first plurality, and a second logic tile to receive a second external clock signal wherein each logic tile of a second plurality of logic tiles generates the tile clock using (i) the second external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the second plurality, wherein the first and second external clock signals are the same clock signals.

Abstract: Device assisted services (DAS) install techniques are provided in accordance with some embodiments. In some embodiments, DAS install techniques for providing service processors for mobile devices are provided. In some embodiments, DAS install techniques for downloading/installing new and/or updated service processors for mobile devices are provided. In some embodiments, DAS install techniques for providing verified service processors for mobile devices are provided. In some embodiments, DAS install techniques for providing secured service processors for mobile devices are provided.

Abstract: The invention is adapted to acquire more useful log data. A master device (4) includes a timer element (45), adapted to acquire a moment; an instruction sending element (421), adapted to synchronize a moment measured by a slave timer element (14) of slave devices (1-3) with a moment acquired by the timer element (45) according to a time synchronization instruction containing moment information corresponding to the moment acquired by the timer element (45); and a slave log receiving element (423), adapted to receive slave logs (131).

Abstract: In one example in accordance with the present disclosure, a method may include performing a transactional operation such that if one step of the transactional operation is performed, each other step of the transactional operation is performed. The transactional operation may include making a first copy, stored in a first persistent memory, of a next ticket number stored in a second persistent memory and updating the next ticket number in the second persistent memory. The method may also include determining when to serve a first thread based on the first copy of the next ticket number.

Abstract: A system for controlling the advertising machine includes a standby control unit, an application processing unit and a power source unit. The application processing unit is configured to control an operation of the advertising machine. The power source unit is configured to provide power to the standby control unit, and provide power to the application processing unit under the control of the standby control unit. The standby control unit is configured to control a standby period and an operating period of the advertising machine according to a standby scheme, wherein during the standby period of the advertising machine, the power source unit is controlled to stop providing power to the application processing unit, and during the operating period of the advertising machine, the power source unit is controlled to provide power to the application processing unit.

Abstract: Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.

Abstract: An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first plurality of logic tiles generates the tile clock using (i) the first external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the first plurality, and a second logic tile to receive a second external clock signal wherein each logic tile of a second plurality of logic tiles generates the tile clock using (i) the second external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the second plurality, wherein the first and second external clock signals are the same clock signals.

Abstract: A method and an apparatus for implementing a mobile broadband device service. The method includes the following steps: obtaining, service information of a mobile broadband device according to a rule set on the host or by calling an application programming interface of a Web server on the mobile broadband device; and when it is necessary to use a corresponding function of the host for implementing a mobile broadband device service corresponding to the service information, executing, the corresponding function of the host by calling an application programming interface provided by an operating system of the host, to implement the mobile broadband device service. In the embodiments of the present invention limitations when the mobile broadband device is managed in the Web manner are reduced, and a capability of managing the mobile broadband device is improved.

Abstract: A parallel computing control apparatus determines, among a plurality of nodes, relay nodes located on a path from a first node allocated to a job to a second node. The parallel computing control apparatus obtains an index value indicating a use state of resources in the relay nodes. The parallel computing control apparatus calculates an estimated value of a transfer period taken to transfer data on the job from the first node to the second node, on the basis of the index value and the memory usage of the job.

Abstract: Embodiments include systems and methods for providing reliable and precise sample alignment across different clock domains. Some embodiments operate in context of microprocessor power management circuits seeking correlated measurements of voltage droop (VD) and phase delay (PD). For example, a rolling code is generated for each of multiple second clock domain sample times (CDSTs). VD and the rolling code are both sampled according to a first clock domain to generate VD samples and corresponding VCode samples for each of multiple first CDSTs. PD can be sampled according to the second clock domain to generate PD samples for each of the second CDSTs, each associated with the rolling code for its second CDST. For any first CDST, the VD sample for the first CDST can be aligned with a PD sample for a coinciding second CDST by identifying matching associated rolling codes.

Abstract: A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip includes a first synchronization controller and a first counter controller that allows a counter in the master chip to perform counting synchronously with a clock pulse in response to a synchronization control signal from the first synchronization controller. Another semiconductor integrated circuit as a slave chip includes a second synchronization controller that receives the synchronization control signal from the master chip, and a second counter controller that allows a counter in the slave chip to perform counting synchronously with the clock pulse in response to the synchronization control signal received. Each of the first and second counter controllers allows the counter to stop counting if the synchronization control signal is not supplied at the time point that a count value of the counter has reached a predetermined value.

Abstract: A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.

Abstract: By causing information processing apparatuses belonging to a same group to be in a same state and transmitting operation information received from an input unit to the information processing apparatuses belonging to the same group simultaneously or approximately simultaneously, the operations of the information processing apparatuses belonging to the same group are synchronized with each other, and operation results received from the synchronized information processing apparatuses belonging to the same group are output by an output unit. In this way, the plurality of grouped information processing apparatuses can be simultaneously operated.

Abstract: Systems, methods, and articles of manufacture provide for fault-tolerant timers, such as in an online gaming environment. Fault-tolerant timers may, for example, be provided by implementing specific methods for expiring a timer, such as by utilizing broadcast notices and distributed locks.

Abstract: Exemplary aspects are directed toward resolving fault suppression in hardware, which at the same time does not incur a performance hit. For example, when multiple instructions are executing simultaneously, a mask can specify which elements need not be executed. If the mask is disabled, those elements do not need to be executed. A determination is then made as to whether a fault happens in one of the elements that have been disabled. If there is a fault in one of the elements that has been disabled, a state machine re-fetches the instructions in a special mode. More specifically, the state machine determines if the fault is on a disabled element, and if the fault is on a disabled element, then the state machine specifies that the fault should be ignored. If during the first execution there was no mask, if there is an error present during execution, then the element is re-run with the mask to see if the error is a “real” fault.

Abstract: One or more techniques and/or systems are provided for assigning power management classifications to a process, transitioning a computing environment into a connected standby state based upon power management classifications assigned to processes, and transitioning the computing environment from the connected standby state to an execution state. That is, power management classifications, such as exempt, throttle, and/or suspend, may be assigned to processes based upon various factors, such as whether a process provides desired functionality and/or whether the process provides functionality relied upon for basic operation of the computing environment. In this way, the computing environment may be transitioned into a low power connected standby state that may continue executing desired functionality, while reducing power consumption by suspending and/or throttling other functionality.

Abstract: Systems and methods for generating DMA transaction trace records are described. One example system includes a controller that includes a trace module. The trace module receives transfer requests for direct memory access channels, receives timestamps indicative of a transfer request time, generates trace records, wherein each trace record includes a respective timestamp indicative of a transfer request time, generates save commands, and delivers the trace records and the save commands as outputs. The system includes a storage module for saving trace records.

Abstract: Disclosed are various embodiments for executing multiple applications in a single virtual machine. The classes of an application executing in the virtual machine are traversed to identify non-sharable static fields. Upon identifying a non-sharable static field, mapping data is created that corresponds to the non-sharable static field. During another traversal of the classes of the application, access to the identified non-sharable static field is translated into an access to the mapping data that is associated with the non-sharable static field.

Abstract: A method of operating a computer system in communications, via a communication network, with a server comprising an image of a kernel of a minimal operating system and an image of an associated file system for the computer system includes loading, via the communication network, the kernel image from the server to the computer system in accordance with a network transfer protocol interface, and loading, via the communication network, the file system image from the server to the computer system in accordance with the same network transfer protocol interface used to load the kernel image, wherein the loading of the kernel image from the server to the computer system is launched before the loading of the file system image from the server to the computer system is completed, and wherein the loading of the file system image from the server to the computer system is launched before the loading of the kernel image from the server to the computer system is completed.

Abstract: System and method for determining the updating time by a server presumed to have a correct time and a client needing a correct time. The server can first transmit an unencrypted signal, which may be signed or unsigned. The server can then later encrypt or sign the same packet it transmitted with a private key and transmit it to the client. After the client receives the unencrypted packet, the client can compute a time difference. However the client doesn't update its time until a follow-up packet is received from the server. If encrypted, the packet is decoded with the server's public key, and the decoded packet is shown identical to the received packet and that the identification bits are the same.

Abstract: An operating system or other software resident on an electronic processing device employs aggregated timestamps. In this way timestamps can be generated and compared to one another without the need for a real-time clock with a power backup. Aggregated time includes the last known time that the device synchronized its clock with a reference time available over a network. Aggregated time also includes a relative time value which in part accumulates using a session clock whenever the device is powered-up. When network time becomes available the operating system or other software will use this information to fix up the already generated aggregated timestamps. A comparison of timestamps will most of the time be resolved for stamps generated on the same device and will generally be resolved by comparing time frames when the timestamps being compared are generated by different devices.

Abstract: A method and system for providing information management of mobile device data provides a user interface to permit a user of an information management system to define information management policies for the mobile device, receives definitions of the information management policies from the provided interface, and sends data from the mobile device to the information management system in accordance with the information management policies. In some examples, the system sends information identifying the user and the mobile device to the information management system, and/or sends the information management policies defined from the interface to the information management system.