Synchronization Of Plural Processors Patents (Class 713/375)
  • Patent number: 10841414
    Abstract: An information terminal is used with a wrist information device. The information terminal includes a position measurement module, communication circuit, a memory, and a processor. The position measurement module obtains position information. The communication circuit communicates with the wrist information device. The processor obtains information about an operation of a clock function input into the wrist information device during establishment of connection of the communication, obtains the position information from the position measurement module, and stores, in the memory, the position information and the information about the operation of the clock function in association with each other.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: November 17, 2020
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Hirofumi Nagareda
  • Patent number: 10824424
    Abstract: A computer comprising one or more processors and memory may implement an atomic compare and swap (CAS) operation on multiple data elements. Each data element has a corresponding descriptor which includes a new value and a reference to a controlling descriptor for the CAS operation. The controlling descriptor includes a status value which indicates whether the CAS operation is in progress or has completed. The operation first allocates memory locations of the data elements by writing addresses of respective descriptors to the memory locations using CAS instructions. The operation then writes successful status to the status value of the controlling descriptor to indicate that the respective memory locations are no longer allocated. The operation then returns an indicator of successful completion without atomically updating the memory locations with the new values. Extensions are further described to implement CAS operations in non-volatile random access memories.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: November 3, 2020
    Assignee: Oracle International Corporation
    Inventors: Virendra J. Marathe, Alex Kogan, Mihail-Igor Zablotchi
  • Patent number: 10802536
    Abstract: The invention relates to a computer implemented method of generating multiple programs to deliver a computerised function, each program to be executed in a processing unit of a computer comprising a plurality of processing units each having instruction storage for holding a local program, an execution unit for executing the local program and data storage for holding data, a switching fabric connected to an output interface of each processing unit and connectable to an input interface of each processing unit by switching circuitry controllable by each processing unit, and a synchronisation module operable to generate a synchronisation signal, the method comprising: generating a local program for each processing unit comprising a sequence of executable instructions; determining for each processing unit a relative time of execution of instructions of each local program whereby a local program allocated to one processing unit is scheduled to execute with a predetermined delay relative to a synchronisation signal
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: October 13, 2020
    Assignee: Graphcore Limited
    Inventors: Simon Christian Knowles, Daniel John Pelham Wilkinson, Richard Luke Southwell Osborne, Alan Graham Alexander, Stephen Felix, Jonathan Mangnall, David Lacey
  • Patent number: 10761641
    Abstract: Technology for an electronic circuit is described. The electronic circuit can include one or more timed general-purpose input/output (GPIO) pins and a controller. The controller can receive touch sensor data pulses from a plurality of touch sensor integrated circuits (ICs) that are each communicatively coupled to the electronic circuit. A first touch sensor data pulse received from a first touch sensor IC in the plurality of touch sensor ICs can be time synchronized with a second touch sensor data pulse received from a second touch sensor IC in the plurality of touch sensor ICs using the one or more timed GPIO pins. The controller can combine the touch sensor data pulses received time synchronously from each of the plurality of touch sensor ICs to produce joint touch sensor data. The controller can perform joint processing of the joint touch sensor data.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 1, 2020
    Assignee: INTEL CORPORATION
    Inventors: Arvind Kumar, Antonio Cheng, Chai Huat Gan
  • Patent number: 10606307
    Abstract: A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: March 31, 2020
    Assignee: ARM Finance Overseas Limited
    Inventors: Kesava Reddy Talupuru, Sanjai B. Athi
  • Patent number: 10599472
    Abstract: An information processing apparatus includes: a processor performs a scheduling process of scheduling a job for nodes and including: calculating, when one node executes a first job, a job execution end time when execution of the first job is completed by referring an execution history in which an execution time of a job is recorded; acquiring, from a load management node that manages a load of a metadata-process execution node which performing metadata processing to access metadata of a file among the nodes, the load of the metadata-process execution node at the job execution end time; and generating, when the load is equal to or more than a threshold, schedule data to cause a staging execution node which performs the metadata processing produced by staging, at the job execution end time, the metadata processing based on staging to a file having an execution result of the first job.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: March 24, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Atsushi Nukariya, Tsuyoshi Hashimoto
  • Patent number: 10587271
    Abstract: An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first plurality of logic tiles generates the tile clock using (i) the first external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the first plurality, and a second logic tile to receive a second external clock signal wherein each logic tile of a second plurality of logic tiles generates the tile clock using (i) the second external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the second plurality, wherein the first and second external clock signals are the same clock signals.
    Type: Grant
    Filed: July 6, 2019
    Date of Patent: March 10, 2020
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Cheng C. Wang, Nitish U. Natu
  • Patent number: 10582375
    Abstract: Device assisted services (DAS) install techniques are provided in accordance with some embodiments. In some embodiments, DAS install techniques for providing service processors for mobile devices are provided. In some embodiments, DAS install techniques for downloading/installing new and/or updated service processors for mobile devices are provided. In some embodiments, DAS install techniques for providing verified service processors for mobile devices are provided. In some embodiments, DAS install techniques for providing secured service processors for mobile devices are provided.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: March 3, 2020
    Assignee: Headwater Research LLC
    Inventor: Gregory G. Raleigh
  • Patent number: 10523761
    Abstract: The invention is adapted to acquire more useful log data. A master device (4) includes a timer element (45), adapted to acquire a moment; an instruction sending element (421), adapted to synchronize a moment measured by a slave timer element (14) of slave devices (1-3) with a moment acquired by the timer element (45) according to a time synchronization instruction containing moment information corresponding to the moment acquired by the timer element (45); and a slave log receiving element (423), adapted to receive slave logs (131).
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: December 31, 2019
    Assignee: OMRON Corporation
    Inventors: Shigenori Sawada, Taishi Kawaguchi, Yasushi Yamawaki, Kojiro Baba
  • Patent number: 10423464
    Abstract: In one example in accordance with the present disclosure, a method may include performing a transactional operation such that if one step of the transactional operation is performed, each other step of the transactional operation is performed. The transactional operation may include making a first copy, stored in a first persistent memory, of a next ticket number stored in a second persistent memory and updating the next ticket number in the second persistent memory. The method may also include determining when to serve a first thread based on the first copy of the next ticket number.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 24, 2019
    Assignee: Hewlett Packard Enterprise Patent Development LP
    Inventors: Mark Lillibridge, Milind M. Chabbi, Haris Volos
  • Patent number: 10353456
    Abstract: A system for controlling the advertising machine includes a standby control unit, an application processing unit and a power source unit. The application processing unit is configured to control an operation of the advertising machine. The power source unit is configured to provide power to the standby control unit, and provide power to the application processing unit under the control of the standby control unit. The standby control unit is configured to control a standby period and an operating period of the advertising machine according to a standby scheme, wherein during the standby period of the advertising machine, the power source unit is controlled to stop providing power to the application processing unit, and during the operating period of the advertising machine, the power source unit is controlled to provide power to the application processing unit.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: July 16, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Qingyong Li
  • Patent number: 10348307
    Abstract: An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first plurality of logic tiles generates the tile clock using (i) the first external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the first plurality, and a second logic tile to receive a second external clock signal wherein each logic tile of a second plurality of logic tiles generates the tile clock using (i) the second external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the second plurality, wherein the first and second external clock signals are the same clock signals.
    Type: Grant
    Filed: June 2, 2018
    Date of Patent: July 9, 2019
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Cheng C. Wang, Nitish U. Natu
  • Patent number: 10346226
    Abstract: Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 9, 2019
    Assignee: Time Warner Cable Enterprises LLC
    Inventors: Jason McElrath, Karan Sanghi, Saurabh Garg
  • Patent number: 10257811
    Abstract: A method and an apparatus for implementing a mobile broadband device service. The method includes the following steps: obtaining, service information of a mobile broadband device according to a rule set on the host or by calling an application programming interface of a Web server on the mobile broadband device; and when it is necessary to use a corresponding function of the host for implementing a mobile broadband device service corresponding to the service information, executing, the corresponding function of the host by calling an application programming interface provided by an operating system of the host, to implement the mobile broadband device service. In the embodiments of the present invention limitations when the mobile broadband device is managed in the Web manner are reduced, and a capability of managing the mobile broadband device is improved.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: April 9, 2019
    Assignee: HUAWEI DEVICE CO., LTD.
    Inventor: Zhen Zhong
  • Patent number: 10055252
    Abstract: A parallel computing control apparatus determines, among a plurality of nodes, relay nodes located on a path from a first node allocated to a job to a second node. The parallel computing control apparatus obtains an index value indicating a use state of resources in the relay nodes. The parallel computing control apparatus calculates an estimated value of a transfer period taken to transfer data on the job from the first node to the second node, on the basis of the index value and the memory usage of the job.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: August 21, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Takahiro Kagami, Tsuyoshi Hashimoto
  • Patent number: 10009032
    Abstract: Embodiments include systems and methods for providing reliable and precise sample alignment across different clock domains. Some embodiments operate in context of microprocessor power management circuits seeking correlated measurements of voltage droop (VD) and phase delay (PD). For example, a rolling code is generated for each of multiple second clock domain sample times (CDSTs). VD and the rolling code are both sampled according to a first clock domain to generate VD samples and corresponding VCode samples for each of multiple first CDSTs. PD can be sampled according to the second clock domain to generate PD samples for each of the second CDSTs, each associated with the rolling code for its second CDST. For any first CDST, the VD sample for the first CDST can be aligned with a PD sample for a coinciding second CDST by identifying matching associated rolling codes.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: June 26, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventor: Bruce E. Petrick
  • Patent number: 9882569
    Abstract: A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip includes a first synchronization controller and a first counter controller that allows a counter in the master chip to perform counting synchronously with a clock pulse in response to a synchronization control signal from the first synchronization controller. Another semiconductor integrated circuit as a slave chip includes a second synchronization controller that receives the synchronization control signal from the master chip, and a second counter controller that allows a counter in the slave chip to perform counting synchronously with the clock pulse in response to the synchronization control signal received. Each of the first and second counter controllers allows the counter to stop counting if the synchronization control signal is not supplied at the time point that a count value of the counter has reached a predetermined value.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: January 30, 2018
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Daisuke Kadota
  • Patent number: 9817433
    Abstract: A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: November 14, 2017
    Assignee: ARM Finance Overseas Limited
    Inventors: Kesava Reddy Talupuru, Sanjai B. Athi
  • Patent number: 9740300
    Abstract: By causing information processing apparatuses belonging to a same group to be in a same state and transmitting operation information received from an input unit to the information processing apparatuses belonging to the same group simultaneously or approximately simultaneously, the operations of the information processing apparatuses belonging to the same group are synchronized with each other, and operation results received from the synchronized information processing apparatuses belonging to the same group are output by an output unit. In this way, the plurality of grouped information processing apparatuses can be simultaneously operated.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: August 22, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Takahiro Konno
  • Patent number: 9733664
    Abstract: Systems, methods, and articles of manufacture provide for fault-tolerant timers, such as in an online gaming environment. Fault-tolerant timers may, for example, be provided by implementing specific methods for expiring a timer, such as by utilizing broadcast notices and distributed locks.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: August 15, 2017
    Assignee: Gamesys Ltd.
    Inventors: Phillip Jarlath Graham, Joshua Richard Watkins
  • Patent number: 9715432
    Abstract: Exemplary aspects are directed toward resolving fault suppression in hardware, which at the same time does not incur a performance hit. For example, when multiple instructions are executing simultaneously, a mask can specify which elements need not be executed. If the mask is disabled, those elements do not need to be executed. A determination is then made as to whether a fault happens in one of the elements that have been disabled. If there is a fault in one of the elements that has been disabled, a state machine re-fetches the instructions in a special mode. More specifically, the state machine determines if the fault is on a disabled element, and if the fault is on a disabled element, then the state machine specifies that the fault should be ignored. If during the first execution there was no mask, if there is an error present during execution, then the element is re-run with the mask to see if the error is a “real” fault.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: July 25, 2017
    Assignee: INTEL CORPORATION
    Inventors: Ramon Matas, Roger Gramunt, Chung-Lun Chan, Benjamin C. Chaffin, Aditya Kesiraju, Jonathan C. Hall, Jesus Corbal
  • Patent number: 9671816
    Abstract: One or more techniques and/or systems are provided for assigning power management classifications to a process, transitioning a computing environment into a connected standby state based upon power management classifications assigned to processes, and transitioning the computing environment from the connected standby state to an execution state. That is, power management classifications, such as exempt, throttle, and/or suspend, may be assigned to processes based upon various factors, such as whether a process provides desired functionality and/or whether the process provides functionality relied upon for basic operation of the computing environment. In this way, the computing environment may be transitioned into a low power connected standby state that may continue executing desired functionality, while reducing power consumption by suspending and/or throttling other functionality.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: June 6, 2017
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Jon Berry
  • Patent number: 9645870
    Abstract: Systems and methods for generating DMA transaction trace records are described. One example system includes a controller that includes a trace module. The trace module receives transfer requests for direct memory access channels, receives timestamps indicative of a transfer request time, generates trace records, wherein each trace record includes a respective timestamp indicative of a transfer request time, generates save commands, and delivers the trace records and the save commands as outputs. The system includes a storage module for saving trace records.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: May 9, 2017
    Assignee: Atmel Corporation
    Inventor: Ingar Hanssen
  • Patent number: 9639381
    Abstract: Disclosed are various embodiments for executing multiple applications in a single virtual machine. The classes of an application executing in the virtual machine are traversed to identify non-sharable static fields. Upon identifying a non-sharable static field, mapping data is created that corresponds to the non-sharable static field. During another traversal of the classes of the application, access to the identified non-sharable static field is translated into an access to the mapping data that is associated with the non-sharable static field.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 2, 2017
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Brian S. O'Neill, Matthew L. Trahan, Diwakar Chakravarthy
  • Patent number: 9632798
    Abstract: A method of operating a computer system in communications, via a communication network, with a server comprising an image of a kernel of a minimal operating system and an image of an associated file system for the computer system includes loading, via the communication network, the kernel image from the server to the computer system in accordance with a network transfer protocol interface, and loading, via the communication network, the file system image from the server to the computer system in accordance with the same network transfer protocol interface used to load the kernel image, wherein the loading of the kernel image from the server to the computer system is launched before the loading of the file system image from the server to the computer system is completed, and wherein the loading of the file system image from the server to the computer system is launched before the loading of the kernel image from the server to the computer system is completed.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: April 25, 2017
    Assignee: BULL SAS
    Inventors: Frederic Temporelli, Benoit Welterlen
  • Patent number: 9621689
    Abstract: System and method for determining the updating time by a server presumed to have a correct time and a client needing a correct time. The server can first transmit an unencrypted signal, which may be signed or unsigned. The server can then later encrypt or sign the same packet it transmitted with a private key and transmit it to the client. After the client receives the unencrypted packet, the client can compute a time difference. However the client doesn't update its time until a follow-up packet is received from the server. If encrypted, the packet is decoded with the server's public key, and the decoded packet is shown identical to the received packet and that the identification bits are the same.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: April 11, 2017
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventor: Demetrios Nicholas Matsakis
  • Patent number: 9544374
    Abstract: An operating system or other software resident on an electronic processing device employs aggregated timestamps. In this way timestamps can be generated and compared to one another without the need for a real-time clock with a power backup. Aggregated time includes the last known time that the device synchronized its clock with a reference time available over a network. Aggregated time also includes a relative time value which in part accumulates using a session clock whenever the device is powered-up. When network time becomes available the operating system or other software will use this information to fix up the already generated aggregated timestamps. A comparison of timestamps will most of the time be resolved for stamps generated on the same device and will generally be resolved by comparing time frames when the timestamps being compared are generated by different devices.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 10, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David Callaghan, Sergey Karamov
  • Patent number: 9529871
    Abstract: A method and system for providing information management of mobile device data provides a user interface to permit a user of an information management system to define information management policies for the mobile device, receives definitions of the information management policies from the provided interface, and sends data from the mobile device to the information management system in accordance with the information management policies. In some examples, the system sends information identifying the user and the mobile device to the information management system, and/or sends the information management policies defined from the interface to the information management system.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: December 27, 2016
    Assignee: Commvault Systems, Inc.
    Inventors: Anand Vibhor, Kedar Sunil Sarmalkar, Amey Vijaykumar Karandikar
  • Patent number: 9500705
    Abstract: The prediction of hardware failure is obtained by operating two redundant circuit modules while one circuit module is artificially aged. The output of the two circuit modules is compared and a discrepancy between outputs indicates a projected failure of the aged modules. Aging may be accomplished by one or a combination of lowering operating voltages and re-phasing a sampling clock to reduce slack time both of which provide increased sensitivity to gate delay.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: November 22, 2016
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Raghuraman Balasubramanian, Karthikeyan Sankaralingam
  • Patent number: 9490926
    Abstract: A processor time synchronization apparatus and method in a data communication system which includes a plurality of processors and line interfaces. The processor time synchronization apparatus includes a first local processor configured to recognize a time difference between an external device and the system based on a time message exchanged with the external device, and synchronize time between the external device and the system, and a second local processor configured to receive time information from the first local processor that has been time-synchronized with the external device, the time information containing the time difference between the external device and the system, and synchronize the first local processor with a system's internal time using the received time information.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 8, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Bup-Joong Kim, Tae-Sik Cheung, Bheom-Soon Joo, Jong-Hyun Lee
  • Patent number: 9477485
    Abstract: Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, performance characteristics associated with each available CPU, the performance characteristics associated with each available CPU including information describing computing devices such as memory devices, input/output (‘I/O) devices, and other downstream devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the performance characteristics associated with each available CPU and a predetermined performance policy, a target CPU to utilize as a boot CPU.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: October 25, 2016
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Brian A. Baker, Michael Decesaris, Jeffrey R. Hamilton, Douglas W. Oliver
  • Patent number: 9471329
    Abstract: Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, performance characteristics associated with each available CPU, the performance characteristics associated with each available CPU including information describing computing devices such as memory devices, input/output (‘I/O) devices, and other downstream devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the performance characteristics associated with each available CPU and a predetermined performance policy, a target CPU to utilize as a boot CPU.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: October 18, 2016
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Brian A. Baker, Michael Decesaris, Jeffrey R. Hamilton, Douglas W. Oliver
  • Patent number: 9471402
    Abstract: The disclosed computer-implemented method for facilitating dependency-ordered delivery of data sets to applications within distributed systems may include (1) receiving, at a queue of an application running within a distributed system, a data set from at least one other application running within the distributed system, (2) determining that the data set has a dependency on at least one other data set that has yet to arrive, (3) gating the data set at the queue due at least in part to the dependency, (4) receiving, at the queue, the other data set from the other application, (5) determining that the dependency has been satisfied, and then (6) delivering the data set and the other data set to the application to enable the application to process the data set and the other data set in accordance with the dependency. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: October 18, 2016
    Assignee: Juniper Networks, Inc.
    Inventors: Srinath Bayareddy, Aditya Thakur, Pramod Srinivasan, Robert Rodgers, Srivatsan Rajagopal
  • Patent number: 9442511
    Abstract: A method is provided for maintaining a synchronized local timer by using a periodic signal which comprises: providing a value of a clock cycle, and values for a first and second timer-parameters, wherein the first timer-parameter is less than the clock cycle value and the second timer-parameter is higher therefrom; providing values for a first (“a”) and second (“b”) arbitration parameters associated with the first and second timer-parameters respectively; upon receiving a periodic signal, adding to the local timer, at least once the first and/or the second timer-parameter, so that on average over one second, the first timer-parameter is added “a” times and the second timer-parameter is added “b” times, thereby ensuring that a value of the local timer essentially overlaps the period frequency of the periodic signal; upon receiving a subsequent periodic signal, setting the value of the local timer to a propagation delay of the periodic signal.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: September 13, 2016
    Assignee: ECI TELECOM LTD.
    Inventor: Oren Ish-Am
  • Patent number: 9436169
    Abstract: A system energy efficiency controller in a smart energy network, a control method thereof, and a control method for a terminal device. The system energy efficiency controller includes a control decision module, a storage module, a power clock module, an internal communication module, and an external communication module. The storage module is connected to the control decision module, and stores temporary and permanent information data in the operation process of the storage system. The power clock module provides an internal clock, achieving timing synchronization of processors on the controller. The internal communication module provides two-way communication between the system energy efficiency controller and control implementation units of multiple terminal devices. The external communication module provides two-way communication between the system energy efficiency controller and a local optimizer.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: September 6, 2016
    Assignee: ENN SCIENCE & TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Zhongxue Gan, Shenglong Dong, Qizhi Cai
  • Patent number: 9424106
    Abstract: A system for distributed information processing and interaction includes a plurality of output devices arranged to produce a respective output portion of a system output, a plurality of application processors and a state server in data communication with the plurality of application processors. Each respective output portion is defined by context information. Each application processor is configured to process one or more respective application programs and is responsive to the context information. Each application processor is coupled with an associated respective output device for controlling the output device in producing the respective output portion. The state server provides the context information to the plurality of application processors. The architecture is extended to a more general system in which output devices produce a variety of outputs including device actuations, as well as video displays, and receive a variety of inputs.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: August 23, 2016
    Assignee: Accenture Global Services Limited
    Inventors: Kelly L. Dempski, Brandon L. Harvey
  • Patent number: 9391927
    Abstract: Technologies generally described herein relate to systems and methods effective to control an operating frequency of routers in a multicore processor. Heterogeneous routers in a multicore processor with different maximum operating frequencies may be clustered together to form groups of routers with homogenous assigned operating frequencies. The groups may be used to identify paths to send packets from a first router to a second router along one or more paths.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: July 12, 2016
    Assignee: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Patent number: 9389971
    Abstract: A redundant automation system and a method for operating the redundant automation system which is provided with a first subsystem and a second subsystem that each process a control program while controlling a technical process, one of these subsystems operating as a master and the other subsystem operating as a slave, and the slave assuming the function of the master if the master fails such that it becomes possible to dispense with temporally synchronous communication between the participants with regard to the synchronization of the program processing in the two subsystems, thus reducing the communication load.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: July 12, 2016
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Grosch, Jürgen Laforsch, Albert Renschler
  • Patent number: 9286067
    Abstract: A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Valentina Salapura, Robert W. Wisniewski
  • Patent number: 9262272
    Abstract: A power cap agent establishes a power cap. The power cap agent throttles a first power priority virtual machine. The power cap agent determines that the first power priority virtual machine and the additional power priority virtual machine contribute to power consumption above the power cap among the plurality of servers. The power cap agent throttles the additional power priority virtual machine, wherein the first power priority virtual machine has a first power priority lower than an additional power priority of the additional power priority virtual machine. The power cap agent determines that the first power priority virtual machine and the additional power priority virtual machine contribute to power consumption above the power cap, responsive to throttling the first power priority virtual machine and throttling the additional virtual machine.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jason B. Akers, Ross B. Clay, Ryan A. Holt, Perry L. Jones
  • Patent number: 9244723
    Abstract: A non-transitory computer-readable medium including a program which, when executed by a computer, causes the computer to detect completion of one or more processes executed in at least one of the computer and another computer; determine whether the completion of the one or more processes corresponds to a process completion pattern when a specific transactional operation is completed in at least the one of the computer and the another computer; and determine that the specific transactional operation is completed when it is determined that the completion of the one or more processes corresponds to the process completion pattern.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: January 26, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Toru Murai
  • Patent number: 9219783
    Abstract: Apparatus, systems, and methods may operate to support synchronizing machines in groups. In some embodiments, synchronization is implemented by receiving an indication to activate a selected machine of a group of sync-aware machines connected to a subnet of a network, where each member of the group has information identifying all members of the group. Further activities include transmitting an activation message from the selected machine to the remainder of the group to notify the remainder that the selected machine is active, capturing a record of activities conducted at the selected machine while the selected machine is active, and transmitting information, based on the record, to the remainder of the group from the selected machine to synchronize results of the activities with the remainder after the selected machine becomes inactive. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: December 22, 2015
    Assignee: Novell, Inc.
    Inventor: Srinivasa Ragavan
  • Patent number: 9207707
    Abstract: An automated system and method that includes at least two cooperating electrical components, each having a time counter. The electrical components being coupled to one another via signals for cyclically transmitting process data via a signal network, and are synchronized with one another based on global, relative time information as a reference quantity.
    Type: Grant
    Filed: December 22, 2013
    Date of Patent: December 8, 2015
    Assignee: BAUMUELLER NUERNBERG GMBH
    Inventor: Stephan Buechner
  • Patent number: 9191721
    Abstract: A system for configuring an audio/video (AV) system includes a computing device having a processor to enable a user, with a user interface of the computing device, to configure the AV system. The processor may enable the user to draw output zones to create a representation of a geographical layout of a venue in which the AV system is located. The processor may enable the user to place transmitting and receiving AV devices within the output zones that substantially represent physical locations thereof within the venue. The processor may enable the user to logically associate receiving AV device channels of one or more receiving AV devices within an output zone. The processor may also enable the user to select which of a number of source AV signals from transmitting AV devices the user wants to route to the associated output zone.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: November 17, 2015
    Assignee: Harman International Industries, Incorporated
    Inventors: Adam Holladay, Richard A. Kreifeldt, Gregory Matthew Nelson, Spencer Warren George
  • Patent number: 9168006
    Abstract: Systems and methods for wirelessly controlling medical devices are provided. One system includes a portable user interface having a housing and a communication module within the housing configured to wirelessly communicate with at least one medical device. The portable user interface also includes a display displaying a graphical user interface to control the at least one medical device remotely, wherein the displayed graphical user interface corresponds to a control interface of the at least one medical device.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 27, 2015
    Assignee: General Electric Company
    Inventors: Emil Markov Georgiev, Scott William Robinson, Bayne Robin Upton
  • Patent number: 9158287
    Abstract: An information processing apparatus includes: a communication device communicating with an external device and a clock server; a first clock measuring a local time; a second clock measuring a time based on time information from the clock server; a storage device storing setting information; and a controller performing: when receiving the time information from the external device, judging whether a specified condition is met; when the specified condition is met, setting a time indicated by the time information to the first clock as the local time; when the specified condition is met, controlling the first clock to measure the local time, without the controller setting the time to the first clock as the local time; setting the time indicated by the time information to the second clock and setting a time determined based on the time of the second clock and the setting information to the first clock.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: October 13, 2015
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Takatoshi Ono
  • Patent number: 9104501
    Abstract: A job may be divided into multiple tasks that may execute in parallel on one or more compute nodes. The tasks executing on the same compute node may be coordinated using barrier synchronization. However, to perform barrier synchronization, the tasks use (or attach) to a barrier synchronization register which establishes a common checkpoint for each of the tasks. A leader task may use a shared memory region to publish to follower tasks the location of the barrier synchronization register—i.e., a barrier synchronization register ID. The follower tasks may then monitor the shared memory to determine the barrier synchronization register ID. The leader task may also use a count to ensure all the tasks attach to the BSR. This advantageously avoids any task-to-task communication which may reduce overhead and improve performance.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tsai-Yang Jea, William P. Lepera, HanHong Xue, Zhi Zhang
  • Patent number: 9092272
    Abstract: A job may be divided into multiple tasks that may execute in parallel on one or more compute nodes. The tasks executing on the same compute node may be coordinated using barrier synchronization. However, to perform barrier synchronization, the tasks use (or attach) to a barrier synchronization register which establishes a common checkpoint for each of the tasks. A leader task may use a shared memory region to publish to follower tasks the location of the barrier synchronization register—i.e., a barrier synchronization register ID. The follower tasks may then monitor the shared memory to determine the barrier synchronization register ID. The leader task may also use a count to ensure all the tasks attach to the BSR. This advantageously avoids any task-to-task communication which may reduce overhead and improve performance.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tsai-Yang Jea, William P. LePera, Hanhong Xue, Zhi Zhang
  • Patent number: 9058179
    Abstract: A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20. In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits dispatch of other instructions to proceed but controls the commit queue and the result queue such that no program instructions in program order succeeding the status access instruction are permitted to complete until after a trigger state has been detected in which all program instructions preceding in program order the status access instruction have been performed and made any updates to the architectural state. This is followed by the performance of the status access instruction itself.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: June 16, 2015
    Assignee: ARM Limited
    Inventor: James Nolan Hardage
  • Patent number: 9037892
    Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Gerard V. Kopcsay, Thomas A. Liebsch, Don D. Reed