Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: A communication method is provided to reduce an overhead of inter-processor synchronization for a communication phase in collective communication and to speed up the collective communication. Each of processors in a parallel computer start a previous process before a collective communication phase in which communications are performed at a same time among the processors through a inter-processor network. Each processor executes a synchronization command in advance at a time when a portion of the previous process for a predetermined time t is left. The inter-processor synchronization control section transmits a synchronization completion notice to each processor, if a synchronization condition is met. For the period, each processor executes the previous process in parallel. Then, the plurality of processors enter the collective communication phase.

Abstract: A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent read and write to counters so that write signals from the fast clock domain can be directly used in the slower clock domain when the counters are not toggling. This feature removes the need for sampling and holding the data on the fast clock, which would require consume additional power and require additional circuit area.

Abstract: Systems and methods for authenticating access to multiple data stores substantially in real-time are disclosed. The system may include a server coupled to a network, a client device in communication with the server via the network and a plurality of data stores. The server may authenticate access to the data stores and forward information from those stores to the client device. An exemplary authentication method may include receipt of a request for access to data. Information concerning access to that data is stored and associated with an identifier assigned to a client device. If the identifier is found to correspond to the stored information during a future request for access to the store, access to that store is granted.

Abstract: In an information processing apparatus that includes a first and second semiconductor devices that are connected to each other and also includes a system control device that is connected to the first and second semiconductor devices, the timers that are mounted on the semiconductor devices are all synchronized by successively performing a timer correction process between a semiconductor device in which the timer is synchronized and a semiconductor device, adjacent to the semiconductor device, in which the timer is not synchronized, and, when an error occurs in the information processing device, the value in the synchronized timer and the error information are stored in a predetermined register.

Abstract: A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Abstract: A computing device that includes a host processor and a service processor is provided. The host processor is configured to interact with a first user interface. For example, the host processor may be a microprocessor for the device and the first user interface may be a display device. A service processor is provided and can interact with a second user interface. In some cases, the service processor may interact with the second user interface without communicating with the host processor. Accordingly, the service processor can perform functions without relying on the host processor. Using the service processor conserves processing power and also may allow the reduction in size of the device as the service processor may perform the functions previously performed by discrete hardware and the host processor.

Abstract: The goal of the present invention is to improve the useful data efficiency and reliability in the use of commercially available ETHERNET controllers, in a distributed real time computer system, by a number of node computers communicating via one or more communication channels by means of TT ETHERNET messages. To achieve this goal, a distinction is made between the node computer send time (KNSZPKT) and the network send time (NWSZPKT) of a message. The KNSZPKT must wait for the NWSZPKT, so that under all circumstances, the start of the message has arrived in the TT star coupler at the NWSZPKT, interpreted by the clock in the TT star coupler. The TT star coupler is modified, so that a message arriving from a node computer is delayed in an intelligent port of the TT star coupler until the NWSZPKT can send it precisely at the NWSZPKT into the TT network.

Abstract: A node-to-node synchronizing apparatus includes an information generating unit. Before receiving a synchronization request for synchronization, the information generating unit receives, from each process in each computing node, a mask generation request requesting to generate process location information (mask) indicating the location of processes that participate in synchronization. The information generating unit then automatically generates the process location information based on the mask generation request.

Abstract: Methods and apparatus for controlling at least two processing cores in a multi-processor device or system include accessing an operating system run queue to generate virtual pulse trains for each core and correlating the virtual pulse trains to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processing cores to provide a performance level that accommodates interdependent processes, threads and processing cores.

Abstract: A multi-core processor and a frequency conversion device thereof as well as a method of communication between the cores are disclosed. Each processor core of the multi-core processor includes a frequency conversion device, which includes a multi-bit state changing means, a multiple selector, a frequency conversion coefficient register, a multi-input OR gate and a clock-gating circuit unit. A common original clock is sent to the frequency conversion device of each processor core at work. The frequency conversion device real-timely reads the value of the frequency conversion coefficient register of a corresponding processor core and receives data transmission valid signals from other processor cores. By gating the common original clock, a frequency conversion function of the processor core is completed.

Abstract: There is described a method for transmitting synchronization messages, for example PTP messages of the IEEE 1588 standard, the PTP message being inserted into a data packet in line with the Internet Protocol, the data packet having an IP header, and the data packet having a UDP header. In this case, for the encrypted transmission on the PTP message, the data packet is addressed to a UDP port that is reserved for encrypted PTP messages, the data packet is provided with an additional S-PTP header that is provided for encryption, the PTP message is extended with a pseudo random number, and the PTP message is encrypted together with the pseudo random number.

Abstract: This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention selects a set of the finite state machines to participate in an operation. If one or more of the finite state machines are selected for operation, the method waits until all selected finite state machines generate the ready signal. If none of the finite state machines are selected for operation, the method waits until at least one non-selected finite state machine generates the ready signal. This waiting can be accomplished with a precharge-conditional discharge circuit used for voting.

Abstract: Systems, methods and computer readable media for synchronization of electronic message accounts. In one embodiment, a method includes receiving information to establish an electronic message account on a first data processing system, the electronic message account being defined by setup information, and synchronizing the setup information onto a store on a second data processing system. In another embodiment, a method includes receiving information to establish an electronic message account, defined by first setup information, on a host and synchronizing the first setup information onto a device when the device is coupled to the host for synchronization. Systems, other methods and computer readable media are also described.

Abstract: Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.

Abstract: Systems and methods for synchronization of an external control system with Fieldbus devices are described. A message including timing information for at least one Fieldbus device in direct or indirect communication with a controller may be received by the controller. Based upon information included in the received message, the controller may determine a start time for a current operation cycle of the at least one Fieldbus device. The controller may then utilize the start time and a duration of the current operation cycle to determine a specific time at which the controller will execute control functionality for the at least one Fieldbus device such that a control message output by the controller will be received by the at least one Fieldbus device within the current operation cycle.

Abstract: An electric device is capable of operating in a normal operation mode and a power save operation mode. The electric device includes a first processor for processing information input externally in the normal operation mode, and a second processor for processing an internal operation of the electric device in the normal operation mode. The second processor consumes power smaller than that of the first processor. In the electric device, power of the first processor is restricted through a restriction process in the power save operation mode. Further, in the power save operation mode, the second processor restricts the internal operation and processes the information input externally. When the second processor detects the information input externally, power of the first processor is released through a restriction releasing process.

Abstract: Disclosed are various embodiments for determining a source of malware. At least one embodiment of a method includes receiving browsing data from a plurality of client devices, the data being sent by the plurality of client devices, in response to a determination of malware on the plurality of client devices and determining, from the browsing data, a source for the malware. Further, some embodiments include determining whether the source for the malware is associated with a predetermined network site and in response to determining that the source of the malware is associated with a predetermined network site, preventing download of at least a portion of the predetermined network site.

Abstract: A virtual machine receives a request for a current time. The virtual machine determines an approximation of the current time based on readings from one of a plurality of processors and compares the approximation to a virtual machine time stamp value. If the approximation is smaller than the virtual machine time stamp value, the virtual machine returns the global time stamp value as the current time and if the approximation is not smaller than the virtual machine time stamp value, the virtual machine returns the approximation as the current time.

Abstract: Methods and systems for preserving user attribute data by way of managing and synchronizing redundant storage locations.

Abstract: A method, a CAN bus driver and a CAN bus system for the recovery of a clock frequency of a CAN bus, which couples a master device, that has a clock generator for providing the clock frequency, to at least one slave device. A phase-locked loop is used in the slave device, in this context, which utilizes a predetermined bit pattern, that is extracted from a frame sent by the master device via the bus system, as reference signal.

Abstract: A programmable logic processor (PLC) with multiple PLC functions is disclosed. The PLC includes at least one memory storing at least one of a plurality of programs or data, and one or more processor assigned to each of the PLC function and couple to the memory. The PLC functions are run in parallel. A method of operating the PLC and a PLC system with multiple processors are also disclosed.

Abstract: A user of multiple client devices (clients) makes application configuration changes on the clients from time to time. The configuration changes are stored in a local event log on each client, as well as in a synchronization server. When one of the clients connects to the synchronization server, for example when the user logs into the synchronization server while using a respective client, the configuration information in the server and client is synchronized. Conflicts, if any, in the configuration changes for a respective application are resolved in accordance with a conflict resolution procedure or conflict resolution rules associated with that application.

Abstract: Disclosed herein are techniques to manage access to a memory using a buffer construct that includes state information associated with a region of the memory. The disclosed techniques facilitate access to the region of memory through a direct memory access operation while the state information of the buffer construct is in a first state. The state information can be transitioned to a second state in response to a first instruction. The disclosed techniques also facilitate access to the region of memory through a cache operation while the state information of the buffer construct is in the second state is disclosed. The state information can be transitioned to the first state in response to a second instruction.

Abstract: Systems, methods, devices that enable the efficient synchronization of timing information from first time-based process to a second time-based process using periodic or event-driven synchronization messages are provided. In one aspect, the invention includes a media processing system having a first process for processing media based, at least in part, on first timing information derived from a first timing source and a second timing source. The system may also include a second process for processing the media based, at least in part, on second timing information derived from the first timing source. The first process may send one or more timing synchronization messages, generated based at least in part on the first timing source and the second timing source, to the second process to synchronize the second timing information with the first timing information.

Abstract: The present invention relates to a method of generating a downlink frame. The method of generating the downlink frame includes: generating a first short sequence and a second short sequence indicating cell group information; generating a first scrambling sequence and a second scrambling sequence determined by the primary synchronization signal; generating a third scrambling sequence determined by the first short sequence; scrambling the first short sequence with the first scrambling sequence and scrambling the second short sequence with the second scrambling sequence and the third scrambling sequence; and mapping the secondary synchronization signal that includes the scrambled first short sequence and the scrambled second short sequence to a frequency domain.

Abstract: The present invention is directed towards systems and methods for managing SSL session persistence and reuse in a multi-core system. A first core may indicate that an SSL session established by the first core is non-resumable. Responsive to the indication, the core may set an indicator at a location in memory accessible by each core of the multi-core system, the indicator indicating that the SSL session is non-resumable. A second core of the multi-core system may receive a request to reuse the SSL session. The request may include a session identifier of the SSL session. In addition, the session identifier may identify the first core as an establisher of the SSL session. The second core can identify from encoding of the session identifier whether the second core is not the establisher of the SSL session. Responsive to the identification, the second core may determine whether to resume the SSL session.

Abstract: A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache that caches normal active mode software instructions executed by a high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.

Abstract: A method for setting an electronic ballast (101), wherein the electronic ballast and a compensating unit are synchronized, and wherein setting of the electronic ballast is performed by the compensating unit.

Abstract: Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.

Abstract: The present invention facilitates the dynamic provisioning of data assets in a shared storage environment. The invention provides a system and method for dynamically provisioning and de-provisioning shared storage resources based on multi-dimensional decision criteria. By employing specialized computing components configured to assess a data asset and requestor of a data asset, a provisioning engine is able to transform the input from the computing components into a specific configuration of shared storage resource provisioning and security controls. According to the rules and policies applying to a security domain, the provisioning engine may dynamically allocate shared storage resources in a manner that is both safe and efficient for the data asset.

Abstract: A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, determine whether to exit the entry synchronization loop after the timeout value has been reached.

Abstract: A data processing system includes a power supply, a plurality of processors wherein each processor is separately powerable by the power supply under operating system control. The operating system determines periodically a measure of system utilization and controls the switches to alter the number of active (powered) processors where the number of active processors reflects the measured system utilization and a set of utilization threshold values. System utilization may be based on the number of active tasks. The utilization thresholds preferably include a maximum threshold and a minimum threshold. A measured utilization exceeding the maximum threshold causes an increase in the number of active processors while utilization less than the minimum threshold causes a decrease in the number of active processors. The utilization thresholds may be determined from threshold factors that reflect time and date information, quality of service information, or a weighted average of historical utilization values.

Abstract: Systems and methods for rapid Byzantine-fault-tolerant self-stabilizing clock synchronization are provided. The systems and methods are based on a protocol comprising a state machine and a set of monitors that execute once every local oscillator tick. The protocol is independent of specific application specific requirements. The faults are assumed to be arbitrary and/or malicious. All timing measures of variables are based on the node's local clock and thus no central clock or externally generated pulse is used. Instances of the protocol are shown to tolerate bursts of transient failures and deterministically converge with a linear convergence time with respect to the synchronization period as predicted.

Abstract: The invention relates to the use of history information as an aid to synchronization in a peer-to-peer system. In particular, node trees are used to represent portions of files systems designated for synchronization. The nodes in the node tree embody history information regarding associated objects. The history information includes version vectors that are used to simplify synchronization-related comparisons and create job lists that may be used to bring participating peers into synchronization.

Abstract: A mechanism is provided for controlling operational parameters associated with a plurality of processors. A control system in the data processing system determines a utilization slack value of the data processing system. The utilization slack value is determined using one or more active core count values and one or more slack core count values. The control system computes a new utilization metric to be a difference between a full utilization value and the utilization slack value. The control system determines whether the new utilization metric is below a predetermined utilization threshold. Responsive to the new utilization metric being below the predetermined utilization threshold, the control system decreases a frequency of the plurality of processors.

Abstract: Provided are a method and apparatus for controlling a plurality of data processing modules that process data independently and output the processed data. A method of controlling a first data processing module and a second data processing module that process data independently and synchronize and output the processed data, the method including acquiring first data output rate information representing a current data output rate of the first data processing module, acquiring second data output rate information representing a current data output rate of the second data processing module, and adjusting a data output rate of at least one of the first data processing module and the second data processing module, on the basis of the first data output rate information and the second data output rate information.

Abstract: A method for dynamically operating a multi-core processor system is provided. The method involves ascertaining currently active processor cores, identifying a currently active processor core having a lowest operating frequency, and adjusting at least one operational parameter according to voltage-frequency characteristics corresponding to the identified processor core to fulfill a predefined functional mode, e.g. power optimization mode, performance optimization mode and mixed mode.

Abstract: Systems, methods and computer readable media for synchronization of electronic message accounts. In one embodiment, a method includes receiving information to establish an electronic message account on a first data processing system, the electronic message account being defined by setup information, and synchronizing the setup information onto a store on a second data processing system. In another embodiment, a method includes receiving information to establish an electronic message account, defined by first setup information, on a host and synchronizing the first setup information onto a device when the device is coupled to the host for synchronization. Systems, other methods and computer readable media are also described.

Abstract: Method of controlling a wind power system including a plurality of system elements, the wind power system including a plurality of data processors distributed in the system elements, the method including the steps of: synchronizing at least a part of the data processors to at least one reference signal distributed to the data processors from a time synchronization arrangement, associating the data processors with local clock generation circuitries, wherein the local clock generation circuitries associated with data processors of a first subset of the data processors have a peak-to-peak tracking jitter higher than or equal to a predetermined threshold value and wherein a second subset of the data processors have a peak-to-peak tracking jitter less than the predetermined threshold value, controlling at least one of the system elements at least partly by means of a data processor from the first or second subset of data processors.

Abstract: An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: Generating an exception list by a service provider for use in behavior monitoring programs for malware detection is described. A feedback server controlled by a malware prevention service provider receives client process reports from client devices owned by the service provider's customers and others using the provider's behavior monitoring software. The process reports contain data on processes that were evaluated (on the client device) as being processes that require a significant amount of CPU resources (i.e., above a certain threshold) to monitor and that have previously executed on the client device and were considered safe or non-harmful to the device. The feedback server receives the process reports and creates a statistics summary report, which is used by the service provider in evaluating whether to include the processes in the provider's official exception list which is distributed to its customers for use in their behavior monitoring programs.

Abstract: A method and a device for controlling a computer system having at least two execution units, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. At least one set of runtime objects is defined; at least one identifier is assigned to each runtime object of the defined set; and the identifier assigns at least the two operating modes to the runtime object.

Abstract: In a computer system, a standby master processor is configured to serve as a backup processor for an active master processor. A third party replica processor is configured to monitor and record changes on the active master processor when the active master processor is executing, and is further configured to synchronize itself with the standby master processor when the standby master processor takes over execution from the active master processor. Logs of changes are maintained. A negotiation occurs between the standby master processor and the third party replica processor to determine the status of the logs of the standby master processor and the third party replica processor, and logs are applied or paused relating to one or more of the standby master processor and the third party replica processor to synchronize the standby master processor and the third party replica processor.

Abstract: A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores.

Abstract: A system may be employed for allowing the synchronous operation of an asynchronous system. The system may be a system that may include multiple clusters. The clusters may include asynchronous clock domains and may also receive a global clock signal through a global clock grid that may overlay the system. Furthermore, a method may be employed for synchronizing asynchronous clock domains within a cluster. The method of synchronizing may include providing a global clock that corresponds to a global clock grid to each cluster. Additionally, the method of synchronizing may include accounting for the mismatch between the asynchronous clock domains by employing logic in a block.

Abstract: An editing system in which a personal computer is easily configured as an editing apparatus that performs editing processing in synchronization with predetermined timing. According to the invention, a personal computer 2 transmits an acquisition command C1 to a timing notice apparatus 4 over a USB cable 3, as a result, the personal computer 2 receives a timing notice signal S2 transmitted from the timing notice apparatus 4 under frame timing over the USB cable 3. Thus, it becomes possible to notify the personal computer 2 of the frame timing as reception timing of the timing notice signal S2 by connecting the timing notice apparatus 4 to the personal computer 2 over the USB cable 3 without the need of troublesome works such as installing a PCI board in a main body of the personal computer 2, thereby realizing an editing system 1 in which the personal computer 2 is easily configured as an editing apparatus that performs editing processing in synchronization with predetermined timing.

Abstract: A method and apparatus for printing using a synchronization signal are provided. Printing processes are performed in the apparatus by determining points in time for performing the printing processes based on a synchronization signal so that it is possible to reduce a waiting time for printing.

Abstract: A memory controller for a smart card including a non-volatile memory can include an internal circuit that is configured to perform cryptographic key processing responsive to a first clock and a non-volatile memory interface circuit for transferring/receiving a signal to/from the internal circuit in synchronization with the first clock and transferring/receiving the signal to/from an external device in synchronization with a second clock that is asynchronous relative to the first clock.