Abstract: The prediction of hardware failure is obtained by operating two redundant circuit modules while one circuit module is artificially aged. The output of the two circuit modules is compared and a discrepancy between outputs indicates a projected failure of the aged modules. Aging may be accomplished by one or a combination of lowering operating voltages and re-phasing a sampling clock to reduce slack time both of which provide increased sensitivity to gate delay.

Abstract: A processor time synchronization apparatus and method in a data communication system which includes a plurality of processors and line interfaces. The processor time synchronization apparatus includes a first local processor configured to recognize a time difference between an external device and the system based on a time message exchanged with the external device, and synchronize time between the external device and the system, and a second local processor configured to receive time information from the first local processor that has been time-synchronized with the external device, the time information containing the time difference between the external device and the system, and synchronize the first local processor with a system's internal time using the received time information.

Abstract: Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, performance characteristics associated with each available CPU, the performance characteristics associated with each available CPU including information describing computing devices such as memory devices, input/output (‘I/O) devices, and other downstream devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the performance characteristics associated with each available CPU and a predetermined performance policy, a target CPU to utilize as a boot CPU.

Abstract: Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, performance characteristics associated with each available CPU, the performance characteristics associated with each available CPU including information describing computing devices such as memory devices, input/output (‘I/O) devices, and other downstream devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the performance characteristics associated with each available CPU and a predetermined performance policy, a target CPU to utilize as a boot CPU.

Abstract: The disclosed computer-implemented method for facilitating dependency-ordered delivery of data sets to applications within distributed systems may include (1) receiving, at a queue of an application running within a distributed system, a data set from at least one other application running within the distributed system, (2) determining that the data set has a dependency on at least one other data set that has yet to arrive, (3) gating the data set at the queue due at least in part to the dependency, (4) receiving, at the queue, the other data set from the other application, (5) determining that the dependency has been satisfied, and then (6) delivering the data set and the other data set to the application to enable the application to process the data set and the other data set in accordance with the dependency. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method is provided for maintaining a synchronized local timer by using a periodic signal which comprises: providing a value of a clock cycle, and values for a first and second timer-parameters, wherein the first timer-parameter is less than the clock cycle value and the second timer-parameter is higher therefrom; providing values for a first (“a”) and second (“b”) arbitration parameters associated with the first and second timer-parameters respectively; upon receiving a periodic signal, adding to the local timer, at least once the first and/or the second timer-parameter, so that on average over one second, the first timer-parameter is added “a” times and the second timer-parameter is added “b” times, thereby ensuring that a value of the local timer essentially overlaps the period frequency of the periodic signal; upon receiving a subsequent periodic signal, setting the value of the local timer to a propagation delay of the periodic signal.

Abstract: A system energy efficiency controller in a smart energy network, a control method thereof, and a control method for a terminal device. The system energy efficiency controller includes a control decision module, a storage module, a power clock module, an internal communication module, and an external communication module. The storage module is connected to the control decision module, and stores temporary and permanent information data in the operation process of the storage system. The power clock module provides an internal clock, achieving timing synchronization of processors on the controller. The internal communication module provides two-way communication between the system energy efficiency controller and control implementation units of multiple terminal devices. The external communication module provides two-way communication between the system energy efficiency controller and a local optimizer.

Abstract: A system for distributed information processing and interaction includes a plurality of output devices arranged to produce a respective output portion of a system output, a plurality of application processors and a state server in data communication with the plurality of application processors. Each respective output portion is defined by context information. Each application processor is configured to process one or more respective application programs and is responsive to the context information. Each application processor is coupled with an associated respective output device for controlling the output device in producing the respective output portion. The state server provides the context information to the plurality of application processors. The architecture is extended to a more general system in which output devices produce a variety of outputs including device actuations, as well as video displays, and receive a variety of inputs.

Abstract: Technologies generally described herein relate to systems and methods effective to control an operating frequency of routers in a multicore processor. Heterogeneous routers in a multicore processor with different maximum operating frequencies may be clustered together to form groups of routers with homogenous assigned operating frequencies. The groups may be used to identify paths to send packets from a first router to a second router along one or more paths.

Abstract: A redundant automation system and a method for operating the redundant automation system which is provided with a first subsystem and a second subsystem that each process a control program while controlling a technical process, one of these subsystems operating as a master and the other subsystem operating as a slave, and the slave assuming the function of the master if the master fails such that it becomes possible to dispense with temporally synchronous communication between the participants with regard to the synchronization of the program processing in the two subsystems, thus reducing the communication load.

Abstract: A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.

Abstract: A power cap agent establishes a power cap. The power cap agent throttles a first power priority virtual machine. The power cap agent determines that the first power priority virtual machine and the additional power priority virtual machine contribute to power consumption above the power cap among the plurality of servers. The power cap agent throttles the additional power priority virtual machine, wherein the first power priority virtual machine has a first power priority lower than an additional power priority of the additional power priority virtual machine. The power cap agent determines that the first power priority virtual machine and the additional power priority virtual machine contribute to power consumption above the power cap, responsive to throttling the first power priority virtual machine and throttling the additional virtual machine.

Abstract: A non-transitory computer-readable medium including a program which, when executed by a computer, causes the computer to detect completion of one or more processes executed in at least one of the computer and another computer; determine whether the completion of the one or more processes corresponds to a process completion pattern when a specific transactional operation is completed in at least the one of the computer and the another computer; and determine that the specific transactional operation is completed when it is determined that the completion of the one or more processes corresponds to the process completion pattern.

Abstract: Apparatus, systems, and methods may operate to support synchronizing machines in groups. In some embodiments, synchronization is implemented by receiving an indication to activate a selected machine of a group of sync-aware machines connected to a subnet of a network, where each member of the group has information identifying all members of the group. Further activities include transmitting an activation message from the selected machine to the remainder of the group to notify the remainder that the selected machine is active, capturing a record of activities conducted at the selected machine while the selected machine is active, and transmitting information, based on the record, to the remainder of the group from the selected machine to synchronize results of the activities with the remainder after the selected machine becomes inactive. Additional apparatus, systems, and methods are disclosed.

Abstract: An automated system and method that includes at least two cooperating electrical components, each having a time counter. The electrical components being coupled to one another via signals for cyclically transmitting process data via a signal network, and are synchronized with one another based on global, relative time information as a reference quantity.

Abstract: A system for configuring an audio/video (AV) system includes a computing device having a processor to enable a user, with a user interface of the computing device, to configure the AV system. The processor may enable the user to draw output zones to create a representation of a geographical layout of a venue in which the AV system is located. The processor may enable the user to place transmitting and receiving AV devices within the output zones that substantially represent physical locations thereof within the venue. The processor may enable the user to logically associate receiving AV device channels of one or more receiving AV devices within an output zone. The processor may also enable the user to select which of a number of source AV signals from transmitting AV devices the user wants to route to the associated output zone.

Abstract: Systems and methods for wirelessly controlling medical devices are provided. One system includes a portable user interface having a housing and a communication module within the housing configured to wirelessly communicate with at least one medical device. The portable user interface also includes a display displaying a graphical user interface to control the at least one medical device remotely, wherein the displayed graphical user interface corresponds to a control interface of the at least one medical device.

Abstract: An information processing apparatus includes: a communication device communicating with an external device and a clock server; a first clock measuring a local time; a second clock measuring a time based on time information from the clock server; a storage device storing setting information; and a controller performing: when receiving the time information from the external device, judging whether a specified condition is met; when the specified condition is met, setting a time indicated by the time information to the first clock as the local time; when the specified condition is met, controlling the first clock to measure the local time, without the controller setting the time to the first clock as the local time; setting the time indicated by the time information to the second clock and setting a time determined based on the time of the second clock and the setting information to the first clock.

Abstract: A job may be divided into multiple tasks that may execute in parallel on one or more compute nodes. The tasks executing on the same compute node may be coordinated using barrier synchronization. However, to perform barrier synchronization, the tasks use (or attach) to a barrier synchronization register which establishes a common checkpoint for each of the tasks. A leader task may use a shared memory region to publish to follower tasks the location of the barrier synchronization register—i.e., a barrier synchronization register ID. The follower tasks may then monitor the shared memory to determine the barrier synchronization register ID. The leader task may also use a count to ensure all the tasks attach to the BSR. This advantageously avoids any task-to-task communication which may reduce overhead and improve performance.

Abstract: A job may be divided into multiple tasks that may execute in parallel on one or more compute nodes. The tasks executing on the same compute node may be coordinated using barrier synchronization. However, to perform barrier synchronization, the tasks use (or attach) to a barrier synchronization register which establishes a common checkpoint for each of the tasks. A leader task may use a shared memory region to publish to follower tasks the location of the barrier synchronization register—i.e., a barrier synchronization register ID. The follower tasks may then monitor the shared memory to determine the barrier synchronization register ID. The leader task may also use a count to ensure all the tasks attach to the BSR. This advantageously avoids any task-to-task communication which may reduce overhead and improve performance.

Abstract: A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20. In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits dispatch of other instructions to proceed but controls the commit queue and the result queue such that no program instructions in program order succeeding the status access instruction are permitted to complete until after a trigger state has been detected in which all program instructions preceding in program order the status access instruction have been performed and made any updates to the architectural state. This is followed by the performance of the status access instruction itself.

Abstract: Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.

Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

Abstract: A multi-processor system includes a first processor that includes a first time base counter that outputs a first time base count, a second processor that includes a second time base counter that outputs a second time base count, and a communication bus. The first and second processors exchange the first and second time base counts on the communication bus. The first and second processors determine a skew based upon a difference between the first and second time base counts, and the first and second processors synchronize with each other based upon the skew.

Abstract: The present invention relates to a method of synchronous control for a synchronous control system provided with a master device and at least one slave device connected via a communications network. The master device transmits first time data to the master device and the at least one slave device upon detection of generation of a synchronization signal, the first time data indicating a time at which the synchronization signal is generated. The master device transmits second time data to the at least one slave device upon reception of the first time data, the second time data indicating a time at which the first time data is received.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: An information processing apparatus includes a plurality of output circuits that output a plurality of pieces of information to an external device. Each of the output circuits includes a synchronization control unit that synchronizes an operation clock of the output circuit with an operation clock of a separate output circuit; an information receiving unit that receives a piece of information that is different from a piece of information that is received by the separate output circuit; and an output control unit that outputs the received piece of information to the external device in accordance with the synchronized operation clock.

Abstract: An industrial automation system comprising a processor with an updating component coupled to automation devices via a network. The updating component reads control information from machine readable representations of the devices and populates a data structure with the control information. The updating component also updates configuration information of a device from data stored in a file object and/or the data structure, further allowing this transfer to be fragmented into a plurality of messages if the configuration information exceeds a threshold. As well, a vendor deployment methodology is provided that embeds devices and firmware for devices with a Device Type Manager (DTM) prior to deployment and can optionally allow post deployment updates to the DTM.

Abstract: A system and associated methods for providing electronically noted items are disclosed. The noting application includes a communication module, a determination module, a ranking module and a presentation module. The communication module receives a request for electronically noted items from a first user and user identification data identifying the first user. The determination module determines one or more second users related to the first user based at least in part on the user identification data. The determination module retrieves a first set of two or more electronically noted items marked by the one or more second users. The ranking module ranks the first set of two or more electronically noted items to generate a second set of two or more electronically noted items. The presentation module provides for display the second set of two or more electronically noted items to the first user.

Abstract: One embodiment sets forth a technique for N-way memory barrier operation coalescing. When a first memory barrier is received for a first thread group execution of subsequent memory operations for the first thread group are suspended until the first memory barrier is executed. Subsequent memory barriers for different thread groups may be coalesced with the first memory barrier to produce a coalesced memory barrier that represents memory barrier operations for multiple thread groups. When the coalesced memory barrier is being processed, execution of subsequent memory operations for the different thread groups is also suspended. However, memory operations for other thread groups that are not affected by the coalesced memory barrier may be executed.

Abstract: In a computer system, a standby master processor is configured to serve as a backup processor for an active master processor. A third party replica processor is configured to monitor and record changes on the active master processor when the active master processor is executing, and is further configured to synchronize itself with the standby master processor when the standby master processor takes over execution from the active master processor. Logs of changes are maintained. A negotiation occurs between the standby master processor and the third party replica processor to determine the status of the logs of the standby master processor and the third party replica processor, and logs are applied or paused relating to one or more of the standby master processor and the third party replica processor to synchronize the standby master processor and the third party replica processor.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for synchronizing at least one newly activated processor with at least one previously running processor. Each processor is configured to generate a heartbeat and operate according to a STICK. When a previously deactivated processor is added, the heartbeat of each active processor is reset and the current STICK is transmitted to the newly activated processor on the next heartbeat. The newly activated processor may then add the heartbeat period to the acquired STICK and begin incrementing the STICK and normal operation after the next heartbeat.

Abstract: A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the plurality of processing units when the operation clocks of a common frequency are supplied to the plurality of processing units, and to control a frequency of the operation clocks to be supplied to at least one of the plurality of processing units so that a plurality of measured response times become closer to each other.

Abstract: According to one embodiment, there is provided an interface circuit including a plurality of units. Each of the plurality of units includes a clock interface, a data interface, and a selector. The clock interface receives a clock and transfers the clock. The data interface receives data and transfers the data. The selector selects a clock and supplies the selected clock to the data interface such that the data interface transfers the data in synchronization with the selected clock.

Abstract: Techniques for image copying optimization are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for image copying optimization comprising receiving a request to copy a plurality of images, copying one or more of the plurality of images, deferring synchronization for each of the one or more of the plurality of images, receiving an indication to stop deferring synchronization, and synchronizing the one or more copied images of the plurality of images.

Abstract: The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.

Abstract: A portable handheld device includes an image sensor for capturing an image; an orientation sensor for determining a rotation of the image sensor; and a system-on-chip processor having integrated on a common wafer a CPU for processing a script language, a multi-core processor for processing an image captured by the image sensor, and a common synchronization register. The multi-core processor includes multiple processing units connected in parallel by a crossbar switch. Each processing unit stores one or more synchronization bits for identifying which of the other processing units are functioning as a single process therewith. The common synchronization register contains therein synchronization bits from each of the processing units.

Abstract: Asynchronous circuits and techniques are described for asynchronous processing without synchronization to a common clock. Two specific energy-efficient pipeline templates for high throughput asynchronous circuits are provided as examples based on single-track handshake protocol. Each pipeline contains multiple stages of logic. The handshake overhead is minimized by eliminating validity and neutrality detection logic gates for all input tokens as well as for all intermediate logic nodes. Both of these templates can pack significant amount of logic within each pipeline block, while still maintaining a fast cycle time.

Abstract: A method includes receiving identification of an object that includes a plurality of nodes. The object is modeled to provide for association of any of the plurality of nodes into a lock group such that nodes of the lock group are locked together. Identification of a first group of the nodes to form the lock group is received. The method includes storing the object with the first group of the nodes forming the lock group. A method includes receiving identification of an object that includes a plurality of nodes. The object is modeled to provide for association of any of the plurality of nodes into a load group such that nodes of the load group are loaded together. Identification of a first group of the nodes to form the load group is received. The method includes storing the object with the first group of the nodes forming the load group.

Abstract: Systems and methods for temporarily adjusting the frequency of processors are disclosed. A computing device may include a plurality of processors that are each configured to execute one or more tasks at a corresponding one of a plurality of frequencies. A scheduling component migrates tasks between the processors to balance a load that is processed by the plurality of processors. A governor component includes a frequency adjustment component to control a frequency of each of the processors and a frequency synchronization component that detects when the scheduling component is migrating one of the tasks from a source processor to a destination processor. The synchronization component increases, based upon a frequency of the source processor, a frequency of the destination processor.

Abstract: Disclosed are various embodiments for determining a source of malware. At least one embodiment of a method includes receiving browsing data from a plurality of client devices, the data being sent by the plurality of client devices, in response to a determination of malware on the plurality of client devices and determining, from the browsing data, a source for the malware. Further, some embodiments include determining whether the source for the malware is associated with a predetermined network site and in response to determining that the source of the malware is associated with a predetermined network site, preventing download of at least a portion of the predetermined network site.

Abstract: Capacity and spectrum constrained, multiple-access communication systems optimize performance by selectively discarding packets. Changes in the communication systems may be driven using control responses. Control responses include intelligent discard of network packets under capacity constrained conditions. Packets are prioritized and discard decisions are made based on the prioritization. Various embodiments provide an interactive response by selectively discarding packets to enhance perceived and actual system throughout, provide a reactive response by selectively discarding data packets based on their relative impact to service quality to mitigate oversubscription, provide a proactive response by discarding packets based on predicted oversubscription, or provide a combination thereof. Packets may be prioritized for discard using correlations between discards and bandwidth reduction and quality degradation. The quality degradation for video packets may be measured objectively.

Abstract: The present image forming apparatus includes a first control unit and a second control unit driven by built-in clock oscillators to realize the distributed control. The first control unit generates, using a first timer driven by the built-in clock oscillator of the first control unit, a pulse signal corresponding to a predetermined clock rate and outputs the pulse signal to the second control unit. The second control unit measures, using a second timer driven by the built-in clock oscillator of the second control unit, a pulse width of the pulse signal outputted from the first control unit, and calculates a correction coefficient using reference pulse width corresponding to the predetermined clock rate and the measured pulse width. The processing unit processes using the calculated correction coefficient.

Abstract: A portable handheld device includes an image sensor for capturing an image; an orientation sensor for determining a rotation of the image sensor; and a system-on-chip processor having integrated on a common wafer a CPU for processing a script language, a multi-core processor for processing an image captured by the image sensor, and a common synchronization register. The multi-core processor includes multiple processing units connected in parallel by a crossbar switch. Each processing unit stores one or more synchronization bits for identifying which of the other processing units are functioning as a single process therewith. The common synchronization register contains therein synchronization bits from each of the processing units.

Abstract: A time synchronization method and system for a multi-core system are provided.

Abstract: Asset management systems and methods are presented. In one embodiment, a system includes a computing resource associated with a project member. A project container is stored on the computing resource, wherein the project container comprises encrypted objects related to a project. The encrypted objects includes project metadata and one or more working objects associated with one or more sub-projects of which the project member is granted permissioned access. An encryption/decryption engine is included for encrypting and decrypting the encrypted objects. The system includes an archive file system for storing the encrypted objects and previous versions of the objects, and a façade file system for viewing and accessing and interacting with the one or more working objects. Other computing resources associated with other project members are similarly configured, wherein a plurality of project containers store distributed objects that are grouped within the project.

Abstract: A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.