Abstract: Disclosed are various embodiments for determining a source of malware. At least one embodiment of a method includes receiving browsing data from a plurality of client devices, the data being sent by the plurality of client devices, in response to a determination of malware on the plurality of client devices and determining, from the browsing data, a source for the malware. Further, some embodiments include determining whether the source for the malware is associated with a predetermined network site and in response to determining that the source of the malware is associated with a predetermined network site, preventing download of at least a portion of the predetermined network site.

Abstract: The present image forming apparatus includes a first control unit and a second control unit driven by built-in clock oscillators to realize the distributed control. The first control unit generates, using a first timer driven by the built-in clock oscillator of the first control unit, a pulse signal corresponding to a predetermined clock rate and outputs the pulse signal to the second control unit. The second control unit measures, using a second timer driven by the built-in clock oscillator of the second control unit, a pulse width of the pulse signal outputted from the first control unit, and calculates a correction coefficient using reference pulse width corresponding to the predetermined clock rate and the measured pulse width. The processing unit processes using the calculated correction coefficient.

Abstract: Capacity and spectrum constrained, multiple-access communication systems optimize performance by selectively discarding packets. Changes in the communication systems may be driven using control responses. Control responses include intelligent discard of network packets under capacity constrained conditions. Packets are prioritized and discard decisions are made based on the prioritization. Various embodiments provide an interactive response by selectively discarding packets to enhance perceived and actual system throughout, provide a reactive response by selectively discarding data packets based on their relative impact to service quality to mitigate oversubscription, provide a proactive response by discarding packets based on predicted oversubscription, or provide a combination thereof. Packets may be prioritized for discard using correlations between discards and bandwidth reduction and quality degradation. The quality degradation for video packets may be measured objectively.

Abstract: A portable handheld device includes an image sensor for capturing an image; an orientation sensor for determining a rotation of the image sensor; and a system-on-chip processor having integrated on a common wafer a CPU for processing a script language, a multi-core processor for processing an image captured by the image sensor, and a common synchronization register. The multi-core processor includes multiple processing units connected in parallel by a crossbar switch. Each processing unit stores one or more synchronization bits for identifying which of the other processing units are functioning as a single process therewith. The common synchronization register contains therein synchronization bits from each of the processing units.

Abstract: A time synchronization method and system for a multi-core system are provided.

Abstract: Asset management systems and methods are presented. In one embodiment, a system includes a computing resource associated with a project member. A project container is stored on the computing resource, wherein the project container comprises encrypted objects related to a project. The encrypted objects includes project metadata and one or more working objects associated with one or more sub-projects of which the project member is granted permissioned access. An encryption/decryption engine is included for encrypting and decrypting the encrypted objects. The system includes an archive file system for storing the encrypted objects and previous versions of the objects, and a façade file system for viewing and accessing and interacting with the one or more working objects. Other computing resources associated with other project members are similarly configured, wherein a plurality of project containers store distributed objects that are grouped within the project.

Abstract: A transmission system which couples a plurality of transmission devices to a control device includes a first transmission device which is one of the plurality of transmission devices; a first calculation circuit which calculates a first difference value indicating a frequency difference value between a common clock supplied from the control device and a first clock as a clock used in the first transmission device; and a transmitter which reports the first difference value to a second transmission device other than the first transmission device, wherein the second transmission device comprises: a second calculation circuit which calculates a second difference value indicating a frequency difference value between the common clock and a second clock used in the second transmission device, and a frequency controller which controls an oscillator generating the second clock so that the second difference value approaches the first difference value reported from the first transmission device.

Abstract: A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.

Abstract: According to one embodiment, a computer-implemented method for execution on one or more processors includes receiving a first file and determining a file type of the first file. The method also includes determining, according to a first policy, a plurality of malware detection schemes to apply to the first file based on the determined file type of the first file. In addition, the method includes scheduling the application of the determined plurality of malware detection schemes to the first file amongst a plurality of detection nodes according to a second policy. Further, the method includes determining, in response to determining the results of applying the plurality of malware detection schemes, that the first file is malware or determining that the first file is suspected malware according to a third policy.

Abstract: Embodiments of the present disclosure provide a PCIe interface module and a physical layer to negotiate a link by exchanging a number of fast training sequences (N_FTS). The physical layer may count the number of good FTSs exchanged during an initial or a subsequent link training. The number of FTSs to be exchanged during a subsequent link training may be a number in which a maximum initial number of fast training sequences to be exchanged is reduced by the number of good FTSs exchanged during the initial link training, reducing link training time and increasing efficiency.

Abstract: A processor time synchronization apparatus and method in a data communication system which includes a plurality of processors and line interfaces. The processor time synchronization apparatus includes a first local processor configured to recognize a time difference between an external device and the system based on a time message exchanged with the external device, and synchronize time between the external device and the system, and a second local processor configured to receive time information from the first local processor that has been time-synchronized with the external device, the time information containing the time difference between the external device and the system, and synchronize the first local processor with a system's internal time using the received time information.

Abstract: Provided is a communication circuit (10) connected with a plurality of function blocks (A, B) that perform processing based on a first clock signal, and mediates communication between the function blocks (A, B). The communication circuit (10) includes N number of communication means, where N is a positive integer, having the same data width as communication data output from the function blocks, and each of the N number of communication means performs communication processing based on N number of second clock signals specified by 1/N of a frequency of the first clock signal, respectively corresponding to the N number of communication means and having a phase difference of 360/N degrees from each other. This makes it possible to provide a communication circuit between function blocks in which the amount of necessary hardware and power consumption is small, the timing design is easy, and the communication latency is low.

Abstract: A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

Abstract: Device authentication is based on the ability of a human to synchronize the movements of his or her fingers. A pairing procedure for two wireless devices may thus involve a synchronization test that is based on the relative timing of actuations of input devices on each of the wireless devices. In some aspects a synchronization test involves determining whether actuations of user input devices on two different wireless devices occurred within a defined time interval. In some aspects a synchronization test involves comparing time intervals defined by multiple actuations of user input devices on two wireless devices.

Abstract: A processor-based system, including systems without keyboards, may receive user inputs prior to booting. This may done using the graphics controller to generate a window which allows the user to input information. The system firmware may then compare any user inputs, such as passwords, and may determine whether or not to actually initiate system booting.

Abstract: A multi-processor system includes a first processor that includes a first time base counter that outputs a first time base count, a second processor that includes a second time base counter that outputs a second time base count, and a communication bus. The first and second processors exchange the first and second time base counts on the communication bus. The first and second processors determine a skew based upon a difference between the first and second time base counts, and the first and second processors synchronize with each other based upon the skew.

Abstract: In a method of identifying a globally consistent state in a multithreaded program, a plurality of locally consistent states is identified, in which a locally consistent state of a thread comprises a set of memory locations and their corresponding data values accessed between points in the multithreaded program where no locks are held. Globally consistent states are identified based at least in part on the locally consistent states.

Abstract: An electric device is capable of operating in a normal operation mode and a power save operation mode. The electric device includes a first processor for processing information input externally in the normal operation mode, and a second processor for processing an internal operation of the electric device in the normal operation mode. The second processor consumes power smaller than that of the first processor. In the electric device, power of the first processor is restricted through a restriction process in the power save operation mode. Further, in the power save operation mode, the second processor restricts the internal operation and processes the information input externally. When the second processor detects the information input externally, power of the first processor is released through a restriction releasing process.

Abstract: Techniques for synchronizing data object instances between applications/processes in an efficient manner. In one set of embodiments, the techniques described herein can be implemented in one or more network routers to synchronize data between a process running on an active management processor and a process running on a standby management processor, thereby facilitating features such as non-stop routing (NSR).

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor.

Abstract: In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC value after the system suspension, and directly updating a thread offset value associated with a first thread executing on a first core of the processor with the stored TSC value, without performing a synchronization between a plurality of cores of the processor. Other embodiments are described and claimed.

Abstract: The invention refers to a method for synchronizing clocks in a communication network, wherein a first clock of a first network element (MA) which is a master element is used for synchronizing second clocks of one or more second network elements which are slave elements. According to the method of the invention, a first sequence of first messages transmitted from the first network element to the second network element and/or a second sequence of second messages transmitted from the second network element to the first network element is recorded. First messages and/or second messages out of those sequences are identified by using an appropriate threshold function with respect to the transmission delays of those messages. Those identified messages have the same constant minimum delay, and based on those messages clock synchronization between the first clock and the second clock is performed.

Abstract: A mechanism for synchronizing states of components in a first routing engine to corresponding components in a second routing engine is provided. In order to reduce the amount of data required to synchronize the state of the components and the time and resources required to perform the synchronization, the state-related information transmitted from the first routing engine to the second routing engine is limited to information used to build states of a subset of the components associated with the first routing engine. That subset of components is limited to those components that receive stimuli (e.g., data streams or data packets) from sources external to the routing engine. Other components on the second routing engine synchronize state by receiving information from those components on the second routing engine that received the external stimuli information.

Abstract: A method and apparatus for printing using a synchronization signal are provided. Printing processes are performed in the apparatus by determining points in time for performing the printing processes based on a synchronization signal so that it is possible to reduce a waiting time for printing.

Abstract: A processing unit is connected to another processing unit through a system bus composed of serial signal communication line and synchronization signal communication line to be able to communicate therewith. When an operation unit detects abnormal state in the processing unit, the operation unit supplies notification of detection of the abnormal state to synchronization unit. The synchronization unit transmits the received detection notification of abnormal state to the other processing unit through the synchronization signal communication line. Conversion unit receives parallel communication data from the operation unit through important signal line instead of general signal line and converts the received parallel signal into serial signal to be transmitted to the other processing unit through the serial signal communication line, thereby soundness among processing units connected to the system bus is ensured when the system bus is configured to attain serial communication.

Abstract: Methods and systems for operating a wireless clock system for multimedia datastream transmission and display. Source clock frames are compared with a reference clock frames and the clock difference are transmitted to a wireless clock receiver which also receives the same reference clock frames. Source clock frames are re-constructed using the reference clock frames, clock difference information and the receiver's local clock system.

Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

Abstract: A synchronization control apparatus includes a counter that carries out a counting and outputs resulting count information, a timeout time holder that holds a predetermined timeout time and outputs the timeout time, a comparator that compares the count information output from the counter and the timeout time output from the timeout time holder, a synchronization controller that monitors a synchronization between a first processor and a second processor by comparing an output from the first processor and an output from the second processor and starts a counting, when a mis-match of the outputs from the first processor and the second processor is detected and wherein the comparator detects that the count information and the timeout time match, the comparator stops either the first processor or second processor in which a synchronization delay has occurred.

Abstract: The present technology provides a method, system and computer program product for managing the synchronization of a mobile electronic device, wherein management and adjustment of the synchronization process can be provided at least in part on a session by session basis. The synchronization process may be configurable via a user interface. Aspects of the user interface, such as prompts or degree of user configurability, may be adjusted depending on one or more factors, such as link effective speed or expected synchronization time.

Abstract: In certain embodiments, a circuit for transferring signals from a source clock domain to a destination clock domain comprises a first pulse generation circuit, a hold flip-flop circuit, a clocked synchronizer circuit and a second pulse generation circuit. The first pulse generation circuit, operable in the source clock domain, generates a source data pulse from a source data signal. The hold flip-flop circuit, operable in the source clock domain, is configured to hold the source data pulse. The clocked synchronizer circuit, operable in the destination clock domain, samples the source data pulse received from the hold flip-flop circuit, where source data pulse held at the output of the hold flip-flop circuit is cleared when the source data pulse is sampled by the clocked synchronizer circuit. The second pulse generation circuit, operable in the destination clock domain, is configured to generate a destination data pulse from the sampled source data pulse.

Abstract: Various techniques are provided for hosting storage media devices using multi-port devices having a plurality of ports. For example, in one embodiment, a method of operating a multi-port device includes detecting whether a host device or a storage media device is connected to a first port of the multi-port device or a second port of the multi-port device. The method also includes, if the host device is connected to the first port, configuring the first port as a slave port and operating the multi-port device as a slave hosted by the host device. The method also includes, if the host device is connected to the second port and the storage media device is connected to the first port, configuring the first port as a host port and hosting the storage media device from the multi-port device.

Abstract: A plurality of barrier blades, a barrier blade identification information storage unit, and a barrier blade identification information selection unit are provided. The plurality of barrier blades synchronize, using a synchronization address set for a plurality of arithmetic processing units, the plurality of arithmetic processing units. The barrier blade identification information storage unit holds barrier blade identification information to identify the barrier blade corresponding to synchronization address identification information to identify the synchronization address, for each of the plurality of arithmetic processing units. When synchronization address identification information is input, the barrier blade identification information selection unit selects and outputs barrier blade identification information corresponding to the input synchronization address identification information, among barrier blade identification information held by the barrier blade identification information storage unit.

Abstract: Methods simulating a system of devices are described. A model that simulates the system is executed. The system model includes a plurality of modules. A clock object for a module can be disabled when it is not needed or not being used.

Abstract: A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at a second post cursor; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: Method, system, and computer program product embodiments for synchronizing workitems on one or more processors are disclosed. The embodiments include executing a barrier skip instruction by a first workitem from the group, and responsive to the executed barrier skip instruction, reconfiguring a barrier to synchronize other workitems from the group in a plurality of points in a sequence without requiring the first workitem to reach the barrier in any of the plurality of points.

Abstract: Generating monotonically increasing time-of-day values in a multiprocessor system is provided. Synchronization impulses are received by a processor of the multiprocessor system, and an execution of a read instruction of a time-of-day value within a processor of the processors is refused, if the execution of the read instruction of the time-of-day value is requested after a predefined time after a synchronization impulse of the synchronization impulses, and if a trigger signal, indicative of new data received by a related memory system, has been received after the predefined time, wherein the memory system is external to the processor.

Abstract: Each of the plurality of second processing units includes: a counter that counts a count value in synchronization with such a counter included in each remaining second processing unit; a register that holds the count value of the counter; and a control unit that stores the count value, which is counted by the counter when receiving a measurement instruction from the first processing unit, as a receipt-timing count value into the register and notifies the first processing unit of the held receipt-timing count value, and the first processing unit calculates one or more differences between a plurality of the receipt-timing count values notified from the second processing units as a transmitting delay difference from the first processing unit to each of the plurality of second processing units.

Abstract: The present invention provides a serializer/deserializer (SERDES) circuit that can cover both client- and network-side interfaces for high-speed data rates. The present invention leverages commonality between the client and network (also known as line) side, and accommodates differences in a flexible manner. In one exemplary embodiment, the present invention provides a four-channel implementation to meet the requirement of both interfaces. The SERDES circuit can be capable of supporting both 40 Gb/s and 56 Gb/s data rates, can include an integrated DQPSK pre-coder and I/Q input/output signals, and can support RZ clock recovery. Additionally, the SERDES circuit can include differential coding support, electronic pre-emphasis, receiver-side electronic dispersion compensation, and the like.

Abstract: In one embodiment, a network system according to the present invention is a network system in which a plurality of image forming apparatuses are communicably connected via a network, and an electronic device capable of independent operation is communicably connected to each of the plurality of image forming apparatuses. The electronic device includes a data input/output unit that sends/receives control data of the electronic device to/from the image forming apparatus to which the electronic device is connected, and the image forming apparatus includes a data communications unit that sends/receives the control data to/from the electronic device connected to the image forming apparatus, and a network communications unit that sends/receives the control data to/from another image forming apparatus via the network.

Abstract: Technologies are generally described for a multi-processor core and a method for transferring threads in a multi-processor core. In an example, a multi-core processor may include a first group including a first core and a second core. A first sum of the operating frequencies of the cores in the first group corresponds to a first total operating frequency. The multi-core processor may further include a second group including a third core. A second sum of the operating frequencies of the cores in the second group may correspond to a second total operating frequency that is substantially the same as the first total operating frequency. A hardware controller may be configured in communication with the first, second and third core. A memory may be configured in communication with the hardware controller and may include an indication of at least the first group and the second group.

Abstract: A synchronization apparatus synchronizing an operation of a first processing unit pre-processing an input signal and an operation of a second processing unit post-processing on signal from the first processing unit, may include: a counting unit that operates with a period sufficiently shorter than a period of a first reference signal governing timing of pre-processing in the first processing unit, and outputting, when counting a set target count value, a second reference signal governing timing of post-processing in the second processing unit; a phase control unit that generates a control value controlling a phase difference of the second reference signal with respect to the first reference signal in accordance with a count value when the first reference signal is input; and a filter unit that filters the generated control value so as to determine the target count value to be set in the counting unit.

Abstract: A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.

Abstract: A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12P, 12C) that are otherwise configured to communicate over an address-based network (18). Sync signals (46, 56) are generated for each of producer and consumer circuits (12P, 12C) from the address information encoded into requests that communicate the data streams output by the producer circuit (12P) and expected by the consumer circuit (12C). The sync signals (46, 56) for the producer and consumer circuits (12C) are then used to selectively modify the data stream output by the producer circuit (12P) to a format expected by the consumer circuit (12C). Typically, such modification takes the form of inserting data into the data stream when the consumer circuit (12C) expects more data than output by the producer circuit (12P), and discarding data communicated by the producer circuit (12P) when the consumer expects less data than that output by the producer circuit (12P).

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: The a massively parallel computer including a plurality of CPUs to implement barrier synchronization by using a global barrier synchronous counter, wherein the CPUs each comprises a computation core including a GBF cache which caches a part of a plurality of global barrier synchronous flags for controlling synchronization between the CPUs, and a communication control unit including the global barrier synchronous flag, when making a request for reference to the global barrier synchronous flag, the computation core first referring to the GBF cache and only when the reference has a cache miss, making a request to the communication control unit to refer to the global barrier synchronous flag.

Abstract: A method, apparatus and computer program product are present for performing a manufacturing procedure. A component may be positioned in a work area. A plurality of groups of robots may be operated in parallel and robots of each group of robots of the plurality of groups of robots may be operated in synchronism for performing a plurality of manufacturing operations at a plurality of locations on the component.

Abstract: A time synchronization system includes a host system, a BIOS module, a BMC module, and a RTC module. The BIOS module is embedded in the host system. The BMC module is connected with the BIOS module and communicates with the BIOS module. The RTC module communicates with the BMC module and provides time signals to the BMC module. The host system acquires the time signals from the BMC module through the BIOS module.

Abstract: A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.

Abstract: A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.