Abstract: The high-speed barrier synchronization is completed among multiprocessors by saving overhead for parallel process without addition of a particular hardware mechanism. That is, the barrier synchronization process is performed by allocating the synchronization flag area, on the shared memory, indicating the synchronization point where the execution of each processor for completing the barrier synchronization is completed, updating the synchronization flag area with the software in accordance with the executing condition, and comparing, with each processor, the synchronization flag area of the other processors which takes part in the barrier synchronization.

Abstract: A method, apparatus and computer instructions for application based tracing and for normalization of processor clocks in a symmetric multiprocessor environment. By deliberately establishing a large skew among processor clocks, it is possible to perform application based tracing by directly using the processors. In addition, the identity, time stamp, and drift information of each processor may be used to create a time library. The time library is used to adjust a measured time to execute a program or software routine. The adjusted time is a normalized time that is statistically more accurate than the measured time alone. The adjusted time is then reported as the time to execute the program or software routine.

Abstract: A method and system for serial communication capable of increasing the speed of the transmission of serial data are provided. A block mode is employed if transmission of serial data having a specific length is required, and under which data to be transmitted are divided into plural blocks, and firstly transmitted is block information that notifies which blocks out of the entire blocks will be transmitted, and then transmitted are the data included in the blocks notified by the block information. The burst mode is a mode under which the block information which is currently transmitted is compared with the block information which was previously transmitted, and, if the two are the same, transmission of the data is introduced, while the block information being omitted. The system attached mode information notifying the mode through which data will be transmitted, to the data to be transmitted.

Abstract: A recording medium and a method and apparatus for managing data are provided. The method includes recording additional data in a data file separate from a file containing main data and recording navigation information that links the main data and the additional data. The additional data are segmented into a plurality of predetermined units, each of the predetermined units including time information indicating a presentation start time of the corresponding unit.

Abstract: A method for synchronizing data utilized in a redundant, closed-loop feedback control system is disclosed. In an exemplary embodiment, the method includes configuring a plurality of control nodes within the control system, with each of the plurality of control nodes transmitting and receiving data through a common communication bus. At each of the plurality of control nodes during a given control loop time T=N, the receipt of externally generated data with respect to each control node is verified, the externally generated data having been generated during a preceding control loop time T=N?1. At each of the plurality of control nodes during the given control loop time T=N, output control data is calculated using the externally generated data. During the given control loop time T=N, the calculated output control data from each individual control node is further transmitted over the communication bus to be later utilized by other control nodes during a subsequent control loop time T=N+1.

Abstract: A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. Temperatures may be computed at various points in the multiprocessor system by monitoring activity information associated with various subsystems. The activity measurements may be used to compute a current power dissipation distribution over the die. If necessary, the tasks in a scenario may be adjusted to reduce power dissipation.

Abstract: Timers of a plurality of slave units are synchronized with a timer of a master unit by a) sending a synchronization message on the first network by the master unit, which contains a time measurement of the master unit and a time scale, to the slave units; b) at each slave unit, forming the difference between a time measurement recorded in the slave unit and the time measurement received by the master unit, and correcting the current time measurement of the slave unit by this difference, and, at each unit, the recording of a time measurement upon receipt of the time scale; c) at the master unit, inserting the recorded time measurement into a subsequent synchronization message.

Abstract: A high-performance and miniaturizable duplexed processor system is provided. In communications between respective corresponding processor units on 0- and 1-system processor cards C0 and C1, a sequence number is added to transmission data to assess the continuity of the transmission data, and to thereby retransmit missing data. Also, in communications between processor units on the same processor card, interprocessor connection units PC0 and PC1 autonomously transfer data. Furthermore, each processor card is equipped with an input/output unit (an input/output switching unit and an input/output interface unit), so that each input/output switching unit IC0 and IC1 switches input data paths according to operating states of the processor card equipped therewith.

Abstract: A control system includes controllers that are coupled mutually by a communications network, on which information, transmitted from a master controller to a slave controller, is used to make timing corrections on the slave controller in order to synchronize event timers on the slave controller with that of the master controller. Timing accuracy for the occurrence of the event commanded by each controller is synchronized in narrow range of time, preferably within a few milliseconds depending on the specific application and system.

Abstract: A system and method for object rundown protection that scales with the number of processors in a shared-memory computer system is disclosed. In an embodiment of the present invention, prior to object rundown, a cache-aware reference count data structure is used to prevent cache-pinging that would otherwise result from data sharing across processors in a multiprocessor computer system. In this data structure, a counter of positive references and negative dereferences, aligned on a particular cache line, is maintained for each processor. When an object is to be destroyed, a rundown wait process is begun, during which new references on the object are prohibited, and the total number of outstanding references is added to an on-stack global counter. Destruction is delayed until the global reference count is reduced to zero.

Abstract: A system for synchronizing configuration information in a plurality of data processing devices using a common system interconnect bus. The present invention provides a method and apparatus for enforcing automatic updates to the configuration registers in various agents in the data processing system. A node controller is operably connected to a system interconnect bus and a switch. A plurality of interface agents are connected to the switch, with each of the interface agents comprising a configuration space register, a configuration space shadow register and a control and status register (CSR). A token ring connected to the node controller is operable to transmit data from the node controller to a plurality of interface agents connected to the token ring, thereby providing a system for updating the various configuration registers in each of the agents.

Abstract: A method and device for synchronizing the time between at least two integrated circuits (201, 202), which receive the same pulse signal. In the integrated circuits (201, 202) a counter (204, 206) is used to count the number of pulses in the received pulse signal to synchronize the common time between said integrated circuits.

Abstract: A method for synchronizing a plurality of processors within a computer system is provided. The computer system includes a plurality of processors that are each communicatively coupled to a respective network wherein each network is independent of each other network. The method includes receiving a plurality of input signals at a first rate from at least one source, transmitting the input signals to a reference object, and transforming the input signal to a known temporal reference. The apparatus is configured to receive a plurality of input signals at a first rate from at least one source, transmit the input signals to a reference object, and transform the input signal to a known temporal reference.

Abstract: An interface allows communication between a host device coupled to a host bus and a target device coupled to a target bus. First, the interface receives the address of the target device from the host device via the host bus, where the address has a first width. Next, the interface converts the received address from the first width into one or more address components each having a second width. Then, the circuit accesses the target device by driving the one or more address components onto the target bus. Such an interface allows for a simple, direct communication path between the host bus, such as a system bus, and a target bus, such as an LPC bus. The interface consolidates several tasks into one general purpose interface, providing savings in components used, design complexity, and overall cost of implementation. Further, the length of time required for communications between interfaced busses is substantially reduced.

Abstract: A plurality of processors are coupled together. One of the processors may comprise a default boot strap processor (“BSP”). Further, the default BSP may determine whether the BSP has local memory and becomes the BSP for the system if the default BSP has local memory, or selects another processor to be the BSP for the system if the default BSP does not have local memory.

Abstract: A mechanism synchronizes among processors of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a barrier synchronization mechanism that enables synchronization among processors of a column (i.e., different rows) of the systolic array. That is, the barrier synchronization function allows all participating processors within a column to reach a common point within their instruction code sequences before any of the processors proceed.

Abstract: Encryption synchronization (e-sync) is maintained between a transmitter (104) and one or more receivers (102) in a multi-modulation TDM system (100) where information is communicated in slots (402) comprising a slot header (404) and one or more data blocks (406), and wherein the data blocks are eligible to be encoded at different modulation rates thereby creating a likelihood of different numbers of blocks in different slots. The receiver and transmitter employ respective encryption elements (200, 300) comprising e-sync shifter elements (202, 302) and encryption algorithm blocks (204, 304). The e-sync shifter element provides an e-sync signal defining an encryption state vector to the encryption algorithm block and is operable to advance the encryption state vector (in the case of the receiver) according to a number of received bits plus a variable number of bits.

Abstract: A method for producing a computer-assisted real-time system that includes at least one processing unit. Data exchange between the processing unit and the environment or one or more additional processing units is synchronous or asynchronous. At least one real clock is allocated to the processing unit to correlate data exchange.

Abstract: There is provided a data synchronization system, data synchronization method, data center, and client terminal that allow a client terminal to determine whether data held by the client terminal is up-to-date and allow synchronization between a server and the client to be maintained at low costs in a case where synchronization between data in the server and data in the client terminal is provided.

Abstract: A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.

Abstract: Transition signal control for creating asynchronous timing is provided using a transition signal control circuit, which includes Muller C elements each with an inverter. The control device is constituted by a machine ring including n-stages of transition signal control circuits, a state ring including k-stages of transition signal control circuits, and a synchronous circuit for synchronizing with the machine ring by receiving a vector which is output from the state ring. When the output vector of the state ring is received, the synchronous circuit outputs a vector to the machine ring. The output vector of the machine ring and the output vector of the state ring create timings for controlling the processor, for example, asynchronously, and these timings are input to the instruction decoder, for example.

Abstract: The present invention relates to a method of synchronisation between communication networks exchanging information by frame of informations, each communication network having clock and the number of clock pulses is monitored by a counter. The synchronisation is made by reading information representing the counted clock pulses of the clock of the first network at the appearance of a reference event, inserting at least said information or calculated information on the basis of said information into the frame of information as the synchronisation information, transferring said frame of information from the first to the second network, reading information representing the number of counted clock pulse of the clock of the second network at the appearance of reference event, reading synchronisation information inserted in received frame of information from the first network, calculating a difference between information and synchronising the second network.

Abstract: A method for providing a message-time-ordering facility is disclosed. The method comprises initiating the message-timer ordering facility for a message at a sender system. Initiating includes setting a delay variable to zero. The message is sent to a receiver system in response to initiating the message-time-ordering facility. Sending the message includes marking the message with a first departure time-stamp responsive to a sender system clock and transmitting the message to the receiver system. The message is received at the at the receiver system, receiving includes delaying the processing of the message until the time on a receiver system clock is greater than the first departure time-stamp and recording a time associated with the delaying the processing of the message in the delay variable. A response to the message is sent to the sender system in response to receiving the message.

Abstract: System and method for maintenance and examination of timers for a computer system having connections in a networking system. Timer values in a connection table each indicate a timeout for a timer for a connection, where each connection has multiple timers, and one of the timer values is written to a global timer array for each connection such that the global timer array can be scanned to determine when timeouts occur for active connections. Sparse restart of a timer includes restarting the timer if data is communicated with a connected computer before the timeout occurs and after a predetermined time interval after timer start, and not restarting the timer if data is communicated before the timeout occurs and within the predetermined interval after timer start.

Abstract: A Computer based on a dual processing structure, with a main processing subsystem associated to an alternate processing subsystem. The main subsystem includes a main processor, a keyboard and a display, and the alternate processing subsystem has a quicker response time than the main processing subsystem. Additional multiplexing means are used for sharing said display and said keyboard between the two processing subsystems. The computer includes a powering control unit (40) for controlling the powering of the components of said main or said alternate processing subsystem, said powering control unit being controlled by a main power-on control and a alternate power-on control keys. The actuation on the main power-on control key causes the power-on control unit to power the two processors while actuating the alternate power-on control key causes the powering of the alternate processing subsystem only.

Abstract: A method is provided for synchronizing distributed processors. The method comprises determining a desired number of offset values between two processors, wherein each processor comprises a quartz crystal, determining parameters of a regression line, wherein the regression line is a function of the offset values over the desired number of offsets, and adjusting a synchronization interval according to the parameters.

Abstract: A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.

Abstract: A method for the synchronous control of several manipulators, such as several industrial robots, is characterized in that control units of specific manipulators exchange control information according to the data structures contained in a corresponding control program, through which control units to be synchronized and synchronization points in the control programs taking place there can be clearly identified, and in that on reaching and synchronization points the program sequence in the control units to be synchronized is continued according to the contents of the data structures in conjunction with the already exchanged control information or stopped until corresponding information arrives from other control units to be synchronized.

Abstract: To provide an integrated information processing unit that is capable of producing images and sounds of high quality. It includes a control unit, information processing units, and a merge unit. Each of the information processing units includes a counter for synchronization purpose. The information processing units performs a predetermined processing based on the measured value obtained by the counter for synchronization purpose. The control unit simultaneously provides a trigger of measurement of synchronization clocks to all counters for synchronization purpose and individually provides a reset signal to the counters for synchronization purpose which the reset signal is for initializing the measured value obtained by the counters for synchronization purpose. The merge unit merges information processed by the information processing units according to the unit of output (in frame) of, for example, a display device.

Abstract: Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between controllers in a distributed or localized control system, which is employed in order to allow operation of such controllers to be synchronized with respect to time. Also disclosed are synchronization protocols and hardware apparatus employed in synchronizing control operations in a control system.

Abstract: A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. Memory sharing is controlled to allocate the full bandwidth of the DSP memory to the PLCs and other DMA devices in proportion to their operating speeds. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers.

Abstract: A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.

Abstract: In a method for adaptive synchronization of a data sink device to a data source device coupled by a USB, data is received and stored in a buffer of the sink device at an average data rate representative of the data rate of the source device. A data level for the buffer is determined based on input packet size and output packet size. An accumulated data level for the buffer is compared with a threshold level. A clock frequency for the sink device is corrected when the accumulated data level exceeds the threshold level.

Abstract: A system and method for synchronizing a plurality of main processors. At a first time and in response to a first time reference, a first rendezvous signal is sent from a first to a second of the plurality of main processors. At a second time, and in response to a second time reference, a second rendezvous signal is sent from the second of the plurality of main processors, to the first of said plurality of main processors. After the first rendezvous signal is received by the second of the plurality of main processors and the second rendezvous signal is received by the first of said plurality of main processors, substantially simultaneous scanning of control information is initiated by the first and second of the plurality of main processors. In variations, a difference between the first and second times signals a fault condition.

Abstract: A method and system that synchronizes time-related data in a digital processing system. The data to be synchronized includes display data such as audio or video data and command data such as uniform resource locators. The data is encoded with time indicators that allow the media data, through the execution of a set of instructions, to be processed synchronously with the display data.

Abstract: A method and a system for saving the local clock of a data processing area of a multicellular platform, configured from a management tool as a data processing server on a partitionable machine. For the management tool and each data processing area, an absolute reference clock is established. For each area comprising a local clock managing an operating activity, there is calculated and stored a backup attribute containing at least one time shift parameter of the parameters for management of the local time with respect to the absolute reference clock. For the subsequent execution of the operating activity on a successive different data processing area, parameters for management of the time of this activity with respect to the absolute reference clock are recalculated. The successive local clock, associated with the successive different data processing area is updated, prior to the launching of the operating activity to continue execution.

Abstract: A method for time synchronization of a computer network by a main computer, in which case, for synchronization with an N-th interrupt, a time signal corresponding to the instant of the interrupt plus a time interval between the interrupts is transmitted on an ATM bus and the secondary computers to be synchronized set their clock to this transmitted time signal with the next interrupt.

Abstract: In multiprocessor systems the task of holding power dissipation to its lowest possible level is challenging. This invention permits reduced power dissipation by optionally independently clocking selected central processing units at lower frequencies if they are not fully loaded. The variable clocking system enables synchronization between central processing units operating a differing frequencies and shared memory and peripherals. This allows for significant power reduction in the frequently occurring scenario where all processors are not driven to their limits by prevailing system requirements.

Abstract: A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates signals in response to receiving clock signals from a clock source. A second timer detects the presence or absence of signals from the first timer and in response to an absence outputs a circuit reset signal to a circuit. The circuit in turn issues a reset signal to the PLL and to other systems.

Abstract: An integrated circuit device includes a receiver, a register and a clock circuit. The receiver samples data from an external signal line in response to an internal clock signal. The register stores a value that represents a timing offset to adjust the time at which the data is sampled. The clock circuit generates the internal clock signal such that the internal clock signal maintains a controlled timing relationship with respect to an external clock signal. The clock circuit includes an interpolator that phase mixes a set of reference clock signals such that the internal clock signal is phase offset in accordance with the value.

Abstract: A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.

Abstract: An apparatus comprising a first plurality of parallel switches and a second plurality of parallel switches. The first plurality of parallel switches may be configured to control a voltage on a first output pin. The second plurality of parallel switches may be configured to control a voltage on a second output pin. The first and second pluralities of parallel switches may be configured to provide rise time control of a differential waveform and be driven by a phased data signal.

Abstract: A peer-to-peer protocol is based on the use of global timestamps and client priorities in serializing modifications to a shared workspace of real-time collaboration. The method caters to dynamic clients wherein a client can leave or join an ongoing collaboration session as long as there is always at least one client present/remaining in the collaboration session. The method can support multiple definitions of a modification, including partitioning-based definitions, wherein the method provides full support for locking of partitions, and a full treatment of inter-partition synchronization via a modification definition over multiple partitions. The method is capable of utilizing the many standard methods of creating a global, distributed, synchronized clock for the global timestamps utilized by it. The method is rollback-based for correcting tentative but incorrect serializations, and provides additional backup in terms of checkpoints for additional safety and for the support of lightweight, pervasive clients.

Abstract: In the case of a data bus for several users, the users have hierarchical transmission authorizations; the users are synchronized by a synchronization signal; and the communication of the user with the highest priority, which can be emitted at regular time intervals by this user, serves as a synchronization signal.