Abstract: A system for transitioning from a first logical state to any second logical state of a plurality of logical states includes a first circuit. The first circuit is associated with a first clock domain. The first circuit includes a first state machine. The first state machine includes a plurality of logical states. Each of the plurality of logical states is associated with a plurality of physical states. A single state element in one of the plurality of physical states associated with a first logical state is modified to transition from the first logical state to any second logical state.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between controllers in a distributed or localized control system, which is employed in order to allow operation of such controllers to be synchronized with respect to time. Also disclosed are synchronization protocols and hardware apparatus employed in synchronizing control operations in a control system.

Abstract: A system may be employed for allowing the synchronous operation of an asynchronous system. The system may be a system that may include multiple clusters. The clusters may include asynchronous clock domains and may also receive a global clock signal through a global clock grid that may overlay the system. Furthermore, a method may be employed for synchronizing asynchronous clock domains within a cluster. The method of synchronizing may include providing a global clock that corresponds to a global clock grid to each cluster. Additionally, the method of synchronizing may include accounting for the mismatch between the asynchronous clock domains by employing logic in a block.

Abstract: A synchronization control apparatus includes a counter that carries out a counting and outputs resulting count information, a timeout time holder that holds a predetermined timeout time and outputs the timeout time, a comparator that compares the count information output from the counter and the timeout time output from the timeout time holder, a synchronization controller that monitors a synchronization between a first processor and a second processor by comparing an output from the first processor and an output from the second processor and starts a counting, when a mis-match of the outputs from the first processor and the second processor is detected and wherein the comparator detects that the count information and the timeout time match, the comparator stops either the first processor or second processor in which a synchronization delay has occurred.

Abstract: Digital logic processing devices capable of reduced power consumption may be provided. A digital logic processing device may include one or more processing elements, an input FIFO for storing data, a processing unit, and a clock controller circuit. The processing unit may process data from the input FIFO and the clock controller circuit may control a clock signal supplied to the input FIFO and the processing unit. The clock controller circuit may monitor whether there is data to be transferred to the input FIFO and states of the input FIFO and the processing unit and may control the clock signal.

Abstract: A microprocessor system includes a plurality of microprocessors which are connected to one another by signaling technology. In order to temporally synchronize the microprocessors in a relatively simple manner, it is proposed in at least one embodiment that provision be made of a central clock generator which outputs a clock signal in the form of temporally successive pulses to all microprocessors in a parallel manner, that provision be made of a master which can switch the output of the clock signal on and off, that all microprocessors sum the clock signal from the central clock generator in the form of a counter reading in each case, that the master be able to reset the counter readings of all microprocessors. In at least one embodiment, in order to synchronize all microprocessors, the master first of all interrupt the output of the clock signal, then set all counter readings to a defined value, and then cancel the interruption of the output of the clock signal again.

Abstract: Nodes in a network include a pseudo-timestamp in messages or packets, derived from local pseudo-time clocks. When a packet is received, a first time is determined representing when the packet was sent and a second time is determined representing when the packet was received. If the difference between the second time and the first time is greater than a predetermined amount, the packet is considered to be stale and is rejected, thereby deterring replay. Because each node maintains its own clock and time, to keep the clocks relatively synchronized, if a time associated with a timestamp of a received packet is later than a certain amount with respect to the time at the receiver, the receiver's clock is set ahead by an amount that expected to synchronize the receiver's and the sender's clocks. However, a receiver never sets its clock back, to deter attacks.

Abstract: Updating timers of central processing units (CPUs) in a multiprocessor apparatus involves the repeated performance of update operations by a device that is coupled to the CPUs via a memory interface. The operations include selecting one of the plurality of CPUs and determining an offset value that estimates a delay time to process a timer update at the selected CPU. A corrected timer value of the selected CPU is determined based on the offset value and a reference time.

Abstract: A computer implemented method, apparatus, and computer program product for managing symmetric multiprocessor interconnects. The process identifies functional communication connections between each processor in a plurality of processors on a multiprocessor to form identified functional communication connections. The process maps every functional communication connection between any two processors in the plurality of processors, based on the identified functional communication connections, to form an interconnect matrix. The process creates a path map using the interconnect matrix. The path map comprises a sequence of communication connections between the plurality of processors. The process initializes the plurality of processors using the path map.

Abstract: Systems and methods that vary multiple data sampling rates, to collect sets of data with different levels of granularity for an industrial system. The data for such industrial system includes sets of data from the “internal” data stream(s) (e.g., history data collected from an industrial unit) and sets of data from an “external” (e.g., traffic data on network services) data stream(s), based in part on the criticality/importance criteria assigned to each collection stage. Each set of data can be assigned its own unique data collection rate. For example, a higher sample rate can be employed when collecting data from the network during an operation stage that is deemed more critical (e.g., dynamic attribution of predetermined importance factors) than the rest of the operation.

Abstract: The invention relates to the use of history information as an aid to synchronization in a peer-to-peer system. In particular, node trees are used to represent portions of files systems designated for synchronization. The nodes in the node tree embody history information regarding associated objects. The history information includes version vectors that are used to simplify synchronization-related comparisons and create job lists that may be used to bring participating peers into synchronization.

Abstract: The invention relates to a process for digital, bidirectional data transmission between a processing unit and a position encoder, as based on the transmission of frames of a predetermined bit length, such that each frame is provided with at least an initial bit length for the transmission of data from the processing unit to the position encoder and at least a second bit length for the transmission of data from the position encoder to the processing unit; and such that the frame is provided with a time slot in which data is neither transmitted from the processing unit to the position encoder nor from the position encoder to the processing unit. In the time slot a triggering signal (external sync signal) is transmitted from the processing unit to the position encoder and this triggers the acquisition of position data.

Abstract: A timing system is disclosed for use in a wireless communication system that includes wireless transceiver and a digital baseband processing system. The timing system includes a primary clock generation system that provides a low frequency clock that is used as the reference clock for a digital signal processing system, which generates low frequency timing signals, and a secondary clock generation system that provides a high frequency clock that is used by the wireless transceiver to produce high resolution timing signals to control the timing of the wireless transceiver. The high resolution timing signals are commenced responsive to a low resolution timing signal.

Abstract: A method is provided for estimating a frequency offset value. This method includes: receiving a signal from the transmitting device at the receiving device, the received signal having a transmitter frequency (510); generating a local signal at the receiving device, the local signal having a starting frequency (520); comparing a received signal phase and a local signal phase to determine an adjusted error signal representing a phase difference between the received signal and the local signal (530); adjusting a current frequency of the local signal from the starting frequency to the transmitting frequency over a time period (540); integrating the adjusted error signal over the time period to generate an integrated error signal (550); and filtering the integrated error signal to generate a frequency difference estimate indicative of the frequency difference between the transmitter frequency and the starting frequency (560).

Abstract: A master station includes a group of circuits for performing an optimization method. In such a system, the optimization is achieved by adjusting the pull-up resistance and by setting the best possible clock frequency to ensure that data/clock high and low voltage levels are within predetermined specifications. An optimization procedure is performed in a calibration phase invoked by a user or a system whenever a change is introduced to the system, such as addition or deletion of slave stations, a change of data/clock lines, or a change that may affect on the electrical and timing characteristics of the two-wire communication system.

Abstract: Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.

Abstract: A method and a computer system for making a computer achieve high availability. The method includes running a host virtual machine on a host virtual machine container; running a servant virtual machine on the servant virtual machine container; and synchronizing the host virtual machine and the servant virtual machine by using an I/O instruction. The system includes at least two computers including a host computer and a servant computer, each computer including a virtual machine container; a virtual machine running on the virtual machine container; and a communication channel making the virtual machine container execute a virtual machine synchronization operation. The virtual machine synchronization operation of the virtual machine container is triggered by the virtual machine executing I/O instructions.

Abstract: A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD clock with TOD clocks of other computer systems. The computer system comprises a memory; and, a processor in communications with the computer memory.

Abstract: Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may provide synchronized clock distribution for a first destination while the dependent synchronization circuit may provide synchronized clock distribution to a second destination. A method for synchronized clock distribution to a plurality of destinations is also described.

Abstract: A serial interface circuit includes a first circuit disposed in the core portion and connected to the CPU, and a second circuit disposed in the peripheral circuit and connected to the peripheral registers and the first circuit; the first circuit including mirror registers, shift registers, in the write operation, serially outputting write data to the second circuit, and in the read operation, serially receiving read data supplied from the second circuit, and a first control block, in the read operation, generating a timing signal for writing the read data held in the shift registers into the corresponding mirror registers; the second circuit including shift registers and a second control block generating a second timing signal for either writing the write data held in the second shift register into the corresponding peripheral register or outputting data held in the peripheral register to the second shift register.

Abstract: One or more methods and systems of effectively transmitting voice and voice band data from one node to another are presented. In one embodiment, the system comprises an NTP time server generating absolute times to computing devices such as residential voice over internet protocol (VoIP) gateways. The NTP time server generates absolute times in response to NTP time requests made by one or more computing devices such as residential VoIP gateways. In one embodiment, the method comprises determining an adequate rate for requesting absolute times from an NTP server, making periodic requests to the NTP server, obtaining the absolute times from the NTP server, and generating an adjustment parameter for use by a computing device such as a residential VoIP gateway.

Abstract: Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.

Abstract: A method of storing data from a plurality of processors comprising the steps of (a) transferring data along a first bus (b) connectable between a first processor and a synchronising means and operable with a first protocol; (c) synchronising the synchronising means with a second processor; and (d) transferring the data along a second bus to a memory of the second processor wherein the second bus is connectable between the synchronising means and the memory of a second processor and operable with a second protocol.

Abstract: In one embodiment, an apparatus comprises one or more processors and a controller coupled to the processors. Each processor comprises at least one processor time stamp counter (TSC) and a first control unit configured to maintain the processor TSC. The controller comprises at least one controller TSC and a second control unit configured to maintain the controller TSC. The controller is configured to signal the processor responsive to determining that the processor TSC is out of synchronization with the controller TSC. In response to having been signalled that the processor TSC is out of synchronization, the processor is configured to resynchronize the processor TSC to the controller TSC before generating a result for a read TSC instruction. In response to having not been signalled that the processor TSC is out of synchronization, the processor is configured to generate the result responsive to the processor TSC without resynchronizing.

Abstract: Core clock alignment circuits include a serial-in parallel-out (SIPO) data processing circuit, which is configured to generate a plurality of lanes of deserialized data in response to a corresponding plurality of lanes of serialized data. The SIPO data processing circuit is further configured to generate a plurality of recovered clock signals from corresponding ones of the plurality of lanes of serialized data. These recovered clock signals may be out-of-phase relative to each other. The devices also include a plurality of lane FIFOs, which are configured to receive respective ones of the plurality of lanes of deserialized data and respective ones of the plurality of recovered clock signals at write ports thereof. A core clock alignment circuit is provided, which may be electrically coupled to the plurality of lane FIFOs.

Abstract: A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value.

Abstract: This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into circuits (ICs) as used in mobile phones, PDAs or laptop computers. To reduce power consumption, the processor clock rates are often varied depending on the current performance requirements. Differing clock rates of processors sharing a non-volatile memory leads to relatively long read access times of the latter, since the particular microprocessor fetching the data from the memory is usually halted until the data are available. When dual or multi-port non-volatile memory and multiple asynchronous clocks are used, access times are even longer since clock synchronization between the ports is necessary. The present invention overcomes this problem by providing a plurality of wait timers, preferably one dedicated to each processor, advantageously each being clocked synchronously with its associated processor.

Abstract: A system and method are provided which add, via an add-on module, synchronization functionality to an instrument that does not otherwise support such synchronization functionality. Various synchronization techniques may be supported by the synchronization module. For instance, in certain embodiments the synchronization module supports message-based synchronization techniques and/or time-based synchronization techniques. Accordingly, in certain embodiments, the add-on module supports synchronization with another device (e.g., another instrument or another add-on module coupled to an instrument) via synchronized local clocks (e.g., IEEE 1588) and messaging over a communication network. In certain embodiments, the add-on module additionally or alternatively supports the use of “time bombs” to trigger scheduled actions on the instrument with which the synchronization module is interfaced.

Abstract: A method and a device for synchronization in a multiprocessor system having at least two processors, switchover means being provided which make it possible to switch between at least two operating modes, the device being designed in such a way that a synchronization is performed using a stop signal which stops a processor running ahead in order to synchronize it with the at least [one] second processor.

Abstract: In a first aspect, a first method of synchronizing a plurality of processors of a system is provided. The first method includes the steps of (1) modifying a peripheral component interconnect express (PCIe) protocol to include a completion status encode associated with a synchronization command that indicates whether a condition of the synchronization command is met; (2) providing a system including (a) a memory; (b) a first processor coupled to the memory; (c) a second processor; and (d) an interconnect coupling the second processor to the first processor and the memory; and (3) employing the modified PCIe protocol on the interconnect. Numerous other aspects are provided.

Abstract: A system and method to synchronize independent local clocks in multi-core processing system are disclosed. A shared counter or a shared memory/file is provided to establish a partial happened-before relationship (e1<e2 in the happened-before order if we know that the event e1 happened before the event e2) and a synchronizer device is utilized to generate a global time of events in threads or processes.

Abstract: According to an embodiment of the invention, a mobile communication apparatus includes: a first processor; a second processor; an intermittent receiver that is operated using the first processor; and a timer processing unit that is operated using the first processor and the second processor and configured to determine a start time of an operation thereof by performing a time-out control based on a timer, wherein the timer processing unit sets the timer so that a time-out occurs at a given timing, to perform a first function to be started at the given timing, and wherein the timer processing unit sets the timer so that a time-out occurs at a time when the intermittent receiver is operated, to perform a second function to be started at an arbitrary timing.

Abstract: An apparatus and a method for Automatic Repeat reQuest (ARQ) in a broadband wireless access system are provided. The method includes driving a timer which operates by a preset period to synchronize ARQ between the transmitter and a receiver; after transmitting data to the receiver without error, when a driving time of the timer expires, checking whether there is data to transmit to the receiver; when there is no data to transmit to the receiver, initializing the timer; and transmitting an ARQ reset message to the receiver. Hence, the air resource consumption and the power consumption in ARQ reset can be lowered by reducing unnecessary ARQ reset.

Abstract: A method for switching between two oscillator signals within an alignment element, wherein one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. Said method comprises the steps of: introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected; sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed; sending the virtual stepping signal to the output of the alignment element in the event of a failure in the master signal until a switch to the other oscillator signal as a new master signal is performed or until the first master signal becomes valid again.

Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, determine whether a user at a first client has a chat session already active at a second client with a third client in response to a request for initiation of a chat session for the user at the first client. If the user does already have a chat session active, the third client is notified that the first client replaces the second client in the chat session. Then chat data from the second client is copied to the first client, and a disconnect message is sent to the second client from first client. In various embodiments, the determination may be made by sending a query to a plurality of clients connected via a network or by sending a query to a server that serves the first client, the second client, and the third client. The copied chat data, which may include messages sent between the second client and the third client, is presented at the first client.

Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for providing a virtualized time base in a logically partitioned data processing system. A time base is determined for each one of multiple processor cores. The time base is used to indicate a current time to one of the processor cores for which the time base is determined. The time bases are synchronized together for the processor cores such that each one of the processor cores includes its own copy of a synchronized time base. For one of the processor cores, a virtualized time base is generated that is different from the synchronized time base but that remains synchronized with at least a portion of the synchronized time base. The processor core utilizes the virtualized time base instead of the synchronized time base for indicating the current time to the processor core. The synchronized time bases and the portion of the virtualized time base remaining in synchronization together.

Abstract: Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during system boot in a links-based multi-processor system. Some embodiments synchronize data block by block through memory rather than piece by piece through registers by allowing a System Bootstrap Processor (“SBSP”) to directly access synchronization data in local memory of each of one or more Application Processors. These and other embodiments are described in greater detail below.

Abstract: Fault-tolerant synchronization of real-time equipment connected to a computer network of several tens of meters with an option of including or not including such equipment in the synchronization device is disclosed. Global scheduling of the real-time computer platform in the form of minor and major cycles is provided in order to reduce latency during sensor acquisition. The associated calculation and preparation of output to the actuator is provided in an integrated modular avionic (IMA) architecture. To achieve the foregoing, a synchronization bus separate from the data transfer network and circuits interfacing with this specific bus for processing the local real-time clocks in each piece of equipment in a fault-tolerant, decentralized manner is provided.

Abstract: Hardware cells inside of an IC device, such as in a processor circuit, for characterization that replace functional flip-flops that capture inputs or drive outputs in the device. The cells are circuits that are used, in conjunction with a software method, to generate test programs for testing exact I/O transitions for timing measurements at various operating conditions.

Abstract: A method for coupling a collection of master devices on an Inter-Integrated Circuit (IIC) bus, where the collection of master devices includes at least one resident master device, generating a periodic, fixed interval tenure on the IIC bus, synchronizing at least one additional master device with the periodic, fixed interval tenure to enable the at least one additional master device to communicate on the IIC bus, and tuning a period value corresponding to a frequency of the periodic, fixed interval tenure to optimize the synchronizing, wherein the tuning further includes adjusting the period value to vary the frequency of the periodic, fixed interval tenure to balance between available IIC bus bandwidth and synchronization of the at least one additional master device.

Abstract: A system and computer program product for modifying an operation of one or more processors executing message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.

Abstract: Synchronizing multiple instances of an FIB in a network node that has a distributed processing architecture involves associating sequence numbers with all of the FIB entries that are stored with each instance of the FIB and using the sequence numbers that are associated with the FIB entries to determine the most current FIB entry. In one embodiment, the sequence numbers are used to determine the most current FIB entry among two matching FIB entries that have matching information (i.e., matching destination IP addresses and masks). In another embodiment, the sequence numbers are used to identify a line card with the most current FIB entry.

Abstract: A method and a device are provided for performing switching and data comparison in a computer system having at least two processing units which each process data at a specified clock pulse, in which a switchover arrangement is provided and switching takes place between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a compare mode is provided, and a second operating mode corresponding to a performance mode is provided. A synchronization arrangement is provided which assigns to the specifiable data a clock pulse information as a function of a processing unit, and at least the comparison unit takes into consideration this clock pulse information in the corresponding data.

Abstract: A method for synchronizing a first processor and multiple second processors is presented. In the method, each of the second processors waits at a second synchronization point after reaching a first synchronization point. The last of the second processors to reach the first synchronization point sends a signal to the first processor. The first processor waits at the first synchronization point until it receives the signal. After receiving the signal, the first processor initiates a launch of the second processors by launching at least one of the second processors. At least one of the second processors launched by the first processor launches another of the second processors in response to being launched by the first processor. Each of the second processors continues execution from the second synchronization point in response to being launched.

Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.

Abstract: A duplex system has duplicated processor devices. Each of the processor devices has a first copying section which writes data written in a memory of the processor device, into a same address of a memory of the other processor device, a second copying section which divides all data in the memory of the processor device to sequentially write all data into the memory of the other processor device periodically, an error detecting section which checks the data written in the memory of the processor device, and an error check register which sets an error bit when the error detecting section detects an error. After the first copying section and the second copying section write data into a memory of the standby side processor device, the control side processor device checks an error bit of an error check register of the standby side processor device.

Abstract: Rank numbers specified by a second counter are refreshed in sequence by using a count value of a first counter which is initialized by a synchronous reset signal and counts timing for performing refresh, and the rank numbers specified by a refresh rank control unit are continuously refreshed in sequence in the case where the synchronous reset signal is active.

Abstract: A mechanism for synchronizing states of components in a first routing engine to corresponding components in a second routing engine is provided. In order to reduce the amount of data required to synchronize the state of the components and the time and resources required to perform the synchronization, the state-related information transmitted from the first routing engine to the second routing engine is limited to information used to build states of a subset of the components associated with the first routing engine. That subset of components is limited to those components that receive stimuli (e.g., data streams or data packets) from sources external to the routing engine. Other components on the second routing engine synchronize state by receiving information from those components on the second routing engine that received the external stimuli information.

Abstract: The present invention is a method and mechanism of multiple processors synchronization. Calling global memory fence (GMF) service raises asynchronous memory fence being executed on other processors. By guarantee that asynchronous memory fence (AMF) or equivalence on other processors are executed within the window of global memory fence (GMF) service call, the expensive memory ordering semantics can be removed from the critical path of frequently-executed application code. Therefore, the overall performance is improved in modern processor architectures.