Abstract: Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.

Abstract: In a system in which a first computer transmits data to a second computer, the first computer transmits data conveying time information to the second computer, with the information expressing a first time point that occurs prior to commencement of the transmission and, following reception of the time information, the second computer compares the first time point information with a current time point, to thereby obtain a communication delay amount that includes a delay in transmitting data from the first to the second computer.

Abstract: A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including multiple cores. The system reference oscillator clock frequency provides a reference frequency to a local oscillator. The local oscillator supplies a core clock frequency to at least one of the cores. The method further includes adjusting the local oscillator to output the core clock frequency at a frequency greater than the system reference oscillator clock frequency as a function of digital frequency characteristic data associated with the core or cores. The method supports extendibility to larger systems and may support enhanced power management through frequency adjustments at the core level.

Abstract: A processing unit is connected to another processing unit through a system bus composed of serial signal communication line and synchronization signal communication line to be able to communicate therewith. When an operation unit detects abnormal state in the processing unit, the operation unit supplies notification of detection of the abnormal state to synchronization unit. The synchronization unit transmits the received detection notification of abnormal state to the other processing unit through the synchronization signal communication line. Conversion unit receives parallel communication data from the operation unit through important signal line instead of general signal line and converts the received parallel signal into serial signal to be transmitted to the other processing unit through the serial signal communication line, thereby soundness among processing units connected to the system bus is ensured when the system bus is configured to attain serial communication.

Abstract: In one embodiment, an apparatus comprises one or more processors and a controller coupled to the processors. Each processor comprises at least one processor time stamp counter (TSC) and a first control unit configured to maintain the processor TSC. The controller comprises at least one controller TSC and a second control unit configured to maintain the controller TSC. The controller is configured to signal the processor responsive to determining that the processor TSC is out of synchronization with the controller TSC. In response to having been signalled that the processor TSC is out of synchronization, the processor is configured to resynchronize the processor TSC to the controller TSC before generating a result for a read TSC instruction. In response to having not been signalled that the processor TSC is out of synchronization, the processor is configured to generate the result responsive to the processor TSC without resynchronizing.

Abstract: Systems and methods that can vary a data collection rate via a rate adjustment component, to collect data with different level of granularity. The rate adjustment component can further include an estimation component that can automatically predict a required sampling rate for a stage of an operation, based on statistical models and data collected for similar operations and/or history data. Such difference in the granularity level can initiate in part in response to fault detection, alert triggering, and the like. Accordingly, future trouble shooting efforts can be performed with respect to data that is typically collected at an adjustable rate.

Abstract: A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.

Abstract: A system for pre-execution environment (PXE) booting a storage processor from a peer storage processor allows for the ability to reboot and/or restart the storage processor without an externally connected PXE server. In response to a reboot request of the storage processor, the peer storage processor pushes an operating system boot image and/or other information to the storage processor for PXE booting the storage processor, and vice versa. The system may also operate with multiple coupled computers.

Abstract: Full-duplex communication over a communication link between an initiator operating with an initiator clock and a target operating with a target clock involves, in communication from the initiator to the target: storing data from the initiator in a first FIFO memory with the initiator clock, reading data from the initiator stored in the first FIFO memory, wherein reading is with the target clock transmitting the data read from the first FIFO memory over a first mesochronous link, and storing the data transmitted over the first mesochronous link in a buffer whereby the data are made available to the target. Communication from the target to the initiator includes: transmitting data from the target over a second mesochronous link, and storing the data transmitted over the second mesochronous link in a second FIFO memory, wherein storing is with the target clock, whereby the data are made available to the initiator for reading from the second FIFO memory with the initiator clock signal.

Abstract: Updating timers of central processing units (CPUs) in a multiprocessor apparatus involves the repeated performance of update operations by a device that is coupled to the CPUs via a memory interface. The operations include selecting one of the plurality of CPUs and determining an offset value that estimates a delay time to process a timer update at the selected CPU. A corrected timer value of the selected CPU is determined based on the offset value and a reference time. The corrected timer value is written to a cache line of the selected CPU to cause the selected CPU to update the timer of the selected CPU.

Abstract: Mechanisms for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.

Abstract: A programmable logic processor (PLC) with multiple PLC functions is disclosed. The PLC includes at least one memory storing at least one of a plurality of programs or data, and one or more processor assigned to each of the PLC function and couple to the memory. The PLC functions are run in parallel. A method of operating the PLC and a PLC system with multiple processors are also disclosed.

Abstract: Disclosed are a method of and system for digital frequency clocking in a processor core. At least one-processor core is provided, and that processor core has a clocking subsystem for generating an output clock signal, which may be an analog signal at a variable frequency. Digital frequency control data are transmitted or distributed to the processor core; and that one processor core receives the digital frequency control data transmitted to the core, and uses that received digital frequency control data to set the frequency of the output clock signal of the clocking subsystem of the processor core. Preferably, multiple cores are asynchronously clocked and the core frequencies are independently set, and, there is no phase relationship between the core clocks.

Abstract: A method and apparatus for hibernation booting in a mobile terminal supporting two processors are provided. In the hibernation booting method, when power is turned on, a master processor performs hibernation booting. A slave processor performs normal booting under control of the master processor. The master processor and the slave processor determine data needing synchronizing, and perform synchronization depending on whether the data needing synchronizing have been changed.

Abstract: Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.

Abstract: Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.

Abstract: In general, this disclosure describes techniques of ensuring cache coherency in a multi-processor computing system. More specifically, a relaxed coherency mechanism is described that provides the appearance of strong coherency and consistency to correctly written software executing on the multi-processor system. The techniques, as described herein, combine software synchronization instructions with certain hardware-implemented instructions to ensure cache coherency.

Abstract: An operating system in a virtual environment can obtain the current time of the processor that the OS is utilizing through a method for synchronizing timers on multiple processors with a standard reference time, such as the Coordinated Universal Time (UTC). A hypervisor controlling the processors obtains a number of synchronization values that, together with a local timer counter value, are utilized by the guest operating system to determine the physical processor time.

Abstract: A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices.

Abstract: Methods and apparatus are provided for generating interrupts associated with the completion of data processing. An external host may pass a first data block to a first processing engine and later pass a second data block to a second processing engine. In typical implementations, the external host expects that processing of the first data block completes first. To prevent errors and faults on the part of the external host, an interrupt associated with the processing of the second data block completing first is collapsed onto the first data block.

Abstract: A method and a device are provided for performing switching and data comparison in a computer system having at least two processing units which each process data at a specified clock pulse, in which a switchover arrangement is provided and switching takes place between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a compare mode is provided, and a second operating mode corresponding to a performance mode is provided. A synchronization arrangement is provided which assigns to the specifiable data a clock pulse information as a function of a processing unit, and at least the comparison unit takes into consideration this clock pulse information in the corresponding data.

Abstract: There is provided a serial reception circuit that can suppress the occurrence of a bit error due to long-period jitter while suppressing the power consumption. A serial reception circuit for receiving a serial signal in synchronization with a clock signal samples the serial signal in synchronization with multiphase sampling clock signals out of phase with the clock signal, determines based on sampled signals that a sampling phase having little effect of phase variation of the serial signal on a sampling result is an optimum phase, performs a reception operation in which a signal sampled by the optimum phase is reception data, and has, as determination operations for the optimum phase, a first mode and a second mode in which optimality of an optimum phase determined in the first mode is determined based on a sampling result of a reduced number of samplings.

Abstract: A method for tracking memory changes includes defining a change-track area of memory including at least one memory address range for which changes will be tracked. The method also includes allocating a protected log region of memory for storing a change-track log and selecting an operational mode for change tracking from among a plurality of modes, the selected operational mode having criteria for tracking memory changes. The method includes detecting memory transactions using a memory logging module and generating a transaction record for each memory transaction that occurs in the change-track are of memory and which meets the criteria. The transaction records can be stored in the change-track log.

Abstract: A unit and method for clock changeover in a system having at least two processing units, in which switchover device(s) are provided by which a switchover between at least two operating modes of the system is able to be implemented in which a clock pulse changeover is carried out in at least one processing unit in a switching of the operating mode.

Abstract: A processor-based system, including systems without keyboards, may receive user inputs prior to booting. This may done using the graphics controller to generate a window which allows the user to input information. The system firmware may then compare any user inputs, such as passwords, and may determine whether or not to actually initiate system booting.

Abstract: Method of controlling a wind power system comprising a plurality of system elements, the wind power system including a plurality of data processors distributed in the system elements, the method includes the steps of: synchronizing at least a part of the data processors to at least one reference signal distributed to the data processors from a time synchronization arrangement, associating the data processors with local clock generation circuitries, wherein the local clock generation circuitries associated with data processors of a first subset of the data processors have a peak-to-peak tracking jitter higher than or equal to a predetermined threshold value and wherein a second subset of the data processors have a peak-to-peak tracking jitter less than the predetermined threshold value, controlling at least one of said system elements at least partly by mechanism of a data processor from said first or second subset of data processors.

Abstract: A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.

Abstract: A distributed cache management system that minimizes invalid cache notification events is provided. A cache management system in a sending device processes outgoing cache notification events by adding information about the source server's clock. A cache management system in the receiving device then uses this information to adjust event information once the event is received.

Abstract: Method and apparatus for sampling a high-speed digital signal include providing a data signal to a differential data input circuit, an offset control signal, and a strobe pulse. In response to the strobe pulse, the data signal is resolved into an output logic state based to a relatively greater extent on the differential data signal and to a relatively lesser extent on the offset control signal.

Abstract: Simply constituted electronic apparatus that can definitely output an outputted data after predetermined length of time from a time when an inputted data processing is started, even if data processing time of the inputted data varies with the contents of the data.

Abstract: A method, computer program product, and system are provided performing a Message Passing Interface (MPI) job. A first processor chip receives a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system. The arrival signals identify when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job. Responsive to receiving the set of arrival signals from the set of processor chips, the first processor chip identifies a fastest processor chip of the set of processor chips whose arrival signal arrived first. An operation of the fastest processor chip is modified based on the identification of the fastest processor chip. The set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system.

Abstract: An audio data processing device including: a first processor; and a second processor which is connected to the first processor wherein the first processor includes: an audio data acquisition which acquires audio data of digital data; an omitting section which omits a bit corresponding to low volume which is hard to be heard by human ears from the audio data; and a transmitter which transmits the audio data in which the bit corresponding to the low volume is omitted by the omitting section from the first processor to the second processor; wherein the second processor includes: a receiver which receives the audio data transmitted from the first processor; and a reproduction data generator which generates audio reproduction data necessary to reproduce the audio data based on the received audio data.

Abstract: A data processing system ensures maximum reaction times. A novel and significantly improved way of ascertaining, checking and/or observing maximum reaction times in data processing systems includes complex or distributed, safe and/or nonsafe systems, particularly between a safe input signal and the corresponding safe output signal, in a flexible and universally applicable manner. Input and/or output data, which are present on the input side of users incorporated in the system, are read in synchronously during each data cycle and checked in relation to currency parameters, which are based on at least one data cycle and associated with the input and/or output data An error is identified in response to a defined discrepancy being reached between at least one currency parameter and a defined currency threshold, and a defined function, particularly a safety-oriented function, are triggered in response to identification of an error.

Abstract: A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.

Abstract: Resources may be dynamically allocated in a distributed processing portable electronic communication device. The dynamic allocation may include receiving an instruction to process an audio processing task related to audio data; determining whether resources for processing the processing task are available at a first processing unit; performing the audio processing task by the first processing unit when the resources are determined to be available, the audio processing task obtaining processed audio data; and providing the processed audio data synchronously with a global synchronization pulse so that the phase of the audio data is controlled.

Abstract: A method for operating cooperating, differing devices, particularly of a plant, with different controls controlling the control sequences and in particular with different control cycles, is characterized in that the clocks (IPOi) of the different controls (3.1, 3.2, 3.3) are interpolated on a common system clock (tTick) and that the control sequences are synchronized. An apparatus suitable for performing the inventive method correspondingly has at least one common interpolating device (5.3) for the controls (3.1, 3.2, 3.3) for interpolating the cycles (IPOi) of the different controls (3.1, 3.2, 3.3) on a common system clock (tTick) and at least one synchronizing device (5) for synchronizing the control sequences.

Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: Techniques are disclosed for synchronizing multiple clock sources of a system, and may include: determining time of a first clock at a first and second time instants; determining time of a second clock at a third time instant occurring between the first and second time instants, and a fourth time instant occurring after the second time instant; and determining a clock offset between the first and second clocks based on the determined times. The first and/or second clocks may be adjusted based on the clock offset to synchronize clock operation. This adjusting can be used, for instance, to synchronize operation of an audio and/or video component operating according to the first clock with an audio and/or video component operating according to the second clock. The techniques may further include determining if the clock offset is valid (e.g., based on detection of perturbing events or difference between a clock's times).

Abstract: Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage.

Abstract: Among other things, techniques and systems are disclosed for syncing data between a client device and a server. Synchronizing data includes initiating a sync session by negotiating a sync mode between a client device and a server for each of one or more dataclasses. A status code is generated based on a result of the negotiating. Based on the generated status code, the client device and the server exchanges one or more data items to be updated for the one or more dataclasses using the negotiated sync mode for each dataclass. The exchanged one or more data items are updated at the client device or the server The updated one or more data items are committed at the client or the server.

Abstract: In a serial communication system in which data is transmitted from a first unit to a second unit in synchronization with a clock signal, the mode of communication between the first and second units is switched between a first communication mode in which data is transmitted from the second unit to the first unit in synchronization with the clock signal, and a second communication mode in which a signal asynchronous to the clock signal is transmitted from the first unit to the second unit.

Abstract: A method and apparatus for efficiently executing nested transactions is herein described. Hardware support for execution of transactions is provided. Additionally, through the use of logging previous values immediately before a current nested transaction in a local memory and storage of a stack of handlers associated with a hierarchy of transactions, nested transactions are potentially efficiently executed. Upon a failure, abort, or invalidating event/access within a nested transaction, the state of variables or memory locations written to during execution of the nested transaction are rolled-back to immediately before the nested transaction, instead of all the way back to an original state of the variables or memory locations before an enclosing transaction. As a result, nested transactions may be re-executed within enclosing transactions, without flattening the enclosing and nested transactions to re-execute everything.

Abstract: A system for transitioning from a first logical state to any second logical state of a plurality of logical states includes a first circuit. The first circuit is associated with a first clock domain. The first circuit includes a first state machine. The first state machine includes a plurality of logical states. Each of the plurality of logical states is associated with a plurality of physical states. A single state element in one of the plurality of physical states associated with a first logical state is modified to transition from the first logical state to any second logical state.

Abstract: Disclosed is a system and method for improving the linearity of a clock and data recovery (CDR) circuit. In one embodiment, a data stream is received, and the phase of a clock signal is adjusted using two interpolators. The phase of the output signal of the second interpolator is adjusted simultaneously with, and complementary to, adjusting the phase of the first interpolator. The first interpolator's output signal is injected into a first delay cell in a delay loop having a plurality of delay cells, and the output of the second interpolator is inactivated. When the maximum phase of the first interpolator's output signal is reached, the second interpolator's output signal is injected into another one of the delay cells, and the first interpolator's output signal is inactivated. The data stream is then recovered using the output of the delay loop as a clock signal.

Abstract: Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between controllers in a distributed or localized control system, which is employed in order to allow operation of such controllers to be synchronized with respect to time. Also disclosed are synchronization protocols and hardware apparatus employed in synchronizing control operations in a control system.

Abstract: A system may be employed for allowing the synchronous operation of an asynchronous system. The system may be a system that may include multiple clusters. The clusters may include asynchronous clock domains and may also receive a global clock signal through a global clock grid that may overlay the system. Furthermore, a method may be employed for synchronizing asynchronous clock domains within a cluster. The method of synchronizing may include providing a global clock that corresponds to a global clock grid to each cluster. Additionally, the method of synchronizing may include accounting for the mismatch between the asynchronous clock domains by employing logic in a block.

Abstract: A synchronization control apparatus includes a counter that carries out a counting and outputs resulting count information, a timeout time holder that holds a predetermined timeout time and outputs the timeout time, a comparator that compares the count information output from the counter and the timeout time output from the timeout time holder, a synchronization controller that monitors a synchronization between a first processor and a second processor by comparing an output from the first processor and an output from the second processor and starts a counting, when a mis-match of the outputs from the first processor and the second processor is detected and wherein the comparator detects that the count information and the timeout time match, the comparator stops either the first processor or second processor in which a synchronization delay has occurred.

Abstract: Digital logic processing devices capable of reduced power consumption may be provided. A digital logic processing device may include one or more processing elements, an input FIFO for storing data, a processing unit, and a clock controller circuit. The processing unit may process data from the input FIFO and the clock controller circuit may control a clock signal supplied to the input FIFO and the processing unit. The clock controller circuit may monitor whether there is data to be transferred to the input FIFO and states of the input FIFO and the processing unit and may control the clock signal.

Abstract: A microprocessor system includes a plurality of microprocessors which are connected to one another by signaling technology. In order to temporally synchronize the microprocessors in a relatively simple manner, it is proposed in at least one embodiment that provision be made of a central clock generator which outputs a clock signal in the form of temporally successive pulses to all microprocessors in a parallel manner, that provision be made of a master which can switch the output of the clock signal on and off, that all microprocessors sum the clock signal from the central clock generator in the form of a counter reading in each case, that the master be able to reset the counter readings of all microprocessors. In at least one embodiment, in order to synchronize all microprocessors, the master first of all interrupt the output of the clock signal, then set all counter readings to a defined value, and then cancel the interruption of the output of the clock signal again.