Abstract: An apparatus and a system, as well as a method and article, may operate to independently adjust a plurality of processor clocks coupled to a corresponding plurality of networked processors responsive to one or more status indicators to provide scalable performance and power consumption. The status indicators may indicate the status of routers coupled to the processors. Additional apparatus, systems, and methods are disclosed.

Abstract: A method (which can be computer implemented) for processing a plurality of adjacent rows of data units, using a plurality of parallel processors, given (i) a predetermined processing order, and (ii) a specified inter-row dependency structure, includes the steps of determining starting times for each individual one of the processors, and maintaining synchronization across the processors, while ensuring that the dependency structure is not violated. Not all the starting times are the same, and a sum of absolute differences between (i) starting times of any given processor, and (ii) that one of the processors having an earliest starting time, is minimized.

Abstract: An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio.

Abstract: A bus system which transfers data from a first device to a second device includes a holding unit which holds data input from the first device, and a selecting unit which selects whether to output the data from the first device to the second device by holding the data by the holding unit or without holding the data by the holding unit.

Abstract: In a serial communication system in which data is transmitted from a first unit to a second unit in synchronization with a clock signal, the mode of communication between the first and second units is switched between a first communication mode in which data is transmitted from the second unit to the first unit in synchronization with the clock signal, and a second communication mode in which a signal asynchronous to the clock signal is transmitted from the first unit to the second unit.

Abstract: To detect a non-responsive condition at a processor, a counter is associated with an operation at a first stage of an instruction pipeline. A value stored in the counter is periodically adjusted towards a threshold value. An error indicator is provided in response to the value stored in the counter reaching the threshold value thereby indicating that a defined amount of time expired before a subsequent stage has completed processing of the operation. However, if the subsequent stage completes processing of the operation prior to the value stored in the counter reaching the threshold, the counter is automatically disassociated with the operation and can, therefore, be associated with another operation at the first stage of the pipeline. Accordingly, the counter does not use an explicit instruction that is responsible for resetting its value.

Abstract: The invention relates to a method for synchronizing a communications cycle and a communications node in a network. The node is formed with devices for receiving a desired value for a time base of a communications cycle of the communications node in a communications link to an additional communications node of the network. The node also includes devices for determining a system deviation between the desired value and an actual value of the time base, and a device for generating a manipulated variable for correcting the time base in accordance with the system deviation.

Abstract: Embodiments of the invention relate to synchronizing registers. An embodiment includes a plurality of processing cells each includes a plurality of CPUs, which run at different frequencies and each of which has an ar.itc timer register. A CPU in the fastest cell of the plurality of cells is referred to as the fast CPU. CPUs in slower cells are referred to as slow CPUs. At predetermined time intervals, slow CPUs are provided with the ar.itc value of the fast CPU to replace the values of their ar.itc. As a result, values in the ar.itc registers are synchronized without providing negative time. Other embodiments are also disclosed.

Abstract: A synchronous bit-serial data interface utilizes a transmitter that transmits a data stream having duplicates of each data bit. The receiver samples the data stream utilizing either the rising or falling edge of a received clock signal. If the rising edge is utilized the first duplicated bit is discarded and if the falling edge is utilized the second duplicated bit is discarded. The system allows transmitter/receiver pairs of devices that sample and latch data on the same clock edge to communicate.

Abstract: A method and apparatus to support communication between components in different clock domains having a rational clock frequency ratio of N/D. In one embodiment, a combination of integer phase generators are employed to produce phase control signals during an overall cycle having N phases, wherein the overall cycle is a combination of primary cycles having D phases and an adjustment cycle having R phases, wherein R is the remainder of N/D. For clock frequency ratios of less than 2:1, a combination of 2:1 and 1:1 phase generators are employed. Clocking signals are generated by phase generator logic to provide timing control between communicating components in the different clock domains. In one embodiment, the phase generator logic is implemented in a programmable phase generator.

Abstract: In processors having buffers to manage instruction flow referred to as a ReOrder Buffer (ROB) it is shown that these buffers are of the same approximate size of a checkpoint array for architected state. In a particular “morphing mode” in which a pair of processors can be configured to provide different functionalities on demand, a new “High-Reliability” (HR) mode is provided in which the ROB of one of the processors is used for a checkpoint array, and the pair of processors is made to run in lockstep on a single instruction stream under the control of the remaining ROB so as to provide redundant, hence highly-reliable computing.

Abstract: Interprocess buffer management is described. In an implementation, a method includes determining an amount of time to communicate a message and receive a response to the message by a first process from a second process. A buffer delay time is computed from the amount of time. Data from the first process is stored in a buffer. When the buffer delay time is reached, the buffer is sent to the second process.

Abstract: A method for transmitting data to a data line between a central control device and a decentralized data processing device. Input data of the decentralized data processing device is supplied to a processing unit of the decentralized data processing device in a first resolution. The processing unit carries out a transformation of the input data according to a calculation rule, and transmits the transformed data to the central control device by way of the data line in a second resolution. The central control device is used to determine, in the framework of a configuration of the decentralized data processing device, according to which calculation rule from a plurality of calculation rule, the decentralized data processing device is to carry out the transformation.

Abstract: An architecture for an integrated circuit with in-circuit programming allows real-time modification of the in-circuit programming code and other code stored on the chip. The architecture utilizes a microprocessor and control logic on an integrated circuit having a single non-volatile memory that stores instructions and data, such as in-circuit programming and user code, and input/output ports and related structure for exchanging data with an external device. Using in-circuit programming code stored on the chip, the chip interactively establishes an in-circuit programming exchange with an external device to update data and instructions including the in-circuit programming code. Input/output conflicts during in-circuit programming can be avoided by employing a code generator that supplies control routines to the microprocessor during at least part of the in-circuit programming operations. The code generator allows the in-circuit programming code to be updated in real time.

Abstract: Systems, methods and computer readable media for synchronization tasks and non-synchronization tasks being executed concurrently. In one exemplary embodiment, a method includes executing at least one user-level non-synchronization processing thread and executing at least one synchronization processing thread concurrently with the executing of the at least one user-level non-synchronization processing thread. The at least one user-level non-synchronization processing thread may include operations to access a first database which is synchronized by the at least one synchronization processing thread during a synchronization operation between the first database on a first processing system and a second database on a second data processing system.

Abstract: Bookmark synchronization methods, systems and computer readable media are described. One exemplary method includes storing a mapping relationship between a first topology for bookmarks of a first web browser on a host and at least one of an intermediate topology and a device topology for bookmarks of a second web browser on a device and storing a mapping relationship between the device topology and at least one of the intermediate topology and the first topology, and synchronizing bookmarks on the device with bookmarks on the host. Systems, computer readable media and other methods are also described.

Abstract: The present invention relates to a synchronization system that utilizes a synchronization wizard (“PullSync”) residing on a first computer device to request and receive (or “pull”) data from a second computer device. The first computer device (the “syncer”) copies files from shared folders on the second computer device (the “syncee”) in accordance with specific pull-synchronization rules (PSRs) established on the syncer that define the scope and extent of the synchronization. This copying occurs over a network connection using existing and well-defined protocols by which one computer system is able to view and copy files from the available shared folders of a second computer system, and the PullSync wizard software needs to exist only on the first computer system (the syncer) to utilize these existing networking protocols (including existing security/authentication protocols) to selectively copy files from the second computer system.

Abstract: A synchronization control apparatus includes a first processing block that performs a first process and outputs a first signal upon completion of the first process, a second processing block that can change processing speed according to electric power supplied thereto, performs a second process associated with the first process out of synchronization with the first processing block, and outputs a second signal upon completion of the second process, a control unit that determines an amount of the electric power to be supplied to the second processing block according to time difference between an input of the first signal and an input of the second signal, and a supply unit that supplies the electric power in the amount determined to the second processing block.

Abstract: One embodiment of the present invention provides a system that optimizes synchronization between monitored signals in a computer system. During operation, the system receives a number of monitored signals. The system then forms a number of signal pairs by grouping each signal with every other signal. Next, the system optimizes synchronization between the signals by iteratively perturbing the timing of each signal in an attempt to increase the value of an objective function which reflects the overall synchronization between all the signals.

Abstract: A device for transferring data signals between a first clock domain and a second clock domain comprises a serial memory element and a parallel memory element which are coupled. The serial memory element comprises at least one extra memory position more than the parallel memory element for the storage of the data signals.

Abstract: A fault-tolerant computer uses multiple commercial processors operating synchronously, i.e., in lock-step. In an exemplary embodiment, redundancy logic isolates the outputs of the processors from other computer components, so that the other components see only majority vote outputs of the processors. Processor resynchronization, initiated at predetermined time, milestones, and/or in response to processor faults, protects the computer from single event upsets. During resynchronization, processor state data is flushed and an instance of these data in accordance with processor majority vote is stored. Processor caches are flushed to update computer memory with more recent data stored in the caches. The caches are invalidated and disabled, and snooping is disabled. A controller is notified that snooping has been disabled. In response to the notification, the controller performs a hardware reset of the processors. The processors are loaded with the stored state data, and snooping and caches are enabled.

Abstract: A method of recovering timing information in a packet network is disclosed wherein a modulation scheme is used to transport additional information required for clock recovery between the sender and receiver across the network.

Abstract: A method for dynamic redundancy of processing units. The method includes defining at least one of, (i) an instruction, and (ii) a call, to idle a first processing unit. Both the instruction and the call are blocking operations that shall not return while a second processing unit and the first processing unit are paired together. The method further includes executing at least one of, (i) the defined instruction, and (ii) the call, and temporarily stopping the paired processing unit. Then, the method proceeds by synchronizing the state and enabling the redundant processor execution. Afterwards, the method includes restarting execution of both processing units together.

Abstract: An operating system in a virtual environment can obtain the current time of the processor that the OS is utilizing through a method for synchronizing timers on multiple processors with a standard reference time, such as the Coordinated Universal Time (UTC). A hypervisor controlling the processors obtains a number of synchronization values that, together with a local timer counter value, are utilized by the guest operating system to determine the physical processor time.

Abstract: A method for reducing radiation effects in an electronic circuit is disclosed. The method involves periodically transferring operation of the electronic circuit to at least one alternate processing element of a plurality of processing elements. With the at least one alternate processing element in control, the method reconfigures one or more processing elements of the plurality of processing elements. Once the one or more processing elements are reconfigured, the method synchronizes the one or more processing elements with the at least one alternate processing element.

Abstract: A method for remote control of devices. A remote control device receives a graphical user interface from a controlled device. The graphical user interface is periodically updated with controlled device data. The controlled device data is interrupted by command data from the remote control device. The controlled device responds to the command data and updates the graphical user interface.

Abstract: Described is a synchronization technique that may be used to coordinate processing between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message switch of the message fabric. Each processor is an endpoint within a data storage system. A first endpoint may mark the beginning of the synchronization period by specifying a processing point at which other processors and the first endpoint are to coordinate from the perspective of the first endpoint. Synchronization is performed using local state information about the processing state of each endpoint as reported by each endpoint. The first endpoint waits for successful synchronization within a timeout period in accordance with the first endpoint's local state information. If successful synchronization does not occur prior to the timeout period, the first endpoint broadcasts a message with a new synchronization point to other endpoints.

Abstract: A data interface is provided that can de-skew data signals by taking into account different skewing effects on each data signal. The data interface can be used, for example, in a communication system and can be configured to operate in one of three possible modes of operation. In the first mode, de-skewing is fixed prior to the sample logic. In the second mode, de-skewing is periodically changed automatically as the amount of skew changes based on training signals that are periodically sent into the data interface. The combination of the data phase count and the positive and negative clock width pulse counts will then determine where the final transition or edge of each data signal is to be placed within a bit. The third mode of operation involves an override or programmatic modification of the second mode of operation based on values stored in a register.

Abstract: According to one embodiment of the present invention, a novel method and system are disclosed. In one embodiment, a first node records a first node local time of receiving a wirelessly transmitted packet, the first node local time recorded with a monotonically increasing clock of the first node. The first node wirelessly transmits the recorded local time to at least a second node. The second node records a second node local time of receiving the wirelessly transmitted packet and records the first node local time of receiving the wirelessly transmitted packet. The second node updates a second node timing model to synchronize with the first node, the updating based on the second node local time of receiving the wirelessly transmitted packet and the first node local time of receiving the wirelessly transmitted packet.

Abstract: Disclosed is a method of distributing a number of reference clocks across a packet network. The packet network has a master node and one or more slave nodes, the master node and each slave node having basis clocks. A sender sends time-stamped synchronization packets to said one or more slave nodes, and a receiver at the slave nodes receives the time-stamped synchronization packets and synchronizes the basis clocks in the slave nodes with the basis clock in the master node. Multiple reference clocks are encoded with respect to the basis clock in the master node to generate numerical information describing the reference clock(s) in relation to the basis clock in the master node. The basis clock in each of the slave node is synchronized to the basis clock in the master node using time-stamped synchronization packets. The one or more reference clocks are recovered at the slave nodes using said numerical information describing the reference clock(s) in relation to the basis clock in the master node.

Abstract: A control apparatus for controlling a plurality of computers is described. The control apparatus includes a memory, a clock generator, a clock switch circuit, and a main module. The clock switch circuit switches between a system clock and a corresponding clock of a digital video signal. The main module directly stores the digital video signal into the memory according to the corresponding clock through the clock switch circuit. The main module reads the digital video signal from the memory according to the system clock. The main module also receives a remote control signal sent from a remote computer to control the plurality of computers.

Abstract: A method for synchronizing frame clocks in a plurality of processors comprises the steps of sending data packets from each of the processors to each of the other processors wherein each of the processors receives the data packets and identifies two of the data packets having the largest phase difference. The largest phase difference is used to determine a target synchronization phase angle, and the period of a frame clock is adjusted so that the frame clock approaches the target synchronization phase angle.

Abstract: A method of synchronizing timers in a wireless network is described. According to some embodiments, a master timer is sampled at the start time of a first beacon in a first data object and the sampled master timer value is broadcast in a second beacon of a second data object. A slave timer is sampled at the start of the second beacon in the second data object and a value representing the duration of the first data object is subtracted from the sampled slave timer value to determine an updated sampled slave timer value. According to some variations, a difference is determined between the sampled master timer value and the updated sampled slave timer value. The method then uses the difference to synchronize the slave timer to the master timer and to other slaver timers synchronized to the same master timer.

Abstract: The invention provides a method of synchronizing one or more devices on a first bus with one or more devices on a second bus. The method comprises acquiring timing information from the first bus and the second bus, determining a timing offset between the first bus and the second bus, and, broadcasting the timing offset to the one or more devices on the second bus so that the one or more devices on the second bus can adjust their timing to be synchronized with the one or more devices on the first bus.

Abstract: A clocking scheme is provided to synchronize system clock across plural independent SMP (Symmetric Multi-Processing) domains of the multi-processor system. Each of the SMP domains is connected with another through an interconnection board and two or more identical connectors. The clocking scheme includes a clock source, a SPLL (Select Phase-Locked Loop) and a clock buffer on each of the SMP domains to provide a dedicated base clock. A self-clock path is used to send the base clock from the clock source to the SPLL on the same SMP domain, and on the other hand one or more base clock is sent through a distribution-clock path to another SPLL.

Abstract: Disclosed is a method and apparatus for synchronizing data in a number of separate integrated circuits. In one embodiment, the apparatus includes a first integrated circuit configured to receive first data, and a second integrated circuit coupled to the first integrated circuit configured to receive second data. The second integrated circuit is separate from the first integrated circuit. The second integrated circuit is further configured to synchronize the second data with the first data. In another embodiment, the apparatus includes a first integrated circuit configured to receive first data, and a second integrated circuit coupled to the first integrated circuit configured to receive second data. The second integrated circuit is separate from the first integrated circuit. The second integrated circuit is further configured to detect when the second data is out of synchronization with the first data.

Abstract: An industrial control circuit includes: a first isolation circuit (22) for converting an analog signal to a low level voltage; a single-chip microprocessor SCM (23) for receiving the low level voltage from the first isolation circuit, and generating a control signal according to the low level voltage; and a second isolation circuit (24) for converting the control signal to a high level voltage. The SCM has at least thirty-two input/output (I/O) channels. Because the SCM used in the industrial control circuit has at least thirty-two I/O channels, the industrial control circuit can synchronously deal with sixteen-bit bidirectional communication.

Abstract: Disclosed is a method and apparatus for aligning clock domains over an asynchronous network between a source controlled by a first clock and a destination controlled by a second clock. The predicted delay is estimated for transmitting packets between a source and destination over the network. The time-stamped synchronization packets are sent to the destination, each time-stamped synchronization packet carries timing information based on a master clock at the source. A set of synchronization packets are received at the destination to create a set of data points, and the set of data points is weighted so that synchronization packets exhibiting a delay further from the expected delay are accorded less weight than synchronization packets exhibiting a delay closer to the expected delay. The expected delay is updated to create a current delay estimate based on the set of data points taking into account the different weighting of the data points.

Abstract: A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.

Abstract: A method for overload detection according to one embodiment of the invention includes a control process and a data process. In response to a timing signal, the control process sets a state of a timing indicator. Upon execution of a time-constrained operation, the data process checks the state of the timing indicator. In other embodiments, subsequent to an overload detection, an auxiliary data process is configured to execute in a mode that consumes fewer processing cycles.

Abstract: The invention relates to a method for synchronizing computer clocks in networks used for the transmission of information according to which information is dispatched with a time stamp when being dispatched and which is re-transmitted with a time stamp in a confirmation of receipt. The time stamps are inserted in the outgoing or arriving data packet by a clock module (8) mounted downstream of a network controller (4, 10) once said network controller has authorized transmission. A CPU (2) generates actuator signals that are provided with an identifier and that correct the clock modules (8) on the basis of a comparison between the time stamps in a confirmation of receipt of the addressee of the information and the time stamp of the corresponding transmitted information.

Abstract: In a distributed control system, a first electronic control unit sends trigger information to a second electronic control unit. The trigger information includes a timing that triggers the second electronic unit to obtain second sensor information from a second sensor. The second electronic control unit is designed to receive the trigger information, and obtain, at the timing of the trigger information, the second sensor information from the second sensor. The second electronic unit is configured to send, to the first electronic control unit, the obtained second sensor information.

Abstract: A method and communication system for exchanging data between at least two stations that are connected to one another via a distributed bus system, in which the data is contained in messages that are sent by the stations via the bus system. A common global time base, which at a predefinable instant is synchronized with an external reference time, and is provided for the stations of the bus system. To ensure reliable synchronization of the global time base with the external reference time, in particular without destroying the characteristics of the global time, (that is, without causing jumps in the global time base or a regressive global time), the stations of the communication system receive information regarding correction of the global time base, consent to a uniform correction value, and synchronously carry out external synchronization (that is, correction of the global time base).

Abstract: The present invention relates to a method of synchronization between communication networks exchanging information by frame of informations, each communication network having clock and the number of clock pulses is monitored by a counter the synchronization is made by reading information representing the counted clock pulses of the clock of the first network at the appearance of a reference event, inserting at least said information or calculated information on the basis of said information into the frame of information as the synchronization information, transferring said frame of information from the first to the second network, reading information representing the number of counted clock pulse of the clock of the second network at the appearance of reference event, reading synchronization information inserted in received frame of information from the first network, calculating a difference between information and synchronizing the second network.

Abstract: In a multiprocessor system that includes a plurality of processor modules, each one of which includes its own internal clock, one of the plurality of processor modules is designated as a master processor module having a master internal clock. Each other processor module is designated as a slave processor module having a slave processor module internal clock. Each slave processor module synchronizes its internal clock with the master internal clock.

Abstract: A lock-step synchronism fault-tolerant computer system includes a plurality of computing modules having a processor and a memory in which each computing module processes the same instruction string in synchronization with each other. When disagreement in a state of access to an external bus among the respective processors in each computing module is detected, if no fault is detected in the system including the respective computing modules, an interruption is notified to all of said processors. Synchronization among each computing module is recovered by adjusting timing of a response to an access which each processor executes by an interruption.

Abstract: A method and a system for synchronizing at least two users are described, each user to be synchronized containing its own timer, and the users being connected by at least one communications link, at least one event being transmitted for synchronization on the communications link, a first user determining a first view of the global time as a function of the event, and the at least one second user determining a second view of the global time as a function of the event, the minimum of the first and second views of the global time being transmitted through the corresponding users on the communications link, and each user to be synchronized determining an overall global time from the minimum of a first global time view and a second global time view, and the timer contained therein being synchronized with the overall global time.

Abstract: A method for time synchronisation of at least two clocks contained in a multiprocessor system, wherein a first clock having a predetermined clock rate generates consecutive respective time-stamps indicating the time and at least one second clock which has an adjustable clock rate is synchronised with the first clock at certain time intervals. At predetermined time intervals the relative temporal position of flanks of the first clock and of the second clock representing the transition between two consecutive time-stamps is recorded. From the change in the relative temporal position of the transition flanks of the first clock and of the second clock a correction factor representing the time deviation between the first clock and the second clock is determined. Using the correction factor representing the time deviation between the first clock and the second clock the clock rate of the second clock is readjusted in the sense of a diminution of the time deviation between the first clock and the second clock.

Abstract: Several algorithms are provided to estimate and remove relative clock skews from delay measurements based on the computation of convex hulls. The algorithms are linear in the number of measurement points for the case with no clock resets. For the more challenging case with clock resets, i.e., the clocks are reset to some reference times during the measurement period, linear algorithms are provided to identify the clock resets and derive the best clock skew lines. The algorithms are also extended to environments in which at least one of the clocks is controlled by Network Time Protocol. These algorithms can also be extended for active clock synchronization to replace or further improve Network Time Protocol.

Abstract: A method and apparatus are provided that allow processing engines to be synchronized to each other with high accuracy. In one embodiment, the invention includes obtaining a processor tick counter value from a first processing engine, comparing the obtained processor tick counter value to a processor tick counter value from a second processing engine and determining a timing offset for synchronizing the first processing engine and the second processing engine using the comparison. The invention may further include obtaining a processor tick counter value by sending a request message from the second processing engine to the first processing engine, and receiving a reply from the first processing engine at the second processing engine. The processor tick counter value at the second processing engine can be determined by recording the time at which the request message is sent and by recording the time at which the reply is received.