Using Delay Patents (Class 713/401)
  • Patent number: 10431292
    Abstract: Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Gregory A. King
  • Patent number: 10366188
    Abstract: An apparatus includes a processor and a memory configured to store design data used for disposition and wiring of a logic circuit on a programmable logic device, and store a table indicating a relationship between a power supply voltage value and a delay amount for each type of element in the logic circuit, the relationship having a nature to set the delay amount so as to increase in value as the power supply voltage value is smaller. The processor determines, as an optimum voltage value, a power supply voltage value at which the delay margin of a critical path indicates a desired value that is in the positive and is a minimum value. The processor outputs configuration information including the optimum voltage value and the design data so as to form the logic circuit on the programmable logic device supplied with a voltage determined by the optimum voltage value.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 30, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hideo Tsuji
  • Patent number: 10360959
    Abstract: Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device. Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David D. Wilmoth, Jason M. Brown
  • Patent number: 10355682
    Abstract: A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first phase clock signal and the second phase clock signal exhibiting non-overlapping logical high states; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to cause a difference between a first duration and a second duration within a clock cycle to be less than a predetermined tolerance.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tien-Chun Yang, Chih-Chang Lin, Ming-Chieh Huang
  • Patent number: 10355851
    Abstract: A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 16, 2019
    Assignee: Cornell University
    Inventors: Rajit Manohar, Sandra J. Jackson
  • Patent number: 10330724
    Abstract: A measurement arrangement and method for providing at least one combined measurement dataset, said measurement arrangement comprising at least one measurement device configured to generate measurement data in a measurement session, and a mobile device configured to generate measurement session context data of said measurement session, said measurement device and said mobile device being connected via at least one wireless link for data transfer, wherein the measurement data generated by said measurement device and associated measurement session context data generated by said mobile device are linked to provide a combined measurement dataset.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: June 25, 2019
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Philip Diegmann
  • Patent number: 10305497
    Abstract: According to one embodiment, in a semiconductor integrated circuit of a DLL circuit, in a delay chain, a plurality of delay elements are connected. A first detection circuit detects a group corresponding to a certain delay amount among a plurality of groups obtained by dividing the delay chain. A second detection circuit detects a delay element corresponding to the certain delay amount among a plurality of delay elements included in the detected group. The semiconductor integrated circuit detects the number of delay elements corresponding to one cycle of a first clock. The control circuit includes a second delay chain. The second delay chain has a configuration equivalent to the delay chain in the semiconductor integrated circuit. The control circuit outputs a second clock obtained by delaying the first clock by using the second delay chain according to the number of delay elements detected by the semiconductor integrated circuit.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Masashi Nakata
  • Patent number: 10291192
    Abstract: Apparatus and associated methods relate to a peaking module fabricated on a semiconductor substrate including a follower circuit driving a series peaking circuit-branch, the module configured to extend the bandwidth of a track-and-hold circuit. In an illustrative example, the series peaking circuit-branch may include an inductive element. One or more tracks on a metal interconnect above the semiconductor substrate may form the inductive element, for example. In some examples, one or more peaking modules may be combined creating a customized frequency response. In some examples, one or more combined peaking modules may be adjusted by a controller providing dynamic frequency response customization during operation. The follower circuits may employ constant current biasing and/or constant-gm biasing to provide substantial immunity to process, temperature and voltage variations, for example.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 14, 2019
    Assignee: XILINX, INC.
    Inventors: Ronan Casey, Chi Fung Poon, Ilias Chlis, Junho Cho
  • Patent number: 10133649
    Abstract: Systems and methods for software verification. In some embodiments, an application architecture model is generated for a software application, wherein: the application architecture model is generated based on source code of the software application and a framework model representing a software framework using which the software application is developed; and the application architecture model comprises a plurality of component models. One or more component models may be selected, based on a property to be checked, from the plurality of component models. The one or more component models may be analyzed to determine if the property is satisfied.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 20, 2018
    Assignee: Synopsys, Inc.
    Inventors: Guodong Li, John Steven
  • Patent number: 10127386
    Abstract: Systems and methods for software verification. In some embodiments, an application architecture model is generated for a software application, wherein: the application architecture model is generated based on source code of the software application; and the application architecture model comprises a plurality of component models. A property model type may be selected, based on a property to be checked, from a plurality of property model types. One or more component models may be selected, based on the selected property model type, from the plurality of component models. The one or more selected component models may be used to construct at least one property model of the selected property model type. The at least one property model may be analyzed to determine if the property is satisfied with respect to the at least one property model.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 13, 2018
    Assignee: Synopsys, Inc.
    Inventors: Guodong Li, John Steven
  • Patent number: 10033523
    Abstract: A circuit for measuring latency in an integrated circuit device is described. The circuit comprises a transmitter circuit having signal generator configured to generate a test signal having a marker for determining a latency in a path associated with the integrated circuit device; and a latency calculation circuit coupled to the signal generator and having a latency adjustment circuit and a unit interval (UI) adjustment circuit; wherein the latency calculation circuit generates a latency value (LATENCY) based upon a latency count from the latency adjustment circuit and a UI adjustment from the UI adjustment circuit.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: July 24, 2018
    Assignee: XILINX, INC.
    Inventors: Riyas Noorudeen Remla, Warren E. Cory
  • Patent number: 9985774
    Abstract: A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: May 29, 2018
    Assignee: Cornell University
    Inventors: Rajit Manohar, Sandra J. Jackson
  • Patent number: 9870148
    Abstract: An FPGA can be started up without system failure when a soft error occurs. A configuration control system includes: a first semiconductor chip which is capable of programming a logic circuit inside an LSI; a semiconductor memory which stores a plurality of pieces of circuit information of the first semiconductor chip; and a second semiconductor chip which, when controlling a configuration of the semiconductor chip using the circuit information stored in the semiconductor memory, if the configuration using any one of the plurality of pieces of circuit information fails, performs a re-configuration using another piece of circuit information among the plurality of pieces of circuit information.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: January 16, 2018
    Assignee: NEC CORPORATION
    Inventor: Katsuhisa Ikeuchi
  • Patent number: 9832012
    Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: November 28, 2017
    Assignee: AVNERA CORPORATION
    Inventors: Samuel J. Peters, II, Eric P. Etheridge, Victor Lee Hansen, Alexander C. Stange
  • Patent number: 9811273
    Abstract: The subject system and method are generally directed to ensuring reliable high speed data transfer in multiple data rate nonvolatile memory, such as double data rate (DDR) nonvolatile NAND flash memory and the like. The system and method provide measures to achieve read and write training for data signals (DQ) and the data strobe signal (DQS), one relative to the other. In such manner, high speed data transfers to and from nonvolatile memory such as flash devices may be performed with a reduced risk of data loss even at high operational frequencies.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: November 7, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sandeep Brahmadathan
  • Patent number: 9773557
    Abstract: Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane “1”) can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: September 26, 2017
    Assignee: Marvell World Trade Ltd.
    Inventors: Akio Goto, Chi-Kong Lee, Masayuki Urabe
  • Patent number: 9720485
    Abstract: This disclosure relates generally to a host-peripheral interface, and more particularly to system and method for dynamically adjusting a low power clock frequency of a host device upon detecting coupling of a peripheral device to the host device. In one embodiment, a method is provided for dynamically adjusting a low power clock frequency of a host device. The method comprises dynamically determining an initial frequency of a low power clock of the host device at which a low power link between the host device and a peripheral device is operational, computing a low power clock frequency range of the host device based on the initial frequency of the low power clock, assessing the low power link in the low power clock frequency range, and adjusting the low power clock frequency to a typical frequency of the low power clock frequency range based on the assessment.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: August 1, 2017
    Assignee: Wipro Limited
    Inventor: Vijay Kumar Kodavalla
  • Patent number: 9664737
    Abstract: A method for providing an on-chip variation determination and an integrated circuit utilizing the same are provided. The method includes: outputting, by a launch register circuit, a test data to the capture register circuit according to the first clock; receiving, by a capture register circuit, the test data from the launch register circuit according to the second clock; adjusting, by a control circuit, a first number of a first chain of delay elements to generate the first clock and a second number of a second chain of delay elements for the capture register circuit to just capture the test data to generate the second clock; and determining, by the control circuit, a path delay between the launch register circuit and the capture register circuit based on the first number of the first chain of delay elements and the second number of the second chain of delay elements.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: May 30, 2017
    Assignee: MEDIATEK INC.
    Inventors: Kok-Tiong Tee, Heng-Meng Liu, Yipin Wu
  • Patent number: 9628082
    Abstract: An apparatus includes a plurality of adjustable driver circuits having output nodes coupled to a signal line. Each adjustable driver circuit is configured to drive the signal line with a portion of a total drive strength indicated by a value of a binary control signal. The apparatus also includes a delay circuit configured to delay the binary control signal provided to each adjustable driver circuit by a respective time period unique to the adjustable driver circuit.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: April 18, 2017
    Assignee: XILINX, INC.
    Inventors: David S. Smith, Xiaobao Wang, Arvind R. Bomdica, Balakrishna Jayadev
  • Patent number: 9536589
    Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: January 3, 2017
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Frederick A. Ware
  • Patent number: 9488692
    Abstract: A method and apparatus for implementing mode based skew is disclosed. In one embodiment, an IC includes a number of different functional units each coupled to receive a respective one of a number of different clock signals. One or more of the functional circuit blocks includes at least two clock-gating circuits that are coupled to receive the clock signal provided to that functional circuit block. During a scan test, a first clock-gating circuit within a functional circuit block is configured to provide a first delay to the clock signal. A second clock-gating circuit within the functional circuit block may provide a second delay to the clock signal, the second delay being different from the first.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: November 8, 2016
    Assignee: Apple Inc.
    Inventors: Asad A. Bawa, Benjamin A. Marrou, Christopher Ng, Michael R. Seningen, Mihir S. Sabnis, Zameeruddin Mohammed, Yi Zhao
  • Patent number: 9461862
    Abstract: Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: October 4, 2016
    Assignee: KANDOU LABS, S.A.
    Inventors: Brian Holden, Amin Shokrollahi
  • Patent number: 9437277
    Abstract: An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: September 6, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James A. Welker, Joshua Siegel
  • Patent number: 9407427
    Abstract: A first transceiver is configured to transmit a first data signal to a second transceiver across a communication link. The second transceiver maintains clock data recovery (CDR) lock with the first signal by adjusting a sampling clock configured to sample the first data signal. When the communication link reverses directions, the second transceiver is configured to transmit a second data signal to the first transceiver with the phase of that second data signal adjusted based on the adjustments made to the sampling clock.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: August 2, 2016
    Assignee: NVIDIA Corporation
    Inventors: Gregory Kodani, Guatam Bhatia, Peter C. Mills
  • Patent number: 9401945
    Abstract: An apparatus, system, method, and program stored in a non-transitory recording medium, each of which generates a message indicating that image data is not received or only sound data is received, when a relay device transmits only the sound data from a transmission terminal to a counterpart transmission terminal, and transmits the message to the counterpart transmission terminal for display to a user at the counterpart transmission terminal.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: July 26, 2016
    Assignee: Ricoh Company, Ltd.
    Inventors: Yoshinaga Kato, Takahiro Asai, Masayuki Ishigami
  • Patent number: 9377510
    Abstract: A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree. The method also comprises adding a plurality of delay elements on a clock path, wherein the clock path is a signal resulting from the multiplexing. Further, the method comprises routing the clock path to a plurality of cores and a cache, e.g., an L2C cache, on the integrated circuit. Finally the method comprises staggering the test clock received by each of the plurality of cores and the cache by employing the delay elements during a scan shift cycle.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 28, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Milind Sonawane, Satya Puvvada, Amit Sanghani
  • Patent number: 9368168
    Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: June 14, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyeong-Han Lee, Seok-Cheon Kwon, Dong-Yang Lee
  • Patent number: 9367286
    Abstract: An integrated circuit implements a multistage processing pipeline, where control is passed in the pipeline with data to be processed according to the control. At least some of the different pipeline stages can be implemented by different circuits, being clocked at different frequencies. These frequencies may change dynamically during operation of the integrated circuit. Control and data to be processed according to such control can be offset from each other in the pipeline; e.g., control can precede data by a pre-set number of clock events. To cross a clock domain, control and data can be temporarily stored in respective FIFOs. Reading of control by the destination domain is delayed by a delay amount determined so that reading of control and data can be offset from each other by a minimum number of clock events of the destination domain clock, and control is read before data is available for reading.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: June 14, 2016
    Assignee: Imagination Technologies Limited
    Inventor: Ranjit J. Rozario
  • Patent number: 9367390
    Abstract: A memory controlling method, a memory storage device and a memory controlling circuit unit are provided. The method includes: providing a first clock signal to a rewritable non-volatile memory module and reading a first data in the rewritable non-volatile memory module according to the first clock signal; providing a second clock signal to the rewritable non-volatile memory module and writing a second data into the rewritable non-volatile memory module according to the second clock signal. A frequency of the second clock signal is different from a frequency of the first clock signal. Accordingly, an operation speed of the rewritable non-volatile memory module may be increased and probabilities of having errors for some operations are decreased.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: June 14, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Patent number: 9356589
    Abstract: An interchannel skew adjustment circuit adjusts signal skew between a first channel and a second channel. The circuit includes a phase adjustment circuit configured to receive a signal of the first channel, delay the signal by a discretely variable delay amount, and output a delayed signal; a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of the second channel, and detect a phase difference between these two signals; and a controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit. This interchannel skew adjustment circuit adjusts the interchannel signal skew only at a sender or a receiver, thereby reducing the circuit area and the power consumption.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: May 31, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tsuyoshi Ebuchi, Toru Iwata, Yoshihide Komatsu, Yuji Yamada, Shinya Miyazaki, Tsuyoshi Hiraki
  • Patent number: 9335933
    Abstract: Described are systems and apparatuses to mitigate the timing margin loss caused by inter-symbol interference (ISI) in high speed input/output (I/O) interfaces. Data dependent jitter (DDJ) compensation techniques that may be utilized in the transmission or receiving circuitry of the I/O interface, including capturing bit data values of a data signal prior to an identified data transition, and delaying/advancing the transmission/reception the data signal or a corresponding clock signal based on these bit data values.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 10, 2016
    Assignee: Intel Corporation
    Inventors: Harry Muljono, Charlie Lin, Kai Xiao, Linda K. Sun
  • Patent number: 9274543
    Abstract: A method for estimating a clock skew between a first clock and a second clock. The method includes the steps of detecting the clock skew to generate a detection resultant signal representing the clock skew; and determining time unit of a signal processing process, and estimating the clock skew according to the time unit of the signal processing process and the detection resultant signal.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: March 1, 2016
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ying-Yen Chen, Jih-Nung Lee
  • Patent number: 9223327
    Abstract: In some implementations, a system includes a universal adaptive voltage scaling monitor (UAVSM) and an adaptive voltage scaling (AVS) controller. The UAVSM is configured to delay a first signal generated by a signal path by an adjustable time period, compare the delayed first signal and a second signal associated with the signal path, and provide an error signal indicating a result of the comparison, where the error signal is asserted when the result of the comparison indicates that the delayed first signal is different from the second signal. The AVS controller is configured to provide a first control signal indicating that the voltage is to be increased when the received error signal is an asserted error signal, and provide a second control signal indicating that the voltage is to be decreased when the received error signal is an unasserted error signal and the signal path is active.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 29, 2015
    Assignee: Marvell International Ltd.
    Inventors: Jun Zhu, Liping Guo, Joseph Jun Cao
  • Patent number: 9218490
    Abstract: Embodiments of apparatuses and methods for using a trusted platform module for boot policy and secure firmware are disclosed. In one embodiment, a trusted platform module includes a non-volatile memory, a port, and a mapping structure. The port is to receive an input/output transaction from a serial bus. The transaction includes a system memory address in the address space of a processor. The mapping structure is to map the system memory address to a first location in non-volatile memory.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: December 22, 2015
    Assignee: Intel Corporation
    Inventor: Willard M. Wiseman
  • Patent number: 9203600
    Abstract: The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: December 1, 2015
    Assignee: Google Inc.
    Inventors: Peter Hochschild, Alexander Lloyd, Wilson Cheng-Yi Hsieh, Robert Edman Felderman, Michael James Boyer Epstein
  • Patent number: 9165091
    Abstract: According to one embodiment, a recipe management apparatus for comparing recipes prescribing process conditions of processing apparatuses between a plurality of the processing apparatuses having the same type. The recipe management apparatus includes a recipe reading unit, a mask unit, and a determination unit. The recipe reading unit is configured to read binary-format recipes of the plurality of processing apparatuses. The mask unit is configured to apply masks to data of the recipes based on mask position information prescribing positions which are applied with the masks in binary-format data of the recipes. The determination unit is configured to compare the plurality of recipes applied with the masks, and configured to determine whether there is a difference.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 20, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki Morinaga, Kenichi Tsujisawa
  • Patent number: 9159390
    Abstract: A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: October 13, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jong Ho Jung
  • Patent number: 9154890
    Abstract: The present disclosure provides a method wherein preceding and succeeding data elements of a data element to be sent next are analyzed in order to set a signal pattern which can be correctly recovered on the receiving side in spite of intersymbol interference. More particularly, depending on the transmission characteristics of the transmission path, the content of a window within the data stream to be sent wirelessly is examined in order to determine an energy content with which a data symbol has to be sent so that the data can be recovered securely.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: October 6, 2015
    Assignee: Cochlear Limited
    Inventors: Andrew Fort, Susan Di Genova, Yashodhan V. Moghe
  • Patent number: 9135965
    Abstract: A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: September 15, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre, Dietmar Gogl
  • Patent number: 9135980
    Abstract: This invention discloses a memory control circuit and method of controlling a data reading process of a memory module. In the data reading process, the memory module transmits a data signal and a data strobe signal used to recover the data signal. The data strobe signal includes a preamble part. The method includes steps of: controlling an impedance matching circuit of the memory module so that the data strobe signal is kept at a fixed level before the preamble part; generating a clock; generating an enabling signal according to the clock; sampling the data strobe signal according to the enabling signal to generate a sampled result; adjusting an enabling time of the enabling signal according to the sampled result; and starting a data recovering process for the data signal according to the enabling signal.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: September 15, 2015
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chun-Chi Yu, Chih-Wei Chang, Shen-Kuo Huang
  • Patent number: 9122608
    Abstract: One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit is configured to be coupled to an interconnect of a multiprocessor system and is configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: John T. Hollaway, Jr., Charles F. Marino, Praveen S. Reddy
  • Patent number: 9086272
    Abstract: There is provided a profile measuring apparatus which measures a profile of an object including: a projection unit which projects a pattern on the object from a projection direction; a measurement unit, which is displaced at a difference position for the projection unit and takes an image of the pattern from a direction different from the projection direction to measure a position on a surface of the object based on an image data obtained with the taken image; an object-rotation unit which rotates the object in two directions; and a pattern-rotation unit which is connected to the projection unit so as to be able to rotate the pattern relative to the object-rotation unit.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: July 21, 2015
    Assignee: NIKON CORPORATION
    Inventor: Manabu Komatsu
  • Patent number: 9058273
    Abstract: One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit configured to be coupled to an interconnect of a multiprocessor system and configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: John T. Hollaway, Jr., Charles F. Marino, Praveen S. Reddy
  • Patent number: 9049020
    Abstract: Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: June 2, 2015
    Assignee: SYNOPSYS, INC.
    Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Publication number: 20150143155
    Abstract: A data storage apparatus includes a controller including a controller input/output unit suitable for receiving a ready/busy delay signal and generating a ready/busy output signal in response to a first control signal, and a memory chip including a memory input/output unit suitable for receiving a chip enable delay signal and generating a chip enable output signal in response to a second control signal. The ready/busy delay signal and the chip enable delay signal are transmitted through a substantially same transmission line.
    Type: Application
    Filed: January 20, 2014
    Publication date: May 21, 2015
    Applicant: SK hynix Inc.
    Inventor: Sung Yeob CHO
  • Patent number: 9031544
    Abstract: A status switching method for a mobile device is disclosed. The status switching method includes receiving a first request for switching a radio function of the mobile device from a first status to a second status; keeping the radio function in the first status for a specific duration; switching the radio function to the second status if not receiving a second request for switching the radio function of the mobile device from the second status to the first status during the specific duration; and remaining the radio function in the first status if receiving a second request for switching the radio function of the mobile device from the second status to the first status during the specific duration; and switching the radio function to the first status.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: May 12, 2015
    Assignee: HTC Corporation
    Inventor: Chun-Yu Lai
  • Patent number: 9030242
    Abstract: A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: May 12, 2015
    Assignee: SK Hynix Inc.
    Inventor: Kyung Hoon Kim
  • Publication number: 20150121117
    Abstract: An EVEN component selecting unit and an ODD component selecting unit acquire a first signal from a DQ signal based on a rising edge of a DQS signal and a second signal from the DQ signal based on a falling edge of the DQS signal. Variable delay adding units give the first signal a first delay based on a phase difference between an internal clock signal and the rising edge of the DQS signal and give the second signal a second delay based on a phase difference between the internal clock signal and the falling edge of the DQS signal. Data capturing units capture, based on the internal clock signal, data from the first signal to which the first delay is given and the second signal to which the second delay is given.
    Type: Application
    Filed: September 10, 2014
    Publication date: April 30, 2015
    Inventors: Ryo Mizutani, Noriyuki Tokuhiro, Michitaka Hashimoto
  • Publication number: 20150121116
    Abstract: Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 30, 2015
    Applicant: International Business Machines Corporation
    Inventors: Markus Cebulla, Rolf Fritz, Cédric Lichtenau
  • Patent number: 9021293
    Abstract: A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: April 28, 2015
    Assignee: Uniquify, Incorporated
    Inventors: Jung Lee, Mahesh Goplan