Abstract: A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.

Abstract: An FPGA can be started up without system failure when a soft error occurs. A configuration control system includes: a first semiconductor chip which is capable of programming a logic circuit inside an LSI; a semiconductor memory which stores a plurality of pieces of circuit information of the first semiconductor chip; and a second semiconductor chip which, when controlling a configuration of the semiconductor chip using the circuit information stored in the semiconductor memory, if the configuration using any one of the plurality of pieces of circuit information fails, performs a re-configuration using another piece of circuit information among the plurality of pieces of circuit information.

Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.

Abstract: The subject system and method are generally directed to ensuring reliable high speed data transfer in multiple data rate nonvolatile memory, such as double data rate (DDR) nonvolatile NAND flash memory and the like. The system and method provide measures to achieve read and write training for data signals (DQ) and the data strobe signal (DQS), one relative to the other. In such manner, high speed data transfers to and from nonvolatile memory such as flash devices may be performed with a reduced risk of data loss even at high operational frequencies.

Abstract: Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane “1”) can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device.

Abstract: This disclosure relates generally to a host-peripheral interface, and more particularly to system and method for dynamically adjusting a low power clock frequency of a host device upon detecting coupling of a peripheral device to the host device. In one embodiment, a method is provided for dynamically adjusting a low power clock frequency of a host device. The method comprises dynamically determining an initial frequency of a low power clock of the host device at which a low power link between the host device and a peripheral device is operational, computing a low power clock frequency range of the host device based on the initial frequency of the low power clock, assessing the low power link in the low power clock frequency range, and adjusting the low power clock frequency to a typical frequency of the low power clock frequency range based on the assessment.

Abstract: A method for providing an on-chip variation determination and an integrated circuit utilizing the same are provided. The method includes: outputting, by a launch register circuit, a test data to the capture register circuit according to the first clock; receiving, by a capture register circuit, the test data from the launch register circuit according to the second clock; adjusting, by a control circuit, a first number of a first chain of delay elements to generate the first clock and a second number of a second chain of delay elements for the capture register circuit to just capture the test data to generate the second clock; and determining, by the control circuit, a path delay between the launch register circuit and the capture register circuit based on the first number of the first chain of delay elements and the second number of the second chain of delay elements.

Abstract: An apparatus includes a plurality of adjustable driver circuits having output nodes coupled to a signal line. Each adjustable driver circuit is configured to drive the signal line with a portion of a total drive strength indicated by a value of a binary control signal. The apparatus also includes a delay circuit configured to delay the binary control signal provided to each adjustable driver circuit by a respective time period unique to the adjustable driver circuit.

Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

Abstract: A method and apparatus for implementing mode based skew is disclosed. In one embodiment, an IC includes a number of different functional units each coupled to receive a respective one of a number of different clock signals. One or more of the functional circuit blocks includes at least two clock-gating circuits that are coupled to receive the clock signal provided to that functional circuit block. During a scan test, a first clock-gating circuit within a functional circuit block is configured to provide a first delay to the clock signal. A second clock-gating circuit within the functional circuit block may provide a second delay to the clock signal, the second delay being different from the first.

Abstract: Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.

Abstract: An integrated circuit includes enable circuitry coupled to receive transmit data and configured to set a clock enable to a first logic state when a data value of the transmit data changes to a different logic state. The circuit also includes clock control circuitry coupled to receive the clock enable and a data rate clock and configured to provide a filtered data rate clock, wherein the data rate clock is provided as the filtered data rate clock while the clock enable is the first logic state. The circuit also includes a flip flop having a clock input coupled to receive the filtered data rate clock, a data output coupled to provide final transmit data in response to the filtered data rate clock, and an inverting data input coupled to the data output, wherein the final transmit data corresponds to a first delayed version of the transmit data.

Abstract: A first transceiver is configured to transmit a first data signal to a second transceiver across a communication link. The second transceiver maintains clock data recovery (CDR) lock with the first signal by adjusting a sampling clock configured to sample the first data signal. When the communication link reverses directions, the second transceiver is configured to transmit a second data signal to the first transceiver with the phase of that second data signal adjusted based on the adjustments made to the sampling clock.

Abstract: An apparatus, system, method, and program stored in a non-transitory recording medium, each of which generates a message indicating that image data is not received or only sound data is received, when a relay device transmits only the sound data from a transmission terminal to a counterpart transmission terminal, and transmits the message to the counterpart transmission terminal for display to a user at the counterpart transmission terminal.

Abstract: A method for reducing peak power during a scan shift cycle is presented. The method comprises multiplexing a test clock with a functional clock on a integrated circuit at the root of a clock tree. The method also comprises adding a plurality of delay elements on a clock path, wherein the clock path is a signal resulting from the multiplexing. Further, the method comprises routing the clock path to a plurality of cores and a cache, e.g., an L2C cache, on the integrated circuit. Finally the method comprises staggering the test clock received by each of the plurality of cores and the cache by employing the delay elements during a scan shift cycle.

Abstract: A memory controlling method, a memory storage device and a memory controlling circuit unit are provided. The method includes: providing a first clock signal to a rewritable non-volatile memory module and reading a first data in the rewritable non-volatile memory module according to the first clock signal; providing a second clock signal to the rewritable non-volatile memory module and writing a second data into the rewritable non-volatile memory module according to the second clock signal. A frequency of the second clock signal is different from a frequency of the first clock signal. Accordingly, an operation speed of the rewritable non-volatile memory module may be increased and probabilities of having errors for some operations are decreased.

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

Abstract: An integrated circuit implements a multistage processing pipeline, where control is passed in the pipeline with data to be processed according to the control. At least some of the different pipeline stages can be implemented by different circuits, being clocked at different frequencies. These frequencies may change dynamically during operation of the integrated circuit. Control and data to be processed according to such control can be offset from each other in the pipeline; e.g., control can precede data by a pre-set number of clock events. To cross a clock domain, control and data can be temporarily stored in respective FIFOs. Reading of control by the destination domain is delayed by a delay amount determined so that reading of control and data can be offset from each other by a minimum number of clock events of the destination domain clock, and control is read before data is available for reading.

Abstract: An interchannel skew adjustment circuit adjusts signal skew between a first channel and a second channel. The circuit includes a phase adjustment circuit configured to receive a signal of the first channel, delay the signal by a discretely variable delay amount, and output a delayed signal; a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of the second channel, and detect a phase difference between these two signals; and a controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit. This interchannel skew adjustment circuit adjusts the interchannel signal skew only at a sender or a receiver, thereby reducing the circuit area and the power consumption.

Abstract: Described are systems and apparatuses to mitigate the timing margin loss caused by inter-symbol interference (ISI) in high speed input/output (I/O) interfaces. Data dependent jitter (DDJ) compensation techniques that may be utilized in the transmission or receiving circuitry of the I/O interface, including capturing bit data values of a data signal prior to an identified data transition, and delaying/advancing the transmission/reception the data signal or a corresponding clock signal based on these bit data values.

Abstract: A method for estimating a clock skew between a first clock and a second clock. The method includes the steps of detecting the clock skew to generate a detection resultant signal representing the clock skew; and determining time unit of a signal processing process, and estimating the clock skew according to the time unit of the signal processing process and the detection resultant signal.

Abstract: In some implementations, a system includes a universal adaptive voltage scaling monitor (UAVSM) and an adaptive voltage scaling (AVS) controller. The UAVSM is configured to delay a first signal generated by a signal path by an adjustable time period, compare the delayed first signal and a second signal associated with the signal path, and provide an error signal indicating a result of the comparison, where the error signal is asserted when the result of the comparison indicates that the delayed first signal is different from the second signal. The AVS controller is configured to provide a first control signal indicating that the voltage is to be increased when the received error signal is an asserted error signal, and provide a second control signal indicating that the voltage is to be decreased when the received error signal is an unasserted error signal and the signal path is active.

Abstract: Embodiments of apparatuses and methods for using a trusted platform module for boot policy and secure firmware are disclosed. In one embodiment, a trusted platform module includes a non-volatile memory, a port, and a mapping structure. The port is to receive an input/output transaction from a serial bus. The transaction includes a system memory address in the address space of a processor. The mapping structure is to map the system memory address to a first location in non-volatile memory.

Abstract: The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.

Abstract: According to one embodiment, a recipe management apparatus for comparing recipes prescribing process conditions of processing apparatuses between a plurality of the processing apparatuses having the same type. The recipe management apparatus includes a recipe reading unit, a mask unit, and a determination unit. The recipe reading unit is configured to read binary-format recipes of the plurality of processing apparatuses. The mask unit is configured to apply masks to data of the recipes based on mask position information prescribing positions which are applied with the masks in binary-format data of the recipes. The determination unit is configured to compare the plurality of recipes applied with the masks, and configured to determine whether there is a difference.

Abstract: A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal.

Abstract: The present disclosure provides a method wherein preceding and succeeding data elements of a data element to be sent next are analyzed in order to set a signal pattern which can be correctly recovered on the receiving side in spite of intersymbol interference. More particularly, depending on the transmission characteristics of the transmission path, the content of a window within the data stream to be sent wirelessly is examined in order to determine an energy content with which a data symbol has to be sent so that the data can be recovered securely.

Abstract: This invention discloses a memory control circuit and method of controlling a data reading process of a memory module. In the data reading process, the memory module transmits a data signal and a data strobe signal used to recover the data signal. The data strobe signal includes a preamble part. The method includes steps of: controlling an impedance matching circuit of the memory module so that the data strobe signal is kept at a fixed level before the preamble part; generating a clock; generating an enabling signal according to the clock; sampling the data strobe signal according to the enabling signal to generate a sampled result; adjusting an enabling time of the enabling signal according to the sampled result; and starting a data recovering process for the data signal according to the enabling signal.

Abstract: A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).

Abstract: One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit is configured to be coupled to an interconnect of a multiprocessor system and is configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.

Abstract: There is provided a profile measuring apparatus which measures a profile of an object including: a projection unit which projects a pattern on the object from a projection direction; a measurement unit, which is displaced at a difference position for the projection unit and takes an image of the pattern from a direction different from the projection direction to measure a position on a surface of the object based on an image data obtained with the taken image; an object-rotation unit which rotates the object in two directions; and a pattern-rotation unit which is connected to the projection unit so as to be able to rotate the pattern relative to the object-rotation unit.

Abstract: One or more systems, devices, methods, and/or processes described can determine a maximum cache command rate of a processor unit. For example, an interface of the processor unit configured to be coupled to an interconnect of a multiprocessor system and configured such that a first portion of the interface provides a signal to a second portion of the interface, where the first portion of the interface operates utilizing a known frequency and the second portion of the interface operates utilizing a cache frequency of the processor unit; the second portion of the interface circulates the signal; the first portion of the interface receives the signal from the second portion of the interface; the first portion of the interface determines a cache command rate based on the known frequency, the frequency of the cache, and the signal; and the interface provides information indicating the cache command rate to the interconnect.

Abstract: Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data.

Abstract: A data storage apparatus includes a controller including a controller input/output unit suitable for receiving a ready/busy delay signal and generating a ready/busy output signal in response to a first control signal, and a memory chip including a memory input/output unit suitable for receiving a chip enable delay signal and generating a chip enable output signal in response to a second control signal. The ready/busy delay signal and the chip enable delay signal are transmitted through a substantially same transmission line.

Abstract: A status switching method for a mobile device is disclosed. The status switching method includes receiving a first request for switching a radio function of the mobile device from a first status to a second status; keeping the radio function in the first status for a specific duration; switching the radio function to the second status if not receiving a second request for switching the radio function of the mobile device from the second status to the first status during the specific duration; and remaining the radio function in the first status if receiving a second request for switching the radio function of the mobile device from the second status to the first status during the specific duration; and switching the radio function to the first status.

Abstract: A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code value of the delay control code in sequential synchronization with a plurality of delayed clocks obtained by delaying the external clock as large as predetermined delay amounts, respectively, delay the shifted read command as large as the variable delay amount, and output the result of delay as an output enable flag signal.

Abstract: An EVEN component selecting unit and an ODD component selecting unit acquire a first signal from a DQ signal based on a rising edge of a DQS signal and a second signal from the DQ signal based on a falling edge of the DQS signal. Variable delay adding units give the first signal a first delay based on a phase difference between an internal clock signal and the rising edge of the DQS signal and give the second signal a second delay based on a phase difference between the internal clock signal and the falling edge of the DQS signal. Data capturing units capture, based on the internal clock signal, data from the first signal to which the first delay is given and the second signal to which the second delay is given.

Abstract: Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire.

Abstract: A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

Abstract: A method is provided for maintaining a synchronized local timer by using a periodic signal which comprises: providing a value of a clock cycle, and values for a first and second timer-parameters, wherein the first timer-parameter is less than the clock cycle value and the second timer-parameter is higher therefrom; providing values for a first (“a”) and second (“b”) arbitration parameters associated with the first and second timer-parameters respectively; upon receiving a periodic signal, adding to the local timer, at least once the first and/or the second timer-parameter, so that on average over one second, the first timer-parameter is added “a” times and the second timer-parameter is added “b” times, thereby ensuring that a value of the local timer essentially overlaps the period frequency of the periodic signal; upon receiving a subsequent periodic signal, setting the value of the local timer to a propagation delay of the periodic signal.

Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Abstract: A system and method to synchronize distributed measurements in a borehole are described. The system includes a plurality of wired segments coupled together by couplers and a plurality of nodes configured to measure, process, or relay information obtained in the borehole to a surface processing system, each of the plurality of nodes comprising a local clock and being disposed at one of the couplers or between couplers. The system also includes a surface processing system coupled to a master clock and configured to determine a time offset between the master clock and the local clock of an nth node among the plurality of nodes based on a downhole generated synchronization signal.

Abstract: Devices and methods for synchronizing devices over a switched fabric. A switch receives a request packet from a device, transmits a completion packet to the device, determines an in-switch delay, and stores the in-switch delay. Another switch receives a packet from a first device, forwards the packet to a second device, determines an in-switch delay of the packet, and stores the in-switch delay. Storing of in-switch delays may include adding an in-switch delay to values in one or more transaction delay fields of a packet. Storing of in-switch delays may include storing the delays in a storage element of a switch. In-switch delay may be determined as a difference between a receiving time corresponding to reception of a packet and a forwarding or transmittal time corresponding to forwarding or transmitting of a packet.

Abstract: An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that receives DQS signals from the off-chip memory and that outputs a gated version of the DQS signals. The DQS enable circuitry may include an input buffer, a comparator, a latch, a flip-flop, a counter, and a gating circuit. The input buffer may receive an incoming DQS signal. The comparator may be used to determine when the incoming DQS signal starts to toggle. The latch may be used to control when a gating signal is asserted. The flip-flop controls the counter, which limits the duration that the gating signal is asserted. The gating circuit receives the DQS signal from the buffer and the gating signal and passes the DQS signal through to its output only when the gating signal is asserted.

Abstract: An embodiment for skew compensation for a stacked die is disclosed. For an embodiment of an apparatus, an interposer has a first and a second integrated circuit die coupled to the interposer. The first integrated circuit die includes an information generator, a signal delay compensator, and an input/output block. The information generator is configured to determine: a first delay value for a first path of the interposer between the first integrated circuit die and the second integrated circuit die; a second delay value for a second path of the interposer between the first integrated circuit die and the second integrated circuit die; and a difference between the first delay value and the second delay value. The signal delay compensator is coupled to receive the difference and configured to adjust a parameter of the first integrated circuit die to reduce the difference.

Abstract: A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for byte lanes. In the system, control settings for the read data delay circuits for providing CAS latency compensation are determined and set using controller circuits according to a dynamic calibration procedure performed from time to time. In the system, determining and setting the control settings for the read data delay circuits for providing CAS latency compensation is performed independently and parallely in each of a plurality of byte lanes.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: Command paths, apparatuses, and methods for providing a command to a data block are described. In an example command path, a command receiver is configured to receive a command and a command buffer is coupled to the command receiver and configured to receive the command and provide a buffered command. A command block is coupled to the command buffer to receive the buffered command. The command block is configured to provide the buffered command responsive to a clock signal and is further configured to add a delay before to the buffered command, the delay based at least in part on a shift count. A command tree is coupled to the command block to receive the buffered command and configured to distribute the buffered command to a data block.

Abstract: A computer-implemented method is presented for synchronizing time between two handheld medical devices that interoperate with each other. The method includes: determining a first time as measured by a first clock residing in the first medical device; determining a second time as measured by a second clock residing in a second medical device; evaluating whether the first clock is synchronized with the second clock; determining whether at least one of the first clock and the second clock was set manually by a user; and setting time of the first clock in accordance with the second time when the second clock was set manually by the user.

Abstract: A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt controller includes a main time base counter. The SOC includes multiple local time base counters, each coupled to a respective one of the processing cores. Synchronization logic blocks are used to update the local counters. These blocks receive a subset of bits from the interrupt controller. The subset of bits represents a number of least significant bits of the main counter less than a total number of bits for the main counter. The logic blocks update an associated local counter according to changes to the received subset of bits. A difference may exist between values of the main counter in the interrupt controller and the local counter in the processing core. However, this difference may be a constant value.