Using Delay Patents (Class 713/401)
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Patent number: 8839018Abstract: An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first amount to advance a synchronous data strobe associated with a first data group and a second amount to delay a data bit signal associated with a second data group. The synchronous bus optimizer receives the control information, and develops a first value on a first ratio bus that indicates the first amount and a second value on a second ratio bus that indicates the second amount. The core clocks generator advances a data strobe clock by the first amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the first amount. The DLL generates a delayed data bit signal, delayed by the second amount.Type: GrantFiled: June 21, 2011Date of Patent: September 16, 2014Assignee: Via Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Publication number: 20140258764Abstract: An apparatus for synchronizing an output dock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback dock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit.Type: ApplicationFiled: May 19, 2014Publication date: September 11, 2014Applicant: Micron Technology, Inc.Inventor: JONGTAE KWAK
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Patent number: 8826059Abstract: A apparatus is provided for buffering data between a memory controller and a DRAM. The apparatus includes a phase locked loop (PLL), a phase interpolator for aligning a phase of an output clock signal in response to a phase aligning control word, and a non-volatile storage location permanently storing the phase aligning control word. The phase aligning control word is determined through an initial training procedure of the device under predetermined training conditions of at least a supply voltage level and a temperature, and the predetermined training conditions are set so as to optimize the phase alignment of an edge of the output clock signal with respect to the buffered data signal.Type: GrantFiled: January 13, 2010Date of Patent: September 2, 2014Assignee: Texas Instruments Deutschland GmbHInventor: Joern Naujokat
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Patent number: 8826058Abstract: A Delay-tolerant Asynchronous Interface (DANI) is typically used to make the clock domains for reusable silicon intellectual property (IP) cores completely independent of each other. In fact, a DANI-wrapped IP core usually appears to its environment as if it were clockless. This property is necessary to address the variability in data transmission-time between source and destination. This variability is a result of increased lack of predictability in today's leading-edge manufacturing processes. A DANI wrapper can be applied to the IP core that is the source of data to be transmitted or it can be applied to the IP core that is the destination of that data. The transmission time over the route between source and destination may vary more than a single clock period.Type: GrantFiled: September 12, 2013Date of Patent: September 2, 2014Assignee: Blendics, Inc.Inventors: Jerome R. Cox, Jr., George Engel, James Moscola, Thomas J. Chaney
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Patent number: 8826057Abstract: A multiple time domain synchronizer includes a data pipeline containing a plurality of serially-connected delay elements therein. A latency selection circuit is provided, which has a plurality of inputs electrically coupled to outputs of a corresponding plurality of delay elements in the data pipeline. The latency selection circuit is configured to pass a data pipeline signal from an output of a selected one of the plurality of delay elements in response to a latency control signal. A synchronization circuit is provided, which is electrically coupled to an output of the latency selection circuit. This synchronization circuit, which includes first and second unequal timing paths therein, is responsive to a clock that synchronizes capture of the data pipeline signal selected by the latency selection circuit and a destination code that selects one of the first and second unequal timing paths to be traversed by the captured data pipeline signal as active.Type: GrantFiled: June 29, 2012Date of Patent: September 2, 2014Assignee: Integrated Device Technology Inc.Inventors: Bruce Lorenz Chin, David Stuart Gibson
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Patent number: 8819474Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller. Other embodiments are described and claimed.Type: GrantFiled: April 3, 2009Date of Patent: August 26, 2014Assignee: Intel CorporationInventors: Theodore Z. Schoenborn, John V. Lovelace, Christopher P. Mozak, Bryan L. Spry
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Patent number: 8799697Abstract: Methods, systems and devices configured to add synchronization to the entry and exit from low power modes in asynchronous operating systems on a multiprocessor system. A synchronizing agent tracks the requested sleep and wake up times of the different asynchronous operating systems executing on different cores of the same system on chip or multicore processor. The sleep/wake up times of some cores/operating systems may be delayed in order to synchronize the sleep/wake up times of two or more of the asynchronous operating systems executing on the multiprocessor system.Type: GrantFiled: November 4, 2011Date of Patent: August 5, 2014Assignee: QUALCOMM IncorporatedInventors: Paul R. Johnson, Gabriel A. Watkins
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Patent number: 8793525Abstract: Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.Type: GrantFiled: July 3, 2008Date of Patent: July 29, 2014Assignee: Rambus Inc.Inventors: Jared L. Zerbe, Frederick A. Ware
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Publication number: 20140208148Abstract: An apparatus including a Joint Test Action Group (JTAG) interface and a bit lag control element. The JTAG interface receives information that indicates an amount to adjust a propagation time. The bit lag control element measures the propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and generates a value indicating an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value indicating the propagation time. The adjust logic adjusts the second value by the amount prescribed by the JTAG interface to yield a third value. The gray encoder gray encodes the third value to generate the value on the lag bus.Type: ApplicationFiled: February 1, 2013Publication date: July 24, 2014Applicant: VIA TECHNOLOGIES, INC.Inventor: VIA TECHNOLOGIES, INC.
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Publication number: 20140208147Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a bit lag control element and a synchronous lag receiver. The bit lag control element is configured to measure a propagation time beginning with assertion of a strobe and ending with assertion of a first one of a plurality of radially distributed strobes corresponding to the strobe, and is configured to generate a value on a lag bus that indicates the propagation time. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive the first one of the plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the propagation time.Type: ApplicationFiled: January 22, 2013Publication date: July 24, 2014Applicant: VIA TECHNOLOGIES, INC.Inventors: Vanessa S. Canac, James R. Lundberg
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Publication number: 20140208149Abstract: An apparatus including a synchronous lag receiver that receives one of a plurality of radially distributed strobes and a data bit, and that delays registering of the data bit by a propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters generates successively delayed versions of the data bit. The first mux receives a value on a lag bus that indicates the propagation time, and selects one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver receives the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and registers the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of distributed strobe signals.Type: ApplicationFiled: February 1, 2013Publication date: July 24, 2014Applicant: VIA TECHNOLOGIES, INC.Inventor: VIA Technologies, Inc.
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Patent number: 8782460Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network and a synchronous receiver disposed within a receiving device. The resistor network is configured to provide a ratio signal that indicates an amount to delay a data bit signal associated with a data group, where the data bit signal is transmitted by a transmitting device along with a data strobe signal. The synchronous receiver receives the data bit and the data strobe signals, and includes a delay-locked loop (DLL). The DLL is coupled to the ratio signal, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal, and where the delayed bit signal is delayed relative to the data strobe signal by the amount, thus allowing for proper reception of the data bit signal.Type: GrantFiled: June 21, 2011Date of Patent: July 15, 2014Assignee: VIA Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Patent number: 8781052Abstract: A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to marry up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.Type: GrantFiled: June 21, 2012Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Bernard Arambepola, Shaul Shulman, Naor Goldman, Amos Klimker, Noam Tal
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Patent number: 8769330Abstract: Methods and apparatuses are provided that allow for the synchronization of an operating point transition in an embedded system environment. Identification of an upcoming operating point transition, operating point transition constraints, and maximum parking latency parameters is provided. Then, an ordering of seizing bus activity as well as an ordering of resuming bus activity is determined. The operating point transition is then implemented using the determined ordering. Simulation and determination of change of successfully completing operating point transition prior to initiating and while the transition is pending are also provided.Type: GrantFiled: March 17, 2011Date of Patent: July 1, 2014Inventor: Adam Kaiser
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Publication number: 20140181568Abstract: Interface circuitry transmitting transactions between an initiator and a recipient includes: a clock input receiving a clock signal; a transaction input receiving transactions; clock outputs for outputting the clock signal; transaction outputs outputting the transactions to the recipient; and synchronising circuits clocked by the clock signal and transmitting the transactions to the transaction output in response to the clock signal. A controllable delay circuit is provided between the clock input and the synchronising circuits. A further synchronising circuit configured to provide a similar delay. Phase detection circuitry is arranged to detect alignment of the received clock signals. Calibration control circuitry adjusts a delay of the controllable delay circuit during calibration until the phase detection circuitry detects alignment.Type: ApplicationFiled: December 24, 2012Publication date: June 26, 2014Applicant: ARM LimitedInventors: Gyan Prakash, Nidhir Kumar
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Patent number: 8762611Abstract: A system including a bus, and a method to transmit data over a bus system are disclosed. According to an embodiment, a method to transmit data over a bus system includes deliberately delaying the transmission of data. The deliberate delay caused by deliberately delaying the transmission of data may be chosen to predominate stochastic delay differences.Type: GrantFiled: February 15, 2012Date of Patent: June 24, 2014Assignee: Infineon Technologies AGInventors: Christian Heiling, Heimo Hartlieb
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Patent number: 8756395Abstract: Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.Type: GrantFiled: February 27, 2012Date of Patent: June 17, 2014Assignee: Rambus Inc.Inventors: Richard M. Barth, Ely K. Tsern, Craig E. Hampel, Frederick A. Ware, Todd W. Bystrom, Bradley A. May, Paul G. Davis
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Patent number: 8751852Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal.Type: GrantFiled: June 21, 2011Date of Patent: June 10, 2014Assignee: Via Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Patent number: 8751850Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The resistor network is configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group. The composite delay element is configured to equalize delay paths within a receiving device, where the delay paths correspond to a data strobe signal that is received from a transmitting device. The receiving device and resistor network are coupled to a motherboard. The ratio signal enters said receiving device through an external pin. The DLLs are coupled to the ratio signal and disposed within the receiving device, and are configured to generate delayed data bit signals, where the DLLs add the amount of delay to the data bit signals to generate the delayed data bit signals.Type: GrantFiled: June 21, 2011Date of Patent: June 10, 2014Assignee: VIA Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Patent number: 8751851Abstract: An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to advance a synchronous data strobe associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The core clocks generator is coupled to the ratio bus and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.Type: GrantFiled: June 21, 2011Date of Patent: June 10, 2014Assignee: VIA Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Publication number: 20140157035Abstract: A bus interface, for allowing a plurality of devices to communicate with one another via the bus, includes a bit timing symmetrization component for symmetrizing the bit stream. For an incoming bit stream, the bit timing symmetrization component further includes an input delay filter for delaying recessive to dominant edges for a given received bit stream and sampling the delayed input signal at the sample point. In one embodiment, bit timing synchronization may still be performed with the undelayed recessive to dominant edges. For an outgoing bit stream, the bit timing symmetrization component transmits a recessive bit, that followed a previously transmitted dominant bit, before the start of the next bit time, and transmits a dominant bit, that followed a previously transmitted recessive bit, with a delay of a configurable amount of time.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicant: Infineon Technologies AGInventor: Achim Vowe
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Patent number: 8743633Abstract: An integrated semiconductor device including: a first semiconductor device having a clock generation section, first data storage sections storing input data as transfer data, data output terminals provided, one for each of the first data storage sections, and a clock output terminal adapted to output a transfer clock; and a second semiconductor device having data input terminals which receive the transfer data, a clock input terminal adapted to receive the transfer clock, second data storage sections associated with the data input terminals respectively to store input data, and selection sections associated with the second data storage sections respectively to select either the transfer data or data shifted and output to the associated second data storage section in a first series circuit which is formed by connecting the second data storage sections in series, the selection sections supplying the selected data to the associated second data storage section.Type: GrantFiled: June 13, 2011Date of Patent: June 3, 2014Assignee: Sony CorporationInventor: Takenori Aoki
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Patent number: 8736339Abstract: This invention includes a clock tree to which clock signals are distributed, and a phase comparison circuit configured to detect the phase difference between a plurality of feedback clock signals upon receiving the plurality of feedback clock signals output from different branching points of the clock tree. The invention includes a feedback clock signal generation circuit configured to generate a variation-corrected feedback clock signal for correcting a manufacture variation in the semiconductor integrated circuit based on the phase difference detected by the phase comparison circuit. The invention includes a phase regulation circuit configured to delay the clock signal so as to reduce the phase difference between a reference clock signal and the variation-corrected feedback clock signal generated by the feedback clock signal generation circuit.Type: GrantFiled: September 5, 2012Date of Patent: May 27, 2014Assignee: Canon Kabushiki KaishaInventor: Shigeo Kawaoka
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Patent number: 8732509Abstract: An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback clock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit.Type: GrantFiled: April 7, 2010Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventor: Jongtae Kwak
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Patent number: 8731073Abstract: Methods, systems, and apparatuses are described for aligning lanes of low speed serial links coupled to a transceiver. The transceiver cooperatively performs lane alignment operations with a low speed device during initialization of the transceiver and the low speed device. The lane alignment operations are performed in-band using the low speed serial links, and therefore, do not require additional out-of-band-signaling wires between the transceiver and the low speed device to perform the lane alignment operations. The lane alignment operations may be performed by a handshaking process performed by the transceiver and the low speed device, where the transceiver and the low speed device provide training pattern(s) of data that are used to align the low speed serial links. The low speed serial links are continuously monitored after initialization is complete to detect various transient impairments and to re-initiate lane alignment operations in response to detecting such impairments.Type: GrantFiled: March 14, 2013Date of Patent: May 20, 2014Assignee: Broadcom CorporationInventor: Whay Sing Lee
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Patent number: 8726063Abstract: A computer-implemented method for performing processing including setting a timer associated with a first processing event, scheduling an expected time for the processing event using wall clock time, at the timer, using the expected time to calculate a delay associated with the timer, performing the first processing event in response to the timer, and setting a subsequent timer to compensate for the delay.Type: GrantFiled: July 26, 2011Date of Patent: May 13, 2014Assignee: Raytheon CompanyInventors: David W. Shin, Richard J. Kenefic, Saad Karim
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Patent number: 8726064Abstract: An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.Type: GrantFiled: April 17, 2006Date of Patent: May 13, 2014Assignee: Violin Memory Inc.Inventor: Jon C. R. Bennett
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Patent number: 8726062Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.Type: GrantFiled: December 1, 2011Date of Patent: May 13, 2014Assignee: Synopsys, Inc.Inventor: Jose Angelo Rebelo Sarmento
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Patent number: 8719616Abstract: A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a frequency-shift compensated clock using the repeatable frequency-shifts. A frequency-shift compensated clock includes a synthesizer configured to generate a frequency-shift compensated clock signal using repeatable frequency shifts and encoder clock signals.Type: GrantFiled: February 22, 2013Date of Patent: May 6, 2014Assignee: Seagate Technology LLCInventors: Koichi Wago, Sundeep Chauhan, David M. Tung
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Patent number: 8719613Abstract: A circuit comprising a single-wire serial interface (SWSI), a delay module coupled to the SWSI and operable to introduce a delay during a data transmission, the delay being dependent on a local clock (LC) associated with the circuit, wherein the delay enables the circuit to synchronize the data transmission with a device coupled to the SWSI based on the LC.Type: GrantFiled: January 25, 2011Date of Patent: May 6, 2014Assignee: Futurewei Technologies, Inc.Inventor: Gary Neben
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Patent number: 8707078Abstract: Clock buffers in a clock and data recovery (CDR) system are trimmed by receiving a first transmitted clock-like data pattern in a reduced rate mode, locking the CDR using the received version of the first transmitted clock-like data pattern; and receiving a second transmitted clock-like data pattern. The first transmitted clock-like data pattern is transmitted using a first rate mode and the reduced rate mode divides the first rate mode by an integer value. The second transmitted clock-like data pattern has a run-length that is an integer division of a run-length of the first transmitted clock-like data pattern. A phase of the clock buffers is adjusted using the second transmitted clock-like data pattern. The received first transmitted clock-like data pattern has edges that correspond to only positive or negative edges of the first transmitted clock-like data pattern.Type: GrantFiled: December 30, 2010Date of Patent: April 22, 2014Assignee: LSI CorporationInventor: Mohammad S. Mobin
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Patent number: 8707001Abstract: Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference clock signal. Then, a second phase skew is measured between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal. The memory access time is determined based on the first and second phase skews.Type: GrantFiled: December 4, 2008Date of Patent: April 22, 2014Assignee: QUALCOMM IncorporatedInventors: Nan Chen, Zhiqin Chen, Varun Verma
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Patent number: 8707080Abstract: A clock domain crossing technique that uses a circular buffer toggled by clocks from the two domains with output metastability protection. The resulting output is a pair of enable signals that may be used to pass data between the two clock domains. In one embodiment, a set of storage devices is connected in a circular buffer arrangement. A first subset of the storage devices is clocked by a signal from a first clock domain and a second subset of the flip flops is clocked by a signal taken from a second clock domain. Respective output circuits generate enable signals to be used for transferring data between domains. In some implementations, a pulse is stored and registered by at least two of the storage devices in the first domain before being passed to the devices in the second domain. In other embodiments, the output circuits may include a pair of D flip flops, each clocked by a respective one of the first or second domain signals.Type: GrantFiled: July 12, 2011Date of Patent: April 22, 2014Assignee: EMC CorporationInventor: Jeffrey T. McLamb
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Patent number: 8700818Abstract: Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.Type: GrantFiled: September 29, 2006Date of Patent: April 15, 2014Assignee: Mosaid Technologies IncorporatedInventors: Hong Beom Pyeon, HakJune Oh
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Patent number: 8700943Abstract: In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC value after the system suspension, and directly updating a thread offset value associated with a first thread executing on a first core of the processor with the stored TSC value, without performing a synchronization between a plurality of cores of the processor. Other embodiments are described and claimed.Type: GrantFiled: December 22, 2009Date of Patent: April 15, 2014Assignee: Intel CorporationInventors: Martin G. Dixon, Jeremy J. Shrall, Rajesh S. Parthasarathy
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Patent number: 8687436Abstract: Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.Type: GrantFiled: April 9, 2012Date of Patent: April 1, 2014Assignee: Round Rock Research, LLCInventor: J. Thomas Pawlowski
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Patent number: 8687799Abstract: When an encryption processing circuit encrypts data, a current flows in the encryption processing circuit. A noise current generated by a noise generation circuit is superimposed on the current consumed by the encryption processing circuit. The present invention is applicable to an IC chip that encrypts plaintext data using a key, thus preventing the key from being broken by DPA attacks based on analysis of the current consumption to provide high security.Type: GrantFiled: February 17, 2005Date of Patent: April 1, 2014Assignee: Sony CorporationInventors: Shigeru Arisawa, Seiji Esaka
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Publication number: 20140089717Abstract: A method and apparatus are disclosed to provide ad-hoc synchronization in industrial networks between a programmable logic controller and each I/O device without any specific protocol extensions or distributed clock scheme. An embodiment of an industrial control network comprising a Programmable Logic Controller (PLC), a network coupled to the PLC, and a plurality of networked input/output (I/O) devices coupled to the network is provided. Each I/O device comprises: inputs coupled to the network to receive data from the PLC as device input data; and outputs coupled to the network to transmit output data from the I/O device to the PLC. The embodiment further comprises a programmable timer initiating an I/O cycle for the device on a periodic basis. The I/O device is operable to determine a first time period starting at the time at which specific output data arrives from the PLC and ending when the period of the timer ends. The first time period is compared to a predetermined time period.Type: ApplicationFiled: September 22, 2012Publication date: March 27, 2014Inventor: ANDREW DAVID ALSUP
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Patent number: 8683252Abstract: A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.Type: GrantFiled: September 11, 2009Date of Patent: March 25, 2014Assignee: LG Electronics Inc.Inventors: Hyung Sun Kim, Kang Soo Seo, Byung Jin Kim, Soung Hyun Um
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Patent number: 8683253Abstract: An apparatus that compensates for misalignment on a synchronous data bus, including a resistor network, a transmitting device, and a receiving device. The resistor network indicates an amount to advance a synchronous data strobe associated with a data group. The transmitting device has a core clocks generator and a synchronous strobe driver. The core clocks generator advances a data strobe clock by the amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe is advanced also by the amount. The receiving device has a composite delay element and delay-locked loops (DLLs). The composite delay element equalizes delay paths within the receiving device, where the delay paths correspond to the synchronous data strobe that is received from the transmitting device.Type: GrantFiled: June 21, 2011Date of Patent: March 25, 2014Assignee: VIA Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Publication number: 20140082399Abstract: A data bus part (1) with a data bus interface which has a downstream data bus input (2) for receiving data from a higher-order data bus (1), and a clock generator (6) for generating an internal clock signal for the data bus part (1), is described. The data bus part (1) has a synchronization unit (7) to synchronize the clock generator (6) with the clock signal of the higher-order data bus part (1), wherein the synchronization unit (7) is configured to detect transitions in the downstream data stream (D) received at the downstream data input (2), to regulate the frequency of the internal clock signal depending on the detected transitions, and to set a defined phasing of the internal clock signal in relation to the detected transitions.Type: ApplicationFiled: September 17, 2013Publication date: March 20, 2014Applicant: WAGO Verwaltungsgesellschaft mbHInventor: Daniel JEROLM
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Publication number: 20140082398Abstract: An embedded multimedia card (eMMC) is provided. The eMMC includes a clock channel receiving a clock output from a host, data channels receiving data signals from the host, and a command channel receiving a SWITCH command including delay offset values from the host so as to adjust a delay of at least one of the data signals, which are received, in response to the delay offset values.Type: ApplicationFiled: September 13, 2013Publication date: March 20, 2014Applicant: SAMSUNG SEMICONDUCTOR CO., LTD.Inventors: JUNG PIL LEE, YOUNG GYU KANG, SUNG HO SEO, MYUNG SUB SHIN, KYUNG PHIL YOO, KYOUNG LAE CHO, JIN HYEOK CHOI, SEONG SIK HWANG
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Publication number: 20140082397Abstract: An embedded multimedia card (eMMC) comprises a clock channel configured to receive a clock signal from a host, a command channel configured to receive a command from the host, a plurality of data channels configured to transmit data to the host, a data strobe channel configured to transmit a data strobe signal synchronized with the data to the host, and a data strobe control unit configured to selectively enable or generate the data strobe signal according to a protocol control signal.Type: ApplicationFiled: September 12, 2013Publication date: March 20, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: MYUNG SUB SHIN, SUNG HO SEO, KYUNG PHIL YOO, JUNG PIL LEE, HWA SEOK OH, YOUNG GYU KANG, JUN HO CHOI
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Patent number: 8677170Abstract: An apparatus for generating a delayed clock signal. The apparatus is a computer system with a processor to which a memory device is coupled. The memory device has a delay clock generator that has a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.Type: GrantFiled: February 24, 2012Date of Patent: March 18, 2014Assignee: Round Rock Research, LLCInventor: Leel S. Janzen
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Patent number: 8677173Abstract: A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of packet from an input data stream to initialize a counter, a second detector for detecting a synchronization sequence, a token packet or a handshake packet in the data stream for the counter to carry out clock counting on the clock signal, and a trimming code controller for comparing the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.Type: GrantFiled: June 2, 2010Date of Patent: March 18, 2014Assignee: Elan Microelectronics CorporationInventors: Chun-Chi Wang, Tsung-Yin Chiang, Ching-Shun Lin
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Publication number: 20140075235Abstract: Devices and methods for synchronizing devices over a switched fabric. A switch receives a request packet from a device, transmits a completion packet to the device, determines an in-switch delay, and stores the in-switch delay. Another switch receives a packet from a first device, forwards the packet to a second device, determines an in-switch delay of the packet, and stores the in-switch delay. Storing of in-switch delays may include adding an in-switch delay to values in one or more transaction delay fields of a packet. Storing of in-switch delays may include storing the delays in a storage element of a switch. In-switch delay may be determined as a difference between a receiving time corresponding to reception of a packet and a forwarding or transmittal time corresponding to forwarding or transmitting of a packet.Type: ApplicationFiled: September 7, 2012Publication date: March 13, 2014Inventors: Sundeep Chandhoke, Rodney D. Greenstreet
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Patent number: 8671301Abstract: A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.Type: GrantFiled: October 26, 2007Date of Patent: March 11, 2014Assignee: LG Electronics Inc.Inventors: Hyung Sun Kim, Kang Soo Seo, Byung Jin Kim, Soung Hyun Um
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Patent number: 8671302Abstract: Methods and systems for operating a wireless clock system for multimedia datastream transmission and display. Source clock frames are compared with a reference clock frames and the clock difference are transmitted to a wireless clock receiver which also receives the same reference clock frames. Source clock frames are re-constructed using the reference clock frames, clock difference information and the receiver's local clock system.Type: GrantFiled: June 11, 2008Date of Patent: March 11, 2014Assignee: Picongen Wireless, Inc.Inventors: Sai Manapragada, Alvin Dale Kluesing
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Patent number: 8671303Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.Type: GrantFiled: January 12, 2012Date of Patent: March 11, 2014Assignee: Altera CorporationInventors: Yan Chong, Bonnie I. Wang, Chiakang Sung, Joseph Huang, Michael H. M. Chu
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Patent number: RE45109Abstract: A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.Type: GrantFiled: October 21, 2010Date of Patent: September 2, 2014Assignee: Pact XPP Technologies AGInventors: Martin Vorbach, Robert M. Munch