Synchronization Of Clock Or Timing Signals, Data, Or Pulses Patents (Class 713/400)
  • Patent number: 11909404
    Abstract: A clocking circuit is provided using a master delay-locked loop (DLL) and a slave DLL. A master DLL code indicates a delay adjustment made at a master DLL. A delay of a slave DLL is adjusted based on the master DLL code. A replica phase detector at the slave DLL is temporarily enabled during an interface idle period. A slave DLL code is determined, and a configuration value is determined based on the slave DLL code to the master DLL code. The replica phase detector is then disabled.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: February 20, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Huei Chu, Karthik Gopalakrishnan, Pradeep Jayaraman
  • Patent number: 11906580
    Abstract: A system, a method, and a machine-readable medium for overclocking a computer system is provided. An example of a method for overclocking a computer system includes predicting a stable operating frequency for a central processing unit (CPU) in a target system based, at least in part, on a model generated from data collected for a test system. An operating frequency for the CPU is adjusted to the stable operating frequency. A benchmark test is run to confirm that the CPU is operating within limits.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 20, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Suketu Partiwala, Hiren Bhatt, Dhruv Jain, Chihao Lo, Arnaud Froment
  • Patent number: 11899491
    Abstract: The system and method generates a pulse or a signal that is transmitted between a central processing unit or processor and an Ethernet integrated circuit card to program a trigger generator in the IC. The pulse is effectively a 1PPS signal that is provided to the IC, which may be in the form a field programmable gate array to enable timing synchronization. The trigger in the IC may also generates an interrupt to the processor so a driver in the CPU is instructed to set the next trigger. For the trigger to be accurately controlled, the control routine is implemented in the driver existing in kernel space rather than user space. A routine or protocol periodically polls the interrupt to determine when the trigger must be reset.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: February 13, 2024
    Inventors: Matthew J. Sherman, Mritunjay Sinha, Lawrence Yang
  • Patent number: 11900985
    Abstract: A clocking architecture for a memory module is configurable to independently select either rising or falling edges of an input clock as respective references for generation of an internal clock and an output clock. The clocking architecture supports reference edge selection in both a single data rate (SDR) mode and a double data rate (DDR) mode while maintaining a fixed phase relationship between the input clock and the output clock regardless of the reference edge selection.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: February 13, 2024
    Assignee: RAMBUS INC.
    Inventors: Panduka Wijetunga, Abhishek Desai
  • Patent number: 11886935
    Abstract: A method and system of providing users with a tool to interact with content from a primary app through a secondary app are disclosed. The secondary app obtains source data from the primary app and determines whether the data includes labels that can trigger the application of a particular configuration in the presentation of the content. Changes made to the source data in the secondary app that relate to substantive or key data for the content do not affect the source data in the primary app. However, changes made in the secondary app that relate to non-substantive data can be propagated back to the primary app.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: January 30, 2024
    Assignee: United Services Automobile Association (USAA)
    Inventors: Nathan Ryan Johnson, Julia Beatrice Isaac, Isidoro Garcia, Nathaniel Brett Wiatrek
  • Patent number: 11881907
    Abstract: Aspects present herein relate to methods and devices for wireless communication including an apparatus, e.g., a UE. The apparatus may measure a frequency error from a first pair of pilot symbols and a second pair of pilot symbols received via a channel associated with communication between the UE and a base station, the measured frequency error from the first pair of pilot symbols and the second pair of pilot symbols corresponding to a first frequency error measurement and a second frequency error measurement. The apparatus may detect a first frequency wraparound in the first frequency error measurement and a second frequency wraparound in the second frequency error measurement. The apparatus may adjust the first frequency error measurement based on the first frequency wraparound or the second frequency error measurement based on the second frequency wraparound if the first frequency wraparound or the second frequency wraparound is the non-zero value.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: January 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Aswin R C, Manav Lnu
  • Patent number: 11867756
    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: January 9, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 11842199
    Abstract: An asynchronous pipeline includes a first stage and one or more second stages. A controller provides control signals to the first stage to indicate a modification to an operating speed of the first stage. The modification is determined based on a comparison of a completion status of the first stage to one or more completion statuses of the one or more second stages. In some cases, the controller provides control signals indicating modifications to an operating voltage applied to the first stage and a drive strength of a buffer in the first stage. Modules can be used to determine the completion statuses of the first stage and the one or more second stages based on the monitored output signals generated by the stages, output signals from replica critical paths associated with the stages, or a lookup table that indicates estimated completion times.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: December 12, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Greg Sadowski, John Kalamatianos, Shomit N. Das
  • Patent number: 11831745
    Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: November 28, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Paul Rowland
  • Patent number: 11828479
    Abstract: An air conditioning system includes an air conditioner and an adapter that connects the air conditioner and an external server device. The adapter includes a first updating unit and a second updating unit. The first updating unit updates, when a new learning model that provides a recommended operation to a control unit included in the air conditioner is received from the external server device, the learning model by using a first update method. The second updating unit updates, when an update purpose control program that updates a control program for the air conditioner is received from the external server device, the update purpose control program by using a second update method that is different from the first update method. It is possible to reduce an adapter load by updating the learning model and the control program by using different methods.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 28, 2023
    Assignee: FUJITSU GENERAL LIMITED
    Inventors: Tomofumi Kawai, Yutaka Shimamura, Masae Kitajima, Koichi Kitami
  • Patent number: 11830576
    Abstract: A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: November 28, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinya Koizumi
  • Patent number: 11821946
    Abstract: Testing clock division circuitry includes generating pseudo random test pattern bits for scan chain logic in programmable clock division logic circuitry and divided clock counter circuitry. A shift clock is used to shift the test pattern bits into the scan chain logic. A capture clock signal is used in the programmable clock division logic during a non-test mode of operation. The shift clock is used to provide output shift bits from the scan chain logic to a multi-input shift register (MISR). Once all the output shift bits for the test pattern bits are provided to the MISR, a final test signature from the MISR is compared to an expected test signature to determine whether the programmable clock division logic circuitry and divided clock counter circuitry are free of faults.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: November 21, 2023
    Assignee: NXP USA, Inc.
    Inventors: Jorge Arturo Corso Sarmiento, Anurag Jindal
  • Patent number: 11823770
    Abstract: The present disclosure discloses a memory access interface device. A data processing circuit receives a data signal including 2M pieces of data from a memory device. A sampling clock generation circuit receives a data strobe signal from the memory device to generate a valid data strobe signal having P valid strobe pulses and further generate a sampling clock signal accordingly, in which P is larger than M. A sampling circuit samples the data signal according to the sampling clock signal to generate sampling results. A control circuit determines valid sampling results according to a time difference between the valid data strobe signal and the data signal and outputs valid data generated according to the valid sampling results as a read data signal to a memory access controller.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: November 21, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ger-Chih Chou, Chih-Wei Chang, Li-Jun Gu, Chun-Chi Yu, Fu-Chin Tsai
  • Patent number: 11809609
    Abstract: Various implementations described herein are directed to a device with a reset tree having leaf buffers that provide sensed output signals based on a reset-synchronizing input signal. The device may have a first sensor that receives the sensed output signals from the leaf buffers of the reset tree and provides an attack detection signal based on sensing a malicious attack. The device may have a second sensor that receives the reset-synchronizing input signal, receives the attack detection signal from the first sensor and provides a reset alarm signal based on duration of a timing glitch associated with comparing a difference between the reset-synchronizing input signal and the attack detection signal.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: November 7, 2023
    Assignee: Arm Limited
    Inventors: Shashank Guruprasad, Roma Rudra, Abhishek Tripathi
  • Patent number: 11804921
    Abstract: Disclosed is a method of determining time in a digital processing system, comprising, in a present cycle of a first digital clock: accessing a reference time counter for a reference digital clock, wherein the reference time counter increments in value by a fixed amount at every cycle of the reference digital clock, the reference digital clock being of a higher accuracy than the first digital clock; accessing a first time counter for the first digital clock, wherein the first time counter increments in value by an updatable increment amount at each cycle of the first digital clock; and comparing at least one part of the reference time counter with at least one corresponding part of the first time counter. Based on the comparing, an adjustment is made to one or more attributes of the first time counter, so that first time counter at least approximates the reference time counter.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: October 31, 2023
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Matthew Chapman, Ka-Shu Wong
  • Patent number: 11799577
    Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: October 24, 2023
    Assignee: Google LLC
    Inventors: Yuliang Li, Gautam Kumar, Nandita Dukkipati, Hassan Wassel, Prashant Chandra, Amin Vahdat
  • Patent number: 11777406
    Abstract: Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: October 3, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tawen Mei, Karen Huimun Chan
  • Patent number: 11775005
    Abstract: An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases that are synchronized by generating a common clock signal from a clock generator of the first SoC and simultaneously applying the common clock signal to a first counter of the first SoC and a second counter of the second SoC whereby the first counter and the second counter count clock edges of the common clock. The clock counts are shared through an interface between the first SoC and the second SoC and compared to each other. When the clock counts are different, a clock count of the first counter or the second counter is adjusted to cause the clock counts to match each other. The adjusted clock count is synchronized to the respective clocks of the first and second SoCs, thus synchronizing the first and second SoCs to each other.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: October 3, 2023
    Assignee: Snap Inc.
    Inventors: Samuel Ahn, Jason Heger, Dmitry Ryuma
  • Patent number: 11755441
    Abstract: The present invention discloses a debugging unit and a processor. The debugging unit includes; a register, adapted to sample input data under control of a clock signal; and a dock control unit, adapted to generate a control signal based on a clock enable signal to control the clock signal, so that the register is controlled to sample the input data in a validity period of the clock signal when the control signal is valid. The present invention also discloses a corresponding system-on-chip and an intelligent device including the system-on-chip.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: September 12, 2023
    Assignee: Alibaba Group Holding Limited
    Inventors: Manzhou Wang, Ruqin Zhang
  • Patent number: 11755096
    Abstract: A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: September 12, 2023
    Assignee: Silicon Laboratories Inc.
    Inventors: Partha Sarathy Murali, Suryanarayana Varma Nallaparaju, Kriyangbhai Vinodbhai Shah, Venkata Rao Gunturu, Subba Reddy Kallam, Mani Kumar Kothamasu
  • Patent number: 11750484
    Abstract: A monitoring system monitors processing of incoming messages and logs data related to performance of an application that processes the messages. The monitoring system temporarily associates reusable identifiers with the messages and logs data upon each message traversing different points in the application. Each of the identifiers is sized such that the storage space necessary to store the identifier is less than the storage space necessary to store an identifier sized to uniquely identify all of the plurality of messages, and the identifiers and the logged data are configured to minimize a performance penalty of monitoring the application. The monitoring system parses the data, e.g., during post-processing, to determine, from a plurality of data entries that refers to the same identifier, a subset of the data entries where the same identifier was associated with the same message.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: September 5, 2023
    Assignee: Chicago Mercantile Exchange Inc.
    Inventor: Kyle Dennis Kavanagh
  • Patent number: 11748141
    Abstract: Providing clock times to virtual devices. In one embodiment, a method includes identifying a real-time clock device of a host computing device. The host computing device comprises a hypervisor and a virtual machine. The method also includes determining that a virtual device used by the virtual machine will use clock times obtained from the real-time clock device. The method further includes obtaining, by a processing device of the host computing device, a current clock time from the real-time clock device of the host computing device. The method further includes providing the current clock time to the virtual device.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: September 5, 2023
    Assignee: Red Hat, Inc.
    Inventors: Yuval Kashtan, Gal Hammer
  • Patent number: 11743277
    Abstract: The present invention comprises a novel system and method to detect and estimate the time-frequency span of wireless signals present in a wideband RF spectrum. In preferred embodiments, the Faster RCNN deep learning architecture is used to detect the presence of wireless transmitters from the spectrogram images plotted by searching for rectangular shapes of any size, then localize the time and frequency information from the output of the FRCNN deep learning architecture.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: August 29, 2023
    Inventors: Naga Raghavendra Surya Vara Prasad Koppisetti, Kevin Bradley D'Souza, Hamidreza Boostanimehr, Shankhanaad Mallick
  • Patent number: 11727979
    Abstract: Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kallol Mazumder, Navya Sri Sreeram, William C. Waldrop, Vijayakrishna J. Vankayala
  • Patent number: 11720140
    Abstract: A computing device may perform a method that includes determining whether internal time reference data is available while booting the computing device. When the internal time reference data is unavailable, the device clock is set to a default time setting. However, when the internal time reference data is available while booting the computing device, the method includes searching the internal time reference data for a most recent time reference, and setting the device clock to a current time setting based on the most recent time reference.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: August 8, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Dennis LaCroix
  • Patent number: 11714737
    Abstract: In some examples, an electronic device records, in an entry of a time-state data structure that includes a plurality of entries to store respective times, a time in response to invocation of a time-lapse process that lasts a predefined time duration independently of a time clock of the electronic device. The electronic device determines whether times in successive entries of the plurality of entries of the time-state data structure are within a threshold of one another, the threshold based on the predefined time duration. Based on the determining, the electronic device sets a parameter representing a quality of the time clock.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: August 1, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Robert Raymond Neal-Joslin
  • Patent number: 11709522
    Abstract: Embodiments herein describe techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as “cards”) by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 25, 2023
    Assignee: XILINX, INC.
    Inventors: Sebastian Turullols, Ravinder Sharma, Siva Santosh Kumar Pyla, Raj Kumar Rampelli, Deboleena Minz Sakalley, Nilay Shah
  • Patent number: 11706014
    Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: July 18, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Natan Manevich, Dotan David Levi, Wojciech Wasko, Ariel Almog, Bar Shapira
  • Patent number: 11704258
    Abstract: A method can include: receiving, in a memory device, a read request from a host device that is coupled to the memory device by an interface; decoding an address of the read request that is received from the interface; decoding a command of the read request to determine whether the read request is for an aligned address operation; maintaining the decoded address without modification when the read request is determined as being for the aligned address operation regardless of an actual alignment of the decoded address; and executing the read request as the aligned address operation on the memory device by using the decoded address.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: July 18, 2023
    Assignee: Dialog Semiconductor US Inc.
    Inventor: Gideon Intrater
  • Patent number: 11696247
    Abstract: A hub may receive event data captured by a body-worn device and store the event data in a memory of the hub. The event data is then backed up from the hub to a memory of an additional hub communicatively connected to the hub. A copy of event data for a predetermined period of time as included in the event data is then transferred from the memory of the hub to a data store of a network operations center (NOC). In response to the transfer being complete, the hub may delete the event data for the predetermined period of time, send a first command to the additional hub directing the additional hub to delete a backup of the event data for the predetermined period of time, or send a second command to the body-worn device directing the body-worn device to delete the event data for the predetermined period of time.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: July 4, 2023
    Assignees: Getac Technology Corporation, WHP Workflow Solutions, Inc.
    Inventors: Thomas Guzik, Muhammad Adeel
  • Patent number: 11687320
    Abstract: The disclosure relates to detecting phase slips that may occur in a multi-lane serial datalink. Phase slips may occur when a lane experiences lane skew, which may introduce a phase slip with respect to another lane. To detect phase slippage, the system may select a reference lane from among the lanes. The system may generate a pre-deskew delta value based on a difference between the FIFO filling level of the reference lane before a deskew and the FIFO filling level of a second lane before the deskew. The system may generate a post-deskew delta value based on a difference between the FIFO filling level of the reference lane after the deskew and the FIFO filling level of the second lane after the deskew. The system may use a difference between the post-deskew delta and the pre-deskew delta to detect phase slip on the second lane relative to the reference lane.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: June 27, 2023
    Assignee: VIAVI SOLUTIONS INC.
    Inventor: Reiner Schnizler
  • Patent number: 11681324
    Abstract: Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: June 20, 2023
    Assignee: Achronix Semiconductor Corporation
    Inventors: Namit Varma, Sarma Jonnavithula, Mohan Krishna Vedam, Christopher C. LaFrieda, Virantha N. Ekanayake
  • Patent number: 11683149
    Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: June 20, 2023
    Assignee: Apple Inc.
    Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Jean-Didier Allegrucci, Jeffrey J. Irwin, Kalpana Bansal, Michael Bekerman, Remi Clavel
  • Patent number: 11681457
    Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: June 20, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Gyu Lee, Reum Oh, Ki Heung Kim, Moon Hee Oh
  • Patent number: 11677403
    Abstract: A delay lock loop circuit includes a receiver, a delay line circuit, a clock signal generator and a phase detecting circuit. The receiver receives a clock signal and a reference voltage and generates a reference clock signal according to the clock signal and the reference voltage. The delay line circuit is coupled to the receiver and generates a delayed clock signal by delaying the reference clock signal with a delay indication signal. The clock signal generator generates an output clock signal according to the delayed clock signal. The phase detecting circuit generates a detection result by sampling the reference clock signal with a feedback clock signal generated by the output clock signal, and generates the delay indication signal according to a digital value of the detection result.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: June 13, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11677741
    Abstract: System and method for secure time synchronization in an industrial facility, wherein a synchronization request of a facility component is transmitted to a registration service of a certificate management of the facility and the synchronization request is examined by the registration service, where the synchronization request includes a signature of the requesting facility component, and where depending on an outcome of the examination, a synchronization response is then transmitted to the requesting facility component a system time of the facility component is matched to a system time of the registration service based on the synchronization response.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: June 13, 2023
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Jochen Balduf, Anna Palmin
  • Patent number: 11671278
    Abstract: The present disclosure is directed to systems and methods directed to improving the functions of a vehicle. Systems and methods are provided that provide a custom tool that autogenerates a set of software agents that allows a system to separate processing, transmission and receiving of messages to achieve better synchronization. The disclosure herein also provides a simplified method of key provisioning by designating one client as a server and assigning a symmetric key to every other client permanently provisioned between that client and the server. Systems and method are further provided that predict faults in a vehicle. Systems and methods are also provided that preserve data in the event of a system crash. Systems and methods are also provided in which an operating system of a vehicle detects the presence of a new peripheral and pulls the related interface file for that new peripheral. Further, a data synchronization solution is provided herein which provides optimized levels of synchronization.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: June 6, 2023
    Assignee: Rivian IP Holdings, LLC
    Inventors: Shayan Mukhtar, Richard Stephen Chelminski
  • Patent number: 11671238
    Abstract: A line card of a network box receives a SYNC input signal and generates a first time stamp based on receipt of the SYNC input signal. The line card generates a system clock signal in a phase-locked loop and generates a SYNC output signal by dividing the system clock signal in a divider circuit. The SYNC output signal is fed back to an input terminal as a SYNC feedback signal. A time stamp is generated based on receipt of the SYNC feedback signal. The line card determines a time between the SYNC input signal and the SYNC feedback signal based on the first time stamp and the second time stamp. The timing of the SYNC output signal is adjusted based on the time difference using a coarse time adjustment by adjusting a divide ratio of the divider circuit and using a fine time adjustment in the phase-locked loop based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 6, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventor: Vivek Sarda
  • Patent number: 11660149
    Abstract: Electronic devices that detect their position and/or orientation with respect to earth's frame of reference are described. A coupler can removeably maintain the electronic devices in physical proximity of one another. Each electronic device can have a housing and the coupler can be included on the housing and arranged to physically connect the housing of the electronic device to the housing of at least one other electronic device. Alternatively, the coupler can be a packaging that maintains the electronic devices in physical proximity of one another. Each electronic device can be calibrated using the orientation or position information obtained by other electronic devices maintained by the coupler. Further, each electronic device can include a power source that remains inactive until the device is ready for use.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: May 30, 2023
    Assignee: DEPUY SYNTHES PRODUCTS, INC.
    Inventors: William Frasier, John Riley Hawkins, Roman Lomeli, Mark Hall, Dennis Chien
  • Patent number: 11664968
    Abstract: A line card receives a SYNC input signal and a first system clock signal. The line card generates a second system clock signal in a PLL and generates a SYNC output signal by dividing the second system clock signal in a divider circuit. The SYNC output signal is fed back as a SYNC feedback signal. The line card determines determining a closest edge of the first system clock signal to a transition of the SYNC input signal and determines a time difference between the closest edge of the first system clock signal and a transition of the SYNC feedback. The SYNC output signal is adjusted based on the time difference using a coarse adjustment by adjusting a divide ratio of the divider circuit and using a fine adjustment in the PLL based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: May 30, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventor: Vivek Sarda
  • Patent number: 11659383
    Abstract: Methods, systems, and devices for wireless communications are described. A first wireless device may communicate, with a second wireless device, a first set of messages of a first message type that are acknowledged according to an acknowledgement procedure. The first wireless device, the second wireless device, or both may select a first subset of messages of the first plurality of messages and a first subset of bits from each message of the first subset of messages based on the first set of messages being acknowledged and according to a sampling configuration common to both the first wireless device and the second wireless device. The first wireless device, the second wireless device, or both may generate a key using bit values of the first subset of bits from each message of the first subset of messages, encoding a message using the key, and communicate the encoded message.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: May 23, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Noam Zach, Guy Wolf, Sharon Levy, Ory Eger, Ori Ben Shahar, Lior Uziel, Assaf Touboul
  • Patent number: 11657010
    Abstract: Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with the bus. Intrinsic noise and jitter are used to increase the precision of the measurements, thereby essentially using these uncertainties as self-dithering for increased measurement resolution. During adaption, delays may be adjusted in multiple step sizes to speed adaption time.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: May 23, 2023
    Assignee: Google LLC
    Inventor: Jens Kristian Poulsen
  • Patent number: 11645035
    Abstract: An audio signal processing graph is automatically recomposed to optimize its properties by reassigning and instantiating its nodes on available locales such that the number of inter-locale connections is minimized and latency between inputs, such a performer's live input, and outputs, such as a monitored recording mix, is minimized. The recomposition exploits associative, commutative, and decomposition properties of certain node types, including mixer nodes. A graph recomposition may decompose a mixer node into a first stage instantiated by a software plug-in hosted by a computer running a digital audio workstation in a first locale, and a second stage assigned to an audio processing device in a second locale. Automatic signal graph recomposition occurs when the system is initialized, the graph is reconfigured, a new desired behavior of the graph is specified, or the available network resources are changed.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: May 9, 2023
    Assignee: AVID TECHNOLOGY, INC.
    Inventors: Paul A. Vercellotti, Robert E. Majors, Kyle M. Splittgerber
  • Patent number: 11644808
    Abstract: To efficiently collect and transfer monitoring target data in a PLC. The PLC includes a first execution engine, a holding section, and a second execution engine. Further, the PLC collects data stored in a collection target holding section according to predetermined collection setting, accumulates collected time-series data in a first buffer, and transfers the time-series data stored in the first buffer to the second execution engine via a bus. The second execution performs data processing of the transferred time series data, generates display data to be displayed on a dashboard, and provides the display data to an external computer.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 9, 2023
    Assignee: KEYENCE CORPORATION
    Inventor: Tatsuya Nakamura
  • Patent number: 11645216
    Abstract: An information handling system may include a bus initiator, a plurality of bus endpoints, and a single-wire bus communicatively coupled between the bus initiator and the plurality of bus endpoints, wherein the bus comprises a multiplexer. The bus initiator may be configured to perform in-band addressing to select a communications channel through the multiplexer via an addressing protocol that uses pulse bursts for initiation of the addressing, identification of the communications channel, and termination of the addressing. Pulses of the pulse bursts may be sufficiently short in duration to pass through filters of the bus endpoints such that the pulse bursts are not processed by the bus endpoints.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 9, 2023
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Michael J. Stumpf, Jeffrey L. Kennedy
  • Patent number: 11641315
    Abstract: An object is to provide a traffic monitoring method, a traffic monitoring apparatus, and a program capable of efficiently merging data structures of each of the cores in a multi-core environment without reconstructing a data structure, retrieving a data structure, and adjusting the RSS function. In the traffic monitoring method according to an embodiment of the present invention, the elements of the data structures formed in the cores are compared for each item, and statistic values in the elements are brought together into any one of the elements, and the statistic values of the other elements are set to zero. Redundant elements between the data structures can be removed by ignoring elements having a statistic value of zero at the time of merging data structures.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: May 2, 2023
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Toru Mano, Hitoshi Masutani, Junki Ichikawa
  • Patent number: 11637955
    Abstract: An image capturing device includes an image capturing unit capturing an image at a timing based on a first frame rate and outputs data corresponding to the image after a first period, an image data generation unit generating image data based on the output data and outputting the image data after a second period, a display unit displaying a display image based on the image data after the second period and at a timing based on a second frame rate, and a mode selecting unit selecting a first or second mode. The first mode prioritizes reduction in a display delay time. The second mode prioritizes image quality of the display image over reduction in the display delay time. A total period of the first and second periods is less than or equal to a first vertical synchronization period based on the first frame rate when the first mode is selected.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: April 25, 2023
    Assignee: Seiko Epson Corporation
    Inventor: Ryuichi Shiohara
  • Patent number: 11606427
    Abstract: A synchronized communication system includes a plurality of network communication devices, one of which is designated as a root device and the others designated as slave devices. Each network communication device includes one or more ports and communications circuitry, which processes the communication signals received by the one or more ports so as to recover a respective remote clock from each of the signals. A synchronization circuit is integrated in the root device and provides a root clock signal, which is conveyed by clock links to the slave devices. A host processor selects one of the ports of one of the network communication devices to serve as a master port, finds a clock differential between the root clock signal and the respective remote clock recovered from the master port, and outputs, responsively to the clock differential, a control signal causing the synchronization circuit to adjust the root clock signal.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: March 14, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dotan David Levi, Avraham Ganor, Arnon Sattinger, Natan Manevich, Reuven Kogan, Artiom Tsur, Ariel Almog, Bar Shapira
  • Patent number: 11601698
    Abstract: Systems and methods for intelligent synchronization of media streams are provided. A server may receive streams corresponding to an interactive session and sent over a communication network from user devices in the interactive session. A predetermined attribute may be identified as present in each of the streams, but received at different times by the server. The server may determine a time difference between a time that a predetermined attribute in a first stream of the streams was received and a time that the predetermined attribute in a second stream of the streams was received. The first stream and the second stream may then be synchronized using the time difference and provided to a recipient device.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: March 7, 2023
    Assignee: SUPER LEAGUE GAMING, INC.
    Inventors: Brian Gramo, Arthur Kmbikyan, David Steigelfest
  • Patent number: 11595137
    Abstract: an orthogonal frequency division multiplexed (OFDM) output signal produced by a device in response to an OFDM input signal is accessed. The OFDM input signal includes OFDM input symbols in the time domain and the OFDM output signal includes OFDM output symbols in the time domain. The OFDM output symbols are time-aligned to the OFDM input symbols and a phase of the OFDM output signal is de-rotated with respect to the OFDM input signal. A complex equalization filter is applied to the OFDM output symbols in the time domain to obtain an estimate of the OFDM input symbols A distortion signal of the OFDM output signal is determined by subtracting the estimate of the OFDM input symbols. An error vector magnitude (EVM) is determined by dividing a root mean square of the distortion, by a root mean square of the OFDM input signal.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: February 28, 2023
    Assignee: Keysight Technologies, Inc.
    Inventor: Rishi Mohindra