Abstract: A method of operation in a memory controller is disclosed. The method includes receiving a strobe signal having a first phase relationship with respect to first data propagating on a first data line, and a second phase relationship with respect to second data propagating on a second data line. A first sample signal is generated based on the first phase relationship and a second sample signal is generated based on the second phase relationship. The first data signal is received using a first receiver clocked by the first sample signal. The second data signal is received using a second receiver clocked by the second sample signal.

Abstract: Embodiments of the disclosure provided herein generally include a system and a method of configuring and/or controlling the transfer of information between two or more electronic devices due to the interaction of an electronic device and a host identifier signal generating system. Embodiments of the disclosure may include a system and a method of distributing useful information received by or contained within a memory of the electronic device based on the receipt of a host identifier signal. The electronic device may then perform one or more desirable functions or processes based the portable electronic device's interaction with the host identifier signal generating system.

Abstract: Creation and use of a digital twin instance (DTI) for a physical instance of the part. The DTI may be created by a model inversion process such that model parameters are iterated until a convergence criterion related to a physical resonance inspection result and a digital resonance inspection result is satisfied. The DTI may then be used in relation to part evaluation including through simulated use of the part. The physical instance of the part may be evaluated by way of the DTI or the DTI may be used to generate maintenance schedules specific to the physical instance of the part.

Abstract: Techniques are provided herein for pre-emptively reinforcing one or more buses of a computing device against the effects of signal noise that could cause a reduction in signal integrity. The techniques generally include detecting an event (or “trigger”) that would tend to indicate that a reduction in signal integrity will occur, examining a reinforcement action policy and system status to determine what reinforcement action to take, and performing the reinforcement action.

Abstract: Instructions can be executed to determine a quantity of logical units that are part of a memory device. The instructions can be executed to operate the logical units with a programming time sufficient to provide a required throughput for storage of time based telemetric sensor data received from a host. The instructions can be executed to operate the logical units with a trim that correspond to the programming time.

Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.

Abstract: In one embodiment, the present disclosure includes multichip timing synchronization circuits and methods. In one embodiment, hardware counters in different systems are synchronized. Programs on the systems may include synchronization instructions. A second system executes synchronization instruction, and in response thereto, synchronizes a local software counter to a local hardware counter. The software counter on the second system may be delayed a fixed period of time corresponding to a program delay on the first system. The software counter on the second system may further be delayed by an offset to bring software counters on the two systems into sync.

Abstract: Methods, systems, apparatuses, and computer program products are provided for prefetching data. A workload analyzer may identify job characteristics for a plurality of previously executed jobs in a workload executing on a cluster of one or more compute resources. For each job, identified job characteristics may include identification of an input dataset and an input bandwidth characteristic for the input dataset. A future workload predictor may identify future jobs expected to execute on the cluster based at least on the identified job characteristics. A cache assignment determiner may determine a cache assignment that identifies a prefetch dataset for at least one of the future jobs. A network bandwidth allocator may determine a network bandwidth assignment for the prefetch dataset. A plan instructor may instruct a compute resource of the cluster to load data to a cache local to the cluster according to the cache assignment and the network bandwidth assignment.

Abstract: A low-power coherent receiver is enabled with enhanced performance for intra-datacenter reach optical interconnection applications using several techniques. The first is a coherent skew adjustment technique which enables lower-power baud-rate ADC sampling and baud-rate-spaced coherent equalization. The second is a real-valued or mixed-valued low-power coherent equalization technique, where a single-tap real-valued 4×4 MIMO equalizer plus four real-valued or two mixed-valued single-input single-out (SISO) equalizers are used for simultaneous polarization recovery, in-phase and quadrature (I/Q) phase error correction, and bandwidth equalization. The third is a power-efficient dual-DSP architecture to enhance coherent receiver performance, in which a complementary low-speed coherent DSP is introduced for optimal I/Q phase error correction and constellation decision parameters determination through more sophisticated algorithms that are too power hungry to be implemented in the primary high-speed DSP.

Abstract: In an aspect, a UE may perform clock synchronization in accordance with a first network timing reference, such as a unicast network timing reference (UNTR) or a broadcast networking timing reference (BNTR). The UE may detect event(s) associated with a connection to a BS, which may trigger a switch between the UNTR and the BNTR for clock synchronization. In a further aspect, a communications device (e.g., UE or BS) may determine to transition a UE between the BNTR and UNTR for clock synchronization, and may perform one or more actions to facilitate the network timing reference transition.

Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

Abstract: The present invention provides a System and method for multi-tiered data synchronization. Data is synchronized between a master synchronization server, one or more proxy synchronization servers, and client devices. Client devices establish synchronization sessions with either a proxy synchronization server or a master synchronization server, depending on which server provides the “best” available connection to that client device. Each proxy synchronization server synchronizes data with client devices that have established a synchronization session with such proxy synchronization server. The master synchronization server synchronizes data with client devices that have established a synchronization session with the master synchronization server. Each proxy synchronization server synchronizes data with the master synchronization server. Metadata associated with synchronized files is synchronized throughout the system in real-time. Files may be synchronized in real-time or of a delayed time.

Abstract: Provided are an electronic device and a method of controlling an external device by the electronic device. According to various embodiments of the present disclosure, a method of controlling an external device by an electronic device includes displaying, on a screen, a first user interface (UI) corresponding to first UI data received from an external server, transmitting, to the external device, second UI data corresponding to the first UI, receiving, from the external device, coordinates selected by a user using the external device, obtaining additional information related to the first UI when the coordinates correspond to a position of the first UI displayed on the screen, and transmitting, to the external device, the additional information and an execution command of an application using the additional information.

Abstract: Disclosed herein is an apparatus that includes a first shift register circuit including a plurality of first latch circuits coupled in series, and a second shift register circuit including a plurality of second latch circuits coupled in series. The first and second shift register circuits are cyclically coupled. Each of the first latch circuits is configured to perform the latch operation in synchronization with a rise edge of a first clock signal. Each of the second latch circuits is configured to perform the latch operation in synchronization with a fall edge of a first clock signal when a first selection signal is in a first state. One or more first latch circuits and one or more second latch circuits are configured to be bypassed when a second selection signal indicates a predetermined value.

Abstract: A method for adjusting the signal frequency includes: acquiring a first number of times of outputting a reference signal at an active level within a reference duration, wherein a correlation between a frequency of the reference signal and temperature is less than a reference correlation threshold, the reference duration is negatively correlated with a frequency of a clock signal, a correlation between a frequency of a clock signal and temperature is greater than the reference correlation threshold, and a drive signal for driving a display device to display an image is generated based on the clock signal; acquiring a target adjustment value based on the first number of times if the first number of times is different from a reference number of times; and controlling and adjusting the frequency of the output clock signal based on the target adjustment value.

Abstract: A power module according to the first embodiment incorporates a power device, and drives the power device by using a control signal acquired from a microcomputer being a control circuit. The power module includes: a plurality of first terminals that receive input of the control signal from the microcomputer; a main circuit that drives the power device based on the control signal, and detects an abnormality of the power module; an error output circuit that outputs an error signal from a second terminal to the microcomputer when the abnormality is detected by the main circuit; and a switching circuit that causes the first terminal to operate as an output terminal for the microcomputer when the error signal is output. Information of the power device is output from the first terminal operating as the output terminal to the microcomputer.

Abstract: A semiconductor device includes a memory device configured to have a first buffer and a second buffer, the first buffer storing a plurality of requests sent to a plurality of destinations, the second buffer storing identification information of the entry associated with a first destination of a first request written to first buffer; and an entry selector configured to identify the first destination from the plurality of destinations when the identification information of the entry is stored in the second buffer, and to read the first request from the plurality of requests stored in the first buffer by using the first destination.

Abstract: Automated correlation of process attribute value changes with events related to the changes. A managed historian utilizes a namespace property to correlate process tag values with corresponding events. The managed historian generates and provides to remote user devices a graphical user interface that includes a plot of data values of the process tag and a visual icon representing the event overlaid atop the plot of data values.

Abstract: A parameter synchronization method is implemented in a computing device. The parameter synchronization method includes importing a deep learning training task of a preset model into a server communicatively coupled to the computing device, recording a preset number of iterative processes during the deep learning training, dividing each iterative process into a number of phases according to time, determining whether a time ratio of an H2D phase, a D2H phase, and a CPU phase in each iterative process is greater than a preset value, and confirming the server to use a copy mode for performing parameter synchronization when the time ratio of the H2D, D2H, and CPU phases is determined to be greater than the preset value.

Abstract: Techniques for network latency estimation in a computer network are disclosed herein. One example technique includes instructing first and second nodes in the computer network to individually perform traceroute operations along a first round-trip route and a second round-trip route between the first and second nodes. The first round-trip route includes an inbound network path of an existing round-trip route between the first and second nodes and an outbound network path that is a reverse of the inbound network path. The second round-trip route has an outbound network path of the existing round-trip route and an inbound network path that is a reverse of the outbound network path. The example technique further includes upon receiving traceroute information from the additional traceroute operations, determine a latency difference between the inbound and outbound network paths of the existing round-trip route based on the received additional traceroute information.

Abstract: One example includes a clock distribution system. The system includes a resonator feed network comprising a plurality of resonant transmission lines that each propagate a clock signal. The system also includes at least one resonator spine. Each of the at least one resonator spine can be conductively coupled to at least one of the resonant transmission lines, such that each of the at least one resonator spine propagates the clock signal. The system further includes at least one resonator rib conductively coupled to at least one of the at least one resonator spine. Each of the at least one resonator rib can be arranged as a standing wave resonator to propagate the clock signal.

Abstract: Systems, devices, and methods are described herein for aligning a phase of a ring oscillator and removing jitter. An oscillator includes a resistor bank array, an operational amplifier, a first and second transistor, and a realignment circuit. The resistor bank array has a plurality of resistors configured to generate a first signal. The operational amplifier is coupled to a PLL circuit and is configured to compare a voltage of the PLL circuit with a voltage of the resistor bank array. The first transistor is coupled between the operational amplifier and a ring oscillator. The first transistor is configured to generate a second signal to control a frequency of the ring oscillator during a realignment state. The realignment circuit is coupled to the first transistor and the ring oscillator. The realignment circuit is configured to generate a realignment signal to align the ring oscillator with a first clock signal.

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

Abstract: According to certain embodiments, a method in a network node for delivering a time synchronization service comprises obtaining a timing accuracy threshold for a time synchronization service provided to a wireless device; determining, based on a first timing accuracy error at the network node and a second timing accuracy error between the network node and the wireless device, that a timing accuracy of the time synchronization service is equal or superior to the timing accuracy threshold, and transmitting the time synchronization service to the wireless device with a timing accuracy equal or superior to the timing accuracy threshold. The method further comprises, in response to determining that the timing accuracy of the time synchronization service is inferior to the timing accuracy threshold, reconfiguring the network node to improve the timing accuracy of the time synchronization service.

Abstract: The disclosure pertains to a method for operating a user equipment in a radio access network. The method includes measuring first synchronisation signaling associated to a first cell of the radio access network, wherein for measuring a set of parametrisations of the first synchronisation signaling is utilised, in which the set of parametrisations is determined based on a signaling parametrisation of second synchronisation signaling associated to a second cell of the radio access network, and further based on a mapping of the signaling parametrization to the first set of parametrisations. The disclosure also pertains to related methods and devices.

Abstract: In one embodiment, a method for managing clock synchronization for a baseboard management controller includes identifying, by a management unit of the information handling system, a real-time clock of the information handling system based on a real-time clock time value; receiving, by the management unit, a request for the real-time clock time value from the baseboard management controller; retrieving, by the management unit, the real-time clock time value from the real-time clock; sending, by the management unit, the real-time clock time value to a logic device of the information handling system; sending, by the logic device, an interrupt signal to the baseboard management controller indicating that the real-time clock time value is stored; retrieving, by the baseboard management controller, the real-time clock time value from the logic device; and updating, by the baseboard management controller, a baseboard management controller time value based on the real-time clock time value.

Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.

Abstract: An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.

Abstract: Certain aspects provide techniques for disambiguating graph data. In one example, a method includes receiving entity data from a data source in a first format; converting the entity data in the first format to a second format, wherein the second format is a standardized input format for a disambiguation pipeline; determining a blocked data set from the entity data in the second format based on a blocking parameter, wherein: the blocked data set comprises data regarding a first plurality of entities, and the first plurality of entities is a subset of a second plurality of entities represented in the entity data from the data source; matching at least two entities in the first plurality of entities in the blocked data set; merging the at least two entities into a single entity; generating a unique ID for the single entity; and importing the single entity into a graph database.

Abstract: Creation and use of a digital twin instance (DTI) for a physical instance of the part. The DTI may be created by a model inversion process such that model parameters are iterated until a convergence criterion related to a physical resonance inspection result and a digital resonance inspection result is satisfied. The DTI may then be used in relation to part evaluation including through simulated use of the part. The physical instance of the part may be evaluated by way of the DTI or the DTI may be used to generate maintenance schedules specific to the physical instance of the part.

Abstract: A method of virtualizing a clock is executed by a network controller comprising a processor and computer-readable instructions for creating one or more virtual network elements comprising one or more virtual clocks. The method comprises retrieving, at a first virtual network element of the one or more virtual network elements, a first time of day value and a second time of day value. The method further comprises adjusting the amount of time elapsed based, in part, on a frequency adjustment value and incrementing a clock value based on the amount of time elapsed.

Abstract: The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

Abstract: To optimize an operation of a manufacturing facility by presenting a countermeasure for improving quality, even in a manufacturing process where the product quality changes even under constant manufacturing conditions. A countermeasure recommendation device includes a data acquisition unit for collecting a plurality of pieces of facility data, and assigning a label for each process to each piece of the facility data; a countermeasure detection unit for creating countermeasure record data; a countermeasure recommendation unit for calculating the characteristic amount, extracting the characteristic amount, and selecting the countermeasure related to the extracted characteristic amount; and a countermeasure presentation unit for presenting the countermeasure in a visualized state.

Abstract: In some examples, a circuit can include a first buffer circuit that can be configured to receive a first clock signal and a first output voltage. The first buffer circuit can be configured to operate in a first voltage domain based on the first output voltage. The circuit can include a second buffer circuit configured to receive a second clock signal, the second buffer circuit being configured to operate in a second voltage domain based on the second output voltage. The first voltage domain can be different from the second voltage domain. In some examples, one of the first and second buffer circuits can be configured to provide one of the first and second clock signals as a clock output signal at a clock output terminal in response to a clock enable signal.

Abstract: An objective of the present invention is to achieve optimal operating guidance on day-to-day operations in a plant while also achieving, for example, soundness and reduced operating costs for a plant equipment piece without increasing the load on the central operation room, by determining the optimal configuration value for the operating value of the plant equipment piece. To this end, there is provided an equipment state monitoring device 331 for analyzing an operating state of a first plant equipment piece 303 during a prescribed period. The equipment state monitoring device 331 analyzes the operating state of the first plant equipment piece 303, and depending on a result of the analysis, carries out determination of an optimal operating value.

Abstract: Methods, systems, and computer-readable storage media for receiving a query that is coded into a computer-executed application that queries a database system, the query including a first portion that defines a number of groups that data is to be divided into, and a second portion that removes redundant values from a group, if any, processing, within the database system, the query to perform a plurality of computations within the database system, and produce a result set including a plurality of data groups, each data group having a minimum value and associated timestamp, and a maximum value and associated timestamp, and transmitting the result set to the application to provide one or more time series visualizations for display in a user interface.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.

Abstract: The disclosure relates to clock-crossing elements that may be used to transfer data between different clock domains. The embodiments include dual clock first-in first-out (FIFO) buffers that may employ toggle-based protocols to manage the transference of information regarding the state of the FIFO buffer. The toggle-based protocols may include a feedback-based handshake and bit-sliced toggle lines to prevent errors due to differences between the clock signals in the different clock domains.

Abstract: Systems and methods to warehouse, handle, and deliver products are disclosed. The system can comprise a vendor-based virtual network that is associated with a supplier-based physical network. The system can enable vendors with institutional, market, or industry knowledge to manage inventory, logistics, and delivery more efficiently. The system can enable vendors to configure a virtual warehouse and delivery network based on the institutional, market, or industry knowledge. The virtual network can be mapped—behind the scenes—to physical warehouses and delivery networks by warehousing providers (“providers”) based at least in part on the virtual network. The provider can then adjust the physical network based on market knowledge, research, physical sales, warehouse and personnel availability, weather, and other factors. The provider can also offer periodic data to the vendor based on physical sales and delivery information to enable both the virtual and physical networks to converge on an efficient solution.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

Abstract: An input/output (I/O) circuit provides a direct current (DC) bias between I/O stages to control duty cycle of the I/O. The I/O circuit can include one or more predriver stages and one or more output stages. The predriver stages can collectively be referred to as a predriver stage, and the output stages can collectively be referred to an output stage. The output stage for a transmitter drives the signal line. The output stage for an input buffer provides a receive signal for processing by the receiver. The I/O circuit includes a control circuit to control the DC bias between the stages to provide trim adjustment of a duty cycle for the output stage.

Abstract: Wireless Electronic Check Deposit Scanning and Cashing Machine (also known and referred to as WEDS) Web-based Online account cash Management computer application System (also known and referred to as OMS virtual/live teller)—collectively invented integrated as “WEDS.OMS” System. Method and Apparatus for Depositing and Cashing Ordinary paper and/or substitute checks and money orders online Wirelessly from home/office computer, laptop, Internet enabled mobile phone, pda (personal digital assistant) and/or any Internet enabled device. WEDS enables verification and transmittal of image, OMS is the navigation tool used to set commands and process requests, integrated with WEDS, working collectively as WEDS.OMS System.

Abstract: A method and an apparatus for executing an application are provided. The application execution method of the present disclosure includes connecting a first external device, receiving, from the first external device, connection information for use in connecting to a second external device, connecting to the second external device using the connection information, and transmitting, when a transfer command is received, application execution state information to the second external device. The application execution method of the present disclosure is capable of allowing the user to execute the application conveniently.

Abstract: Electronic devices that detect their position and/or orientation with respect to earth's frame of reference are described. A coupler can removeably maintain the electronic devices in physical proximity of one another. Each electronic device can have a housing and the coupler can be included on the housing and arranged to physically connect the housing of the electronic device to the housing of at least one other electronic device. Alternatively, the coupler can be a packaging that maintains the electronic devices in physical proximity of one another. Each electronic device can be calibrated using the orientation or position information obtained by other electronic devices maintained by the coupler. Further, each electronic device can include a power source that remains inactive until the device is ready for use.

Abstract: Methods and systems for synchronization of multiple processing cores of an electronic control system are disclosed. The electronic control system is configured to monitor and control operation of a multicore architecture employing one or more processing cores to generate a time reference signal and/or to synchronize with the time reference signal. In some examples, the system employs a single master processor to generate the reference synchronization signal (e.g., a master sync signal). In examples, a rising edge of the partition time reference signal is used as the marker of reference time zero (e.g., the start of a new partition frame). If a core is out of sync with the master sync signal, that core adjusts one or more timing characteristics to align the associated signal with the reference signal.

Abstract: A cloud radio access network (C-RAN) includes a baseband controller communicatively coupled to a plurality of radio points (RP) via a fronthaul network. Each of the plurality of RPs are configured to exchange radio frequency (RF) signals with at least one user equipment (UE). At least one of the RPs is configured to determine a timing difference while synchronizing to the baseband controller; and determine a frequency error, between the RP and a neighboring base station, based on a radio environment monitoring (REM) procedure. A phase error is determined, between the baseband controller and the neighboring base station, phase error is determined based on the timing difference for the RP and baseband controller, and the frequency error for the RP and the neighboring base station.

Abstract: Systems, methods, and apparatus for improving bus latency for trigger activation are described. One method includes using configuration information received from a serial bus and stored in a holding register to reconfigure a peripheral device in accordance with timing indicated by at least one edge in clock pulses transmitted on a clock line of the serial bus. A trigger is activated by detection of a first edge in the clock pulses. Bits of the holding register are transferred to a register that controls elements of the peripheral device when the trigger is actuated. The trigger may be activated as indicated by trigger activation information received in a datagram. The trigger may be activated as indicated by a start condition transmitted on the serial bus. The trigger may be enabled or disabled based on signaling state of a data line of the serial bus when the first edge is detected.

Abstract: The described systems, apparatus and methods enable communication between devices that use a single-wire link and devices that use a multi-wire link. One method performed at a master device includes transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition, transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal, and transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The second datagram may be transmitted in a data signal with embedded timing information.

Abstract: The present disclosure relates to a transmitter and a transmission method and a receiver and a reception method that make it possible to suppress an increase in power consumption. Data in which a clock signal is embedded is transmitted, and a frequency of the clock signal embedded in the data is controlled to reduce the frequency of the clock signal in a predetermined period. Alternatively, data in which a clock signal is embedded and a notification indicating that a frequency of the clock signal is variable are received, and a frequency of the received data is reduced in a predetermined period, on the basis of the received notification. The present disclosure is applicable to, for example, a transmitter, a receiver, a signal processor, a controller, an information transfer system, a transmission method, a reception method, a program, or the like.