Abstract: The present specification provides a method and a device, the method, performed by a device, for transmitting a first pulse train in a quantum communication system being characterized by: receiving a random access (RA) preamble from another device; transmitting an RA response (RAR) to the other device as a response to the RA preamble; performing a radio resource control (RRC) connection process with the other device; receiving data from the other device; and decoding the data on the basis of key information, wherein a first pulse train is generated in a laser diode of the device, and the key information is determined on the basis that the first pulse train passes through both a first path and a second path and is then transmitted from the device to the other device via a quantum channel.

Abstract: This application discloses a clock synchronization method and a related apparatus in a distributed system. The distributed system includes a plurality of nodes, and the plurality of nodes include a master node and a plurality of slave nodes. The master node obtains a plurality of local clock offsets, where each of the plurality of local clock offsets indicates a clock offset between two nodes in the distributed system. The master node determines a global clock offset of a target slave node relative to the master node based on the plurality of local clock offsets, and sends the global clock offset to the target slave node. The target slave node obtains a clock reference value of a local clock, and then performs clock synchronization based on the clock reference value and the global clock offset.

Abstract: The present application relates to the technical field of computers. Disclosed are a starting method and apparatus for an Advanced RISC Machine (ARM) server, an ARM server, and a non-volatile computer-readable storage medium. The method includes: after a Basic Input Output System (BIOS) is started, setting a clock frequency of an Inter-Integrated Circuit (I2C) bus to a preset clock frequency by using the BIOS, where the preset clock frequency is a clock frequency at which a baseboard management controller (BMC) reads real-time clock (RTC) time through the I2C bus; initializing the I2C bus by using the BIOS, and starting and entering an operating system; reading the RTC time through the I2C bus by using the BIOS, and determining whether the BIOS successfully reads the RTC time; and if the BIOS successfully reads the RTC time, displaying, under the operating system, system time corresponding to the RTC time.

Abstract: One example securely updates an integrated circuit to mitigate undesirable modifications and this involves an application circuit accessing an external network while a (e.g., nonvolatile) program memory is write protected; and a reset-boot circuit resetting and booting the application circuit while access to the external network is disabled, and causing an update for the application circuit. In response to an indication that an update is downloaded for installation, the downloaded update is installed in the memory while access to the external network is disabled, and execution of the reset mode is permitted after the update is installed. Also, a retrieval module may download, in response to an indication that an update is not downloaded, an update provided via the external network while the memory is write-protected and thereby permitting execution of the reset mode after the update is downloaded.

Abstract: A method for calibrating a characteristic value of a signal processing device comprised in SerDes inside of an interface circuit of a memory controller includes: monitoring a current of a voltage of a test element to generate a process detection result by a monitor and calibration module; monitoring an environment temperature to generate a temperature monitored result by the monitor and calibration module; selecting a reference value subset from multiple reference value subsets as a preferred reference value subset for a calibration operation based on the process detection result and the temperature monitored result; and performing the calibration operation on the signal processing device by at least one calibration circuit of the monitor and calibration module according to the preferred reference value subset to adjust the characteristic value of the signal processing device.

Abstract: A data storage device and method for reducing read disturbs when reading redundantly-stored data are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The memory is configured to redundantly store a plurality of copies of data, wherein the plurality of copies of the data comprise a primary copy of the data and at least one secondary copy of the data. The controller is configured to randomly select one of the plurality of copies of the data instead of selecting the primary copy of the data as a default; and read, from the memory, the randomly-selected one of the plurality of copies of the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

Abstract: A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.

Abstract: A recording apparatus includes the following. A timekeeper keeps time. A recorder records data. At least one processor is configured to perform, associating the time at a timing that the data is recorded in the recorder to the data as recorded time, the time based on the kept time kept by the timekeeper, obtaining modified time regarding modification of the kept time, and in a situation that it is determined that a predetermined condition to determine whether there is a possibility that the modified time is before the recorded time associated to the latest data is satisfied, associating the time in which the kept time is not modified based on the modified time to the data recorded thereafter as the recorded time.

Abstract: A BMC time management method, system and apparatus, and a computer medium are provided. The BMC time management apparatus includes a BMC, a CPU and a BIOS, wherein the BMC is configured to send time loss information to a CPU after detecting a loss of time of the BMC; the CPU is configured to send, after receiving the time loss information, a notification of executing a time recovery operation to the BIOS; and the BIOS is configured to obtain time information in a CMOS after receiving the notification of executing the time recovery operation, and synchronize the time information to the BMC, so that the BMC recovers the time of the BMC based on the time information.

Abstract: Aspects of the disclosure are directed to supporting time synchronization across a datacenter network with greater accuracy. The time synchronization includes both software based and hardware based time synchronization mechanisms to provide more precise time synchronization across various nodes in the datacenter network. The software based mechanism can provide the initial coarse time synchronization while the hardware based mechanism can provide the subsequent finer time synchronization.

Abstract: According to the present invention, when there is a change in a network configuration, timers of a changed network configuration are synchronized with a timer having high accuracy among the timers. This control system has a network configuration in which one or more control devices each for controlling a target can be communicably connected to a network, and each of the one or more control devices has: a timer for managing time with accuracy; a communicator for transmitting a control command to a target corresponding to said control device on the basis of the time managed by the timer; and a timer synchronizer that, when the network configuration is changed, time-synchronizes, among timers of each control device of a changed network configuration, timers with another timer having higher accuracy than the timers.

Abstract: A method includes generating a new storage target assignment for a placement group (PG) as a last started set, the PG including the last started set and a last clean set, wherein the last started set includes a current set of storage targets assigned for the PG, and the last clean set includes a set of storage targets assigned for the PG at the last time all data stores in its acting set of storage targets were online and up-to-date; performing a process to rebalance or add new data stores in the last started set; storing one or more of the new data stores in a supplemental clean list; and performing one or more update operations on the last started set, based on the supplemental clean list.

Abstract: Techniques are described for reconciling events timestamped in different time domains in multi-node systems supporting low-latency hardware timestamping. First and second nodes having independent time bases are synchronized by the first node generating an event that is received effectively simultaneously at the first and second nodes, the first and second nodes recording a timestamp of receipt of the event, the first node asynchronously querying the second node for its timestamp of receipt of the event and comparing its timestamp of receipt of the event with the timestamp of receipt of the event by the second node, and the first node using a difference in the timestamps of receipt of the event by the first and second nodes to align the time bases of the first and second nodes. The nodes may include hardware timestamping functionality or use an external component (e.g., field programmable gate array) to provide the timestamping functionality.

Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

Abstract: An agent on a terminal send an instruction to firmware on a miscellaneous board of the terminal. The instruction includes a time period during which power to the terminal and peripherals of the terminal are to be powered off. The agent sends an instructions to a core of a motherboard of the terminal to perform shutdown operations in anticipation of the terminals and peripherals being powered off. In response to the instruction received, the firmware monitors the core for a state indicating that the core is shutdown, the firmware sets a timer to the time period, and causes power to be cut between the motherboard and a power supply unit of the terminal. When the timer expires, the firmware re-establishes power between the motherboard and the power supply unit causing the core to initiate the proper sequence of operations to start up the terminal and the peripherals.

Abstract: A slave device for IO-Link communication with a master device, wherein the master device and the slave device operate on a common basic timing, the slave device including at least one Universal Asynchronous Receiver Transmitter (UART) module configured to detect an INIT request sent from the master device during communication setup, calculate an actual timing of the master device from the INIT request and correct an initial timing of the slave device to an actual timing of the slave device based on the actual timing of the master device.

Abstract: A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.

Abstract: The disclosed embodiments provide various compensated charge pumps (CPs) which have a current mismatch compensation circuitry and various CP output-current-mismatch compensation structures based on using a dummy charge pump (CPdum) and feedback loops. In some embodiments, the CPdum is identically biased as the CP to be compensated. CPdum is configured to sense the output voltage and use the feedback loops to generate compensation currents for the CP. The compensation currents simultaneously compensate CP and CPdum. Moreover, CPdum is loaded with high impedance so that the compensation current makes sure CPdum doesn't have current mismatch. Because CP and CPdum have identical biasings and are compensated in the same manner with the same amount of current, CP output current mismatch is hence effectively eliminated.

Abstract: A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

Abstract: An apparatus includes at least one processing device comprising a processor coupled to a memory, with the processing device being configured to maintain a synchronous replication input-output (IO) request list having a plurality of entries corresponding to respective synchronous replication IO requests, a given such entry identifying at least a sender component and one or more associated component resources to be released responsive to a failure of the sender component. The processing device is further configured to detect a failure of a particular one of a plurality of sender components, to access the synchronous replication IO request list to determine one or more associated component resources to be released, to release the one or more associated component resources, and to update the synchronous replication IO request list by marking the one or more associated component resources as released. Other embodiments include methods and computer program products.

Abstract: An electronic device is disclosed. The electronic device comprises a first clock configured to operate at a frequency. First circuitry of the electronic device is configured to synchronize with the first clock. Second circuitry is configured to determine a second clock based on the first clock. The second clock is configured to operate at the frequency of the first clock, and is further configured to operate with a phase shift with respect to the first clock. Third circuitry is configured to synchronize with the second clock.

Abstract: This disclosure is directed to systems and methods for managing a group session for consuming media content across a plurality of devices. In some configurations and by non-limiting example, the group session operates to synchronize playback and control of media content at the plurality of devices. In one aspect a method of simultaneously playing media content on a plurality of media playback devices for a group session is disclosed.

Abstract: A method and system are provided for synchronizing signals, using a synchronizer circuit, between a source circuit and a destination circuit that utilizes detection of when the destination circuit clock is turned off. In the method performed by the synchronizer circuit, a stop signal is received from the destination circuit that is generated upon determination that the destination clock in the destination circuit is turned off. A data signal from the source circuit is, upon receipt of the stop signal, prevented by the synchronizer circuit from being transmitted from the source circuit to the destination circuit. Then once a start signal is received in response to the destination circuit clock signal turning back on, the data signal is once again transmitted from the source circuit to the destination circuit by the synchronizer.

Abstract: A controller includes circuitry configured to: receive global time data indicating a global time associated with an external global clock; synchronize an internal controller clock of the controller with the global clock based on the global time; set a controller time based on the synchronized controller clock; and transmit controller time data indicating the controller time to at least one local device through periodic communication.

Abstract: A method for securing time synchronization in a server Electronic Control Unit (ECU), including: initializing time synchronization of the components; storing a unique clock identification of a grandmaster clock; identifying a shadow controller; transmitting synchronization messages; querying the sending time with the shadow controller; inserting the time in the follow-up message via the controller that forms the grandmaster clock, and retransmitting the time; sending additional messages relating to time synchronization via selected network devices that do not provide the previously determined grandmaster clock. The time information sent in the additional messages relating to time synchronization and the clock parameters relevant for determining the best clock by Best Master Clock Algorithm (BMCA) and the domain number match those of the previously determined grandmaster clock, or are comparable with them.

Abstract: A memory device includes one or more memory cells, and a pipeline coupled to the one or more memory cells. The memory device includes a first pulse generator coupled to the one or more memory cells. The first pulse generator is configured to generate, based on a first delayed clock signal, a memory clock signal to control the one or more memory cells. The first delayed clock signal is delayed with respect to a clock signal. The memory device includes a second pulse generator to generate, based on a second delayed clock signal and the memory clock signal, a pipeline clock signal to provide data from the one or more memory cells through the pipeline. The second delayed clock signal is delayed with respect to the clock signal.

Abstract: A thread executing a task at a node in a multi-socket computing system may access a first data structure to obtain a first calibration dataset for the node. The first thread may generate a timestamp based on the first calibration dataset and a first quantity of time measured by a clock at the first node. The real-time duration of the task may be determined based on the timestamp. The first thread may recalibrate the first clock by at least generating, based on the first quantity of time measured by the clock and a second quantity of time measured by a wall clock of an operating system of the multi-socket computing system, a second calibration dataset. The first thread may update the first data structure to include the second calibration dataset while a second thread accesses a second data structure to obtain calibration data.

Abstract: Devices, systems, and methods for hardware-based time synchronization for heterogenous sensors are described. An example method includes generating a plurality of input trigger pulses having a nominal pulse-per-second (PPS) rate, generating, based on timing information derived from the plurality of input trigger pulses, a plurality of output trigger pulses, and transmitting the plurality of output trigger pulses to a sensor of a plurality of sensors, wherein a frequency of the plurality of output trigger pulses corresponds to a target operating frequency of the sensor, wherein, in a case that a navigation system coupled to the synchronization unit is functioning correctly, the plurality of input trigger pulses is generated based on a nominal PPS signal from the navigation unit, and wherein, in a case that the navigation system is not functioning correctly, the plurality of input trigger pulses is generated based on a simulated clock source of the synchronization unit.

Abstract: A two-chip die module with minimal chip-to-chip clock skew is provided. The two-chip die module includes a common substrate, first and second chips operably disposed on the common substrate to be communicative in parallel with one another and a single phase lock loop (PLL). The PLL is disposed within one of the first and second chips to provide a source for a common clock signal for the first and second chips. PLL signals of the PLL to the first and second chips are nearly equal and clock sample signals of the first and second chips are nearly equal.

Abstract: In an electronic device capable of running multiple software applications concurrently, applications, documents, cards, or other activities can be selected for hibernation so as to free up system resources for other activities that are in active use. A determination is made as to which activities should hibernate, for example based on a determination as to which activities have not been used recently or based on relative resource usage. When an activity is to hibernate, its state is preserved on a storage medium such as a disk, so that the activity can later be revived in the same state and the user can continue with the same task that was being performed before the activity entered hibernation.

Abstract: A computer-assisted method for monitoring a first time base of a first communication device and a second time base of a second communication device. First, Cristian's algorithm is used to calculate time offset intervals between the time bases. Second, the maximally possible drift of the time offset is ascertained multiple times for two measurement steps. A minimally possible drift is ascertained from the upper limit of the time offset interval for the previous measurement step and the lower limit of the time offset interval for the subsequent measurement step. The upper and lower limits of a drift interval are calculated from the maximally and minimally possible drifts. Third, the lowest upper limit is defined as the upper limit of a resulting drift interval, and the highest lower limit is defined as the lower limit of the resulting drift interval with narrow limits for the relative drift.

Abstract: It is provided a synchronization system capable of managing execution of synchronization for clocks to be mounted on various devices. A synchronization system of clocks comprising: a leader device; a follower device capable of establishing communication connection with the leader device; and a server apparatus capable of establishing communication connection with the leader device and/or the follower device, the system further comprising: a time deviation calculator configured to calculate a time deviation between the leader device and the follower device; and a time corrector configured to correct a time in the follower device based on the calculated time deviation, wherein the synchronization system executes the time deviation calculator and/or the time corrector when the server apparatus generates, transmits, and/or receives predetermined information.

Abstract: An information processing device includes a reception I/F unit, a reception-time-point measuring unit, and an event-detection-time-point estimation unit. The event-detection-time-point estimation unit estimates an event detection time point, which is a time point at which an event corresponding to latest detection data is detected, from a minimum system delay time, a minimum-system-delay jitter, and a time period from detection of the event corresponding to a target data to detection of the event corresponding to latest detection data. The minimum-system-delay jitter is the difference between a minimum-reception-time expected reception time point and the reception time point of the target detection data. The minimum-reception-time expected reception time point is calculated to be a time point at which the target data is received before the latest detection data. The target detection data is one piece of detection data, out of the multiple pieces of detection data, sent with a minimum system delay time.

Abstract: Bus interface protocols allow users to transmit data from one IP to another. Allowing definition of multiple per-symbol and per-packet user signals allows users to append information with each segment of data or transmit additional information pertaining to the whole packet of data, respectively. This provides finer granularity and control over the information.

Abstract: A method of performing clock synchronisation across multiple devices, the method including: in a first device: emitting timing pulses based on a first clock signal; and, outputting event data including events associated with first event times based on the first clock signal; in a second device: receiving the timing pulses; and, generating reference data including an indication of each timing pulse associated with a reference time based on a second clock signal; and, in one or more processing devices: receiving the event data; recording an approximate local event time for each event based on a time of local receipt determined using a local clock signal; using the local event times and first event times to derive a first function that relates the first clock signal and the local clock signal; using the first function and the reference data to derive a synchronisation function relating the first and second clock signals; and, using the synchronisation function to perform clock synchronisation of the first and se

Abstract: Disclosed are a device synchronization calibration method and apparatus, a device, and a storage medium. The method includes that timestamp synchronization deviations between all two devices among at least two devices is acquired, that it is determined whether each of the timestamp synchronization deviations between the all two devices is a set value, and that a synchronization calibration instruction is generated in response to a determination result that any timestamp synchronization deviation is not the set value. The synchronization calibration instruction is used for performing synchronization calibration for two devices corresponding to any timestamp synchronization deviation.

Abstract: A distributed system includes a plurality of compute nodes configured to process messages. The compute nodes each process messages corresponding an assigned value of a common parameter of the messages. The values are assigned to the compute nodes such that two or more compute nodes are available to process each message. The values can be assigned to the compute nodes in a grouping configuration or a striping configuration. The compute nodes also circulate one or more tokens among nodes, and perform a self-maintenance operation during a given state of possession of the token. During a self-maintenance operation, the values assigned to the compute node can be reassigned to other compute nodes to ensure processing of corresponding messages.

Abstract: Existing systems enable secure storage of encryption keys in the form of digital wallets, however, since the keys are preconfigured, they can be prone to malicious attacks. The embodiments herein provide a method and system for randomizing distribution of cryptographic keys across multiple secure key storage devices. The system generates random storage identities (RSIDs) for secure key storage devices by selecting a random storage device from a device portfolio, assigns the RSIDs randomly to create crypto addresses based on random access and partition the devices by deriving crypto addresses. Further, the system generates a user hash function and maps the user hash function to find an associated RSID hash function. The system identifies a device ID, a partition ID and a business date from a device mapper associated with the RSIDs to regenerate new RSIDs and recommends the regenerated new RSIDs randomly to each of the plurality of devices.

Abstract: Provided is a time interleaving circuit to mitigate glitches. A first loading stage outputs first data representative of first serialized data. A second loading stage generates second serialized data. The second loading stage receives the first data output by the first loading stage. In response to the first data having a first state, the time interleaving circuit inverts the second serialized data to generate second data representative of the second serialized data. In response to the first data having a second state, the time interleaving circuit outputting the second data without inverting the second serialized data. Exclusive disjunction logic receives the second data and operates on the first data and the second data to generate output data.

Abstract: An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

Abstract: A system, method and apparatus for configuring a node in a sensor network. A sensor service can enable sensor applications to customize the collection and processing of sensor data from a monitoring location. In one embodiment, sensor applications can customize the operation of nodes in the sensor network via a sensor data control system.

Abstract: In accordance with an embodiment, an electronic device includes a secure element configured to implement a plurality of operating systems; and a near field communication module coupled to the secure element by a single bus and by a routing circuit configured to route routing data between the plurality of operating systems and a receive circuit of the near field communication module.

Abstract: A method includes: receiving a data signal (DQ) and a clock signal (DQS); generating an indicator signal by: delaying the data signal (DQ) to generate a delayed data signal (DQ?); sampling the data signal (DQ) and the delayed data signal (DQ?) using an edge of the clock signal (DQS) to generate a first sampled value and a second sampled value; and generating the indicator signal based on the first sampled value and the second sampled value; and adjusting one or more of a DQ adjustable delay line associated with the data signal (DQ) and a DQS adjustable delay line associated with the clock signal (DQS) based on the indicator signal to synchronize the data signal (DQ) and the clock signal (DQS).

Abstract: The present disclosure generally relates to methods for sending event notifications. In some examples, a controller periodically sends messages concerning a status of an event corresponding to the controller. In some examples, at a first time while periodically sending the messages and in accordance with a determination that the status of the event has changed, the controller sends a message concerning data other than the status of the event. In some examples, at the first time while periodically sending the messages and in accordance with a determination that the status of the event has not changed, the controller continues to periodically send the messages without sending the message concerning data other than the status of the event.

Abstract: A method for monitoring an industrial robot. The method includes configuring the robot to perform a certain task during an integration process and storing integration data in the robot identifying the configuration of the robot for performing the task. The method also includes installing the robot in a manufacturing facility, and uploading the stored integration data to the Cloud when the robot is installed in the manufacturing facility. The method further includes capturing production data generated by the robot during operation of the robot in the manufacturing facility, uploading the production data to the Cloud, and comparing the production data to the integration data.

Abstract: There is provided a method of clock recovery and a system thereof. The method comprises: by master clock node or by client clock node, generating a first flow of time-stamped packets bearing indication of high priority of delivery and, in parallel, generating a second flow of time-stamped packets bearing indication of lower priority of delivery. By client clock node, processing the packets from the first flow separately from the packets from the second flow to define, separately for each flow, a function informative of changes of packets' delays in the respective flow over time; using the defined functions informative of changes of packets' delays in the first and the second flows over the same time intervals to assess a cause of the packets' delays changes; and applying a clock recovery algorithm in a manner differentiated in accordance with the assessed cause.

Abstract: A machine learning accelerator (MLA) implemented on a semiconductor die includes a computing mesh of interconnected compute elements that includes storage elements (SEs) and processing elements (PEs). The compute elements execute a program of instructions to implement a machine learning network according to a static schedule for execution of the instructions. A compiler determines allowable time windows for the transfer of instructions and/or data from off-chip memory to the compute elements in order to fulfill the static schedule. If instructions/data are available before the time window opens, they are held until the window opens. If the window is about to close and the transfer of instructions/data is not yet complete, the execution of statically scheduled instructions is suspended to allow the transfer to complete within the window.

Abstract: In an example, a system is adapted to be coupled to a load device having a load clock. The system includes a clock generation device with a pin. The system also includes a capture circuit coupled to the pin and operable to sample a value at the pin. The system includes a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, where the D flip-flop is operable to provide, at the output, a system reference event (SYSREF) signal to align the load clock to the clock, based at least in part on the value at the pin.

Abstract: An air conditioner includes an adapter including a control unit that controls the air conditioner using a learning model and a communication unit that communicates with a server device that generates the learning model on the basis of operation history data of the air conditioner. The adapter includes an acquisition unit, a determination unit, an erasing unit, and a transmission unit. The acquisition unit acquires the data every predetermined cycle from the air conditioner. The determination unit determines whether or not an amount of change between temporally continuous data of the data acquired by the acquisition unit is within a predetermined range. The erasing unit leaves at least one of the continuous data and deletes the other data in a case where the amount of change between the continuous data is within the predetermined range. The transmission unit transmits the data after being deleted to the server device.