Abstract: Methods and apparatus for synchronizing data transfers across clock domains for using heads-up indications. An integrated circuit includes a first-in first-out buffer (FIFO); a memory controller configured to operate in a first clock domain and coupled to the FIFO, the first clock domain associated with a first clock signal; a data fabric configured to operate in a second clock domain and coupled to the FIFO, the second clock domain associated with a second clock signal, a second frequency of the second clock signal being different from a first frequency of the first clock signal; and a controller coupled to the FIFO. In some instances, the controller determines a phase relationship between the first clock signal and the second clock signal; monitors one or more first clock edges of the first clock signal and one or more second clock edges of the second clock signal; and sends a first heads-up signal to the memory controller.

Abstract: A method includes selectably controlling a power supply from a renewable energy source based power system and an energy storage device charged thereby and/or an Alternating Current (AC) power system to a computing system including one or more data processing device(s) using an electronic control system, and continuously updating, through a computing power management system associated with the electronic control system, a parameter of operation of the energy storage device in response to analyzing data pertinent to prior energy usage/production and/or predicted energy usage/production relevant to execution of a high computational workload through the one or more data processing device(s). The method also includes optimizing the power supply from the energy storage device to the one or more data processing device(s) using the computing power management system based on the continuously updated parameter of operation of the energy storage device.

Abstract: An apparatus can include first circuitry coupled to a FIFO memory. The first circuitry can provide a write pointer of the FIFO memory at a first rate. Second circuitry can be coupled to the FIFO memory. The second circuitry can provide a read pointer of the FIFO memory at a second rate that is different from the first rate. Third circuitry can be coupled to the first and second circuitries. The third circuitry can provide an indication of an error condition of the FIFO memory based on the write pointer and the read pointer.

Abstract: An air conditioner includes an adapter including a control unit that controls the air conditioner using a learning model and a communication unit that communicates with a server device that generates the learning model on the basis of operation history data of the air conditioner. The adapter includes an acquisition unit, a determination unit, an erasing unit, and a transmission unit. The acquisition unit acquires the data every predetermined cycle from the air conditioner. The determination unit determines whether or not an amount of change between temporally continuous data of the data acquired by the acquisition unit is within a predetermined range. The erasing unit leaves at least one of the continuous data and deletes the other data in a case where the amount of change between the continuous data is within the predetermined range. The transmission unit transmits the data after being deleted to the server device.

Abstract: A method includes selectably controlling a power supply from a solar Direct Current (DC) power system and an Alternating Current (AC) power system to a computing system including one or more data processing device(s) using an electronic control system, and continuously updating, through a computing power management system associated with the electronic control system, a power consumption requirement of execution of a high computational workload through the one or more data processing device(s) based on analyzing prior energy usage/production and/or predicted energy usage/production relevant to the execution of the high computational workload. The method also includes optimizing the power supply from the solar DC power system to the one or more data processing device(s) using the computing power management system based on the continuously updated power consumption requirement of the execution of the high computational workload.

Abstract: Alignment circuitry including a first clocked latch for receiving a synchronization signal having an enable edge and a target clock signal and outputting an enable signal having an enable edge corresponding to the enable edge of the synchronization signal and synchronized with the target clock signal; a second clocked latch for receiving the enable signal and a delayed target clock signal, being a version of the target clock signal having been delayed by a delay circuit of the clock-controlled circuitry, and outputting a re-timed enable signal having an enable edge corresponding to the enable edge of the enable signal and synchronized with the delayed target clock signal; and gating circuitry for receiving the delayed target clock signal and the re-timed enable signal and to start output of the delayed target clock signal at a timing defined by the enable edge of the re-timed enable signal for controlling the clock-controlled circuitry.

Abstract: A communication apparatus is provided and receives a communication packet, acquires a timestamp of a reception of the communication packet, analyzes a type of the received communication packet, transfers the received communication packet to a predetermined memory based on information indicating an analyzed type of the communication packet, and associates the analyzed type of the communication packet with the acquired timestamp.

Abstract: A method for reception of a signal by a subscriber of a real-time network. The signal includes a signal clock having a signal clock frequency and the subscriber includes a counter, which has a counter clock with a counter clock frequency and which maps a local time of the subscriber. The method includes sampling the signal with a reception clock of a reception counter of the subscriber, the reception clock being derived from the counter clock, whereby the reception counter maps the local time of the subscriber, adapting a phase position of the reception clock to a phase position of the signal clock when said reception clock is derived from the counter clock, and sampling the signal at a reception clock frequency of the reception counter.

Abstract: A switch is described. The switch includes a plurality of ports, a plurality of port logic modules, a memory, and a switch fabric. Transactions ingress and egress the switch via the ports. The port logic modules are coupled with the ports. Each port logic module has core clock domain logic for a core clock domain specific to a corresponding port. The memory includes banks. The memory and the switch fabric have a system clock domain. The core clock domain for each of the port logic modules is different from the system clock domain.

Abstract: A memory device includes a first rank having first memory banks and a first quad skew adjustment circuit and a second rank having second memory banks and a second quad skew adjustment circuit, wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is configured to: receive a 4-phase clock through first channels; detect internal quad skew of the 4-phase clock; correct skew of the 4-phase clock according to the detected quad skew; and output mode register information corresponding to the detected quad skew through a second channel.

Abstract: According to an embodiment, a track includes first sectors and a second sector. When write of a second data segment to a third sector that is one of the first sectors is requested from a host, a controller acquires the second data segment from the host and stores the second data segment in the memory, and reads a data set including all first data segments and all first information pieces from the track and stores the data set in the memory. The controller acquires a second information piece of the third sector, and updates a first data segment and a first information piece read from the third sector in the data set in the memory with the second data segment and the second information piece. The controller calculates a second parity while the updated data set to the track, and writes the second parity to the second sector.

Abstract: A method performed by a first electronic device. The method generates, at the first electronic device that is sharing a global clock with a second electronic device, a first timebase information that includes a first timebase that defines a relationship between the shared clock and an internal clock of the first electronic device, the first timebase information for synchronizing playback of a first piece of media content associated with a first application between the first and second electronic devices. The method receives, from a second application, a second timebase information that includes a second timebase that defines a relationship between the first timebase and a second piece of media content, generates a third timebase information that includes the first timebase and the second timebase, and transmits the third timebase information to the second electronic device.

Abstract: Disclosed herein are system, method, and computer program product embodiments for synchronizing playback of an audio and/or video content. An embodiment operates by collectively selecting, by a first device in concert with a second device of a plurality of devices in a computer network session, and in accordance with a predetermined synchronization list comprising a first and second synchronization mechanism, the first synchronization mechanism over the second synchronization mechanism such that the first synchronization mechanism is more precise than the second synchronization mechanism. The first and second synchronization mechanisms are configured to provide a synchronized playback of the at least one of the audio content and the video content.

Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide a dynamic data interconnect and networking cable configuration. The dynamic data interconnect includes a substrate, transmitters supported on the substrate configured to generate signals, and receivers supported on the substrate configured to receive signals. The dynamic data interconnect further includes a number of connection pads that receive data cables attached thereto and a number of transmission lanes that operably couple the transmitters and receivers to the connection pads. The dynamic data interconnect further includes transmission circuitry in communication with each of the transmitters and receivers such that, in an operational configuration, the transmission circuitry determines a transmission state of the dynamic data interconnect and selectively disables operation of at least a portion of the transmitters or at least a portion of the receivers.

Abstract: A system, a method, and a machine-readable medium for overclocking a computer system is provided. An example of a method for overclocking a computer system includes predicting a stable operating frequency for a central processing unit (CPU) in a target system based, at least in part, on a model generated from data collected for a test system. An operating frequency for the CPU is adjusted to the stable operating frequency. A benchmark test is run to confirm that the CPU is operating within limits.

Abstract: A clocking circuit is provided using a master delay-locked loop (DLL) and a slave DLL. A master DLL code indicates a delay adjustment made at a master DLL. A delay of a slave DLL is adjusted based on the master DLL code. A replica phase detector at the slave DLL is temporarily enabled during an interface idle period. A slave DLL code is determined, and a configuration value is determined based on the slave DLL code to the master DLL code. The replica phase detector is then disabled.

Abstract: The system and method generates a pulse or a signal that is transmitted between a central processing unit or processor and an Ethernet integrated circuit card to program a trigger generator in the IC. The pulse is effectively a 1PPS signal that is provided to the IC, which may be in the form a field programmable gate array to enable timing synchronization. The trigger in the IC may also generates an interrupt to the processor so a driver in the CPU is instructed to set the next trigger. For the trigger to be accurately controlled, the control routine is implemented in the driver existing in kernel space rather than user space. A routine or protocol periodically polls the interrupt to determine when the trigger must be reset.

Abstract: A clocking architecture for a memory module is configurable to independently select either rising or falling edges of an input clock as respective references for generation of an internal clock and an output clock. The clocking architecture supports reference edge selection in both a single data rate (SDR) mode and a double data rate (DDR) mode while maintaining a fixed phase relationship between the input clock and the output clock regardless of the reference edge selection.

Abstract: A method and system of providing users with a tool to interact with content from a primary app through a secondary app are disclosed. The secondary app obtains source data from the primary app and determines whether the data includes labels that can trigger the application of a particular configuration in the presentation of the content. Changes made to the source data in the secondary app that relate to substantive or key data for the content do not affect the source data in the primary app. However, changes made in the secondary app that relate to non-substantive data can be propagated back to the primary app.

Abstract: Aspects present herein relate to methods and devices for wireless communication including an apparatus, e.g., a UE. The apparatus may measure a frequency error from a first pair of pilot symbols and a second pair of pilot symbols received via a channel associated with communication between the UE and a base station, the measured frequency error from the first pair of pilot symbols and the second pair of pilot symbols corresponding to a first frequency error measurement and a second frequency error measurement. The apparatus may detect a first frequency wraparound in the first frequency error measurement and a second frequency wraparound in the second frequency error measurement. The apparatus may adjust the first frequency error measurement based on the first frequency wraparound or the second frequency error measurement based on the second frequency wraparound if the first frequency wraparound or the second frequency wraparound is the non-zero value.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: An asynchronous pipeline includes a first stage and one or more second stages. A controller provides control signals to the first stage to indicate a modification to an operating speed of the first stage. The modification is determined based on a comparison of a completion status of the first stage to one or more completion statuses of the one or more second stages. In some cases, the controller provides control signals indicating modifications to an operating voltage applied to the first stage and a drive strength of a buffer in the first stage. Modules can be used to determine the completion statuses of the first stage and the one or more second stages based on the monitored output signals generated by the stages, output signals from replica critical paths associated with the stages, or a lookup table that indicates estimated completion times.

Abstract: An air conditioning system includes an air conditioner and an adapter that connects the air conditioner and an external server device. The adapter includes a first updating unit and a second updating unit. The first updating unit updates, when a new learning model that provides a recommended operation to a control unit included in the air conditioner is received from the external server device, the learning model by using a first update method. The second updating unit updates, when an update purpose control program that updates a control program for the air conditioner is received from the external server device, the update purpose control program by using a second update method that is different from the first update method. It is possible to reduce an adapter load by updating the learning model and the control program by using different methods.

Abstract: A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.

Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.

Abstract: Testing clock division circuitry includes generating pseudo random test pattern bits for scan chain logic in programmable clock division logic circuitry and divided clock counter circuitry. A shift clock is used to shift the test pattern bits into the scan chain logic. A capture clock signal is used in the programmable clock division logic during a non-test mode of operation. The shift clock is used to provide output shift bits from the scan chain logic to a multi-input shift register (MISR). Once all the output shift bits for the test pattern bits are provided to the MISR, a final test signature from the MISR is compared to an expected test signature to determine whether the programmable clock division logic circuitry and divided clock counter circuitry are free of faults.

Abstract: The present disclosure discloses a memory access interface device. A data processing circuit receives a data signal including 2M pieces of data from a memory device. A sampling clock generation circuit receives a data strobe signal from the memory device to generate a valid data strobe signal having P valid strobe pulses and further generate a sampling clock signal accordingly, in which P is larger than M. A sampling circuit samples the data signal according to the sampling clock signal to generate sampling results. A control circuit determines valid sampling results according to a time difference between the valid data strobe signal and the data signal and outputs valid data generated according to the valid sampling results as a read data signal to a memory access controller.

Abstract: Various implementations described herein are directed to a device with a reset tree having leaf buffers that provide sensed output signals based on a reset-synchronizing input signal. The device may have a first sensor that receives the sensed output signals from the leaf buffers of the reset tree and provides an attack detection signal based on sensing a malicious attack. The device may have a second sensor that receives the reset-synchronizing input signal, receives the attack detection signal from the first sensor and provides a reset alarm signal based on duration of a timing glitch associated with comparing a difference between the reset-synchronizing input signal and the attack detection signal.

Abstract: Disclosed is a method of determining time in a digital processing system, comprising, in a present cycle of a first digital clock: accessing a reference time counter for a reference digital clock, wherein the reference time counter increments in value by a fixed amount at every cycle of the reference digital clock, the reference digital clock being of a higher accuracy than the first digital clock; accessing a first time counter for the first digital clock, wherein the first time counter increments in value by an updatable increment amount at each cycle of the first digital clock; and comparing at least one part of the reference time counter with at least one corresponding part of the first time counter. Based on the comparing, an adjustment is made to one or more attributes of the first time counter, so that first time counter at least approximates the reference time counter.

Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

Abstract: Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.

Abstract: An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases that are synchronized by generating a common clock signal from a clock generator of the first SoC and simultaneously applying the common clock signal to a first counter of the first SoC and a second counter of the second SoC whereby the first counter and the second counter count clock edges of the common clock. The clock counts are shared through an interface between the first SoC and the second SoC and compared to each other. When the clock counts are different, a clock count of the first counter or the second counter is adjusted to cause the clock counts to match each other. The adjusted clock count is synchronized to the respective clocks of the first and second SoCs, thus synchronizing the first and second SoCs to each other.

Abstract: The present invention discloses a debugging unit and a processor. The debugging unit includes; a register, adapted to sample input data under control of a clock signal; and a dock control unit, adapted to generate a control signal based on a clock enable signal to control the clock signal, so that the register is controlled to sample the input data in a validity period of the clock signal when the control signal is valid. The present invention also discloses a corresponding system-on-chip and an intelligent device including the system-on-chip.

Abstract: A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.

Abstract: A monitoring system monitors processing of incoming messages and logs data related to performance of an application that processes the messages. The monitoring system temporarily associates reusable identifiers with the messages and logs data upon each message traversing different points in the application. Each of the identifiers is sized such that the storage space necessary to store the identifier is less than the storage space necessary to store an identifier sized to uniquely identify all of the plurality of messages, and the identifiers and the logged data are configured to minimize a performance penalty of monitoring the application. The monitoring system parses the data, e.g., during post-processing, to determine, from a plurality of data entries that refers to the same identifier, a subset of the data entries where the same identifier was associated with the same message.

Abstract: Providing clock times to virtual devices. In one embodiment, a method includes identifying a real-time clock device of a host computing device. The host computing device comprises a hypervisor and a virtual machine. The method also includes determining that a virtual device used by the virtual machine will use clock times obtained from the real-time clock device. The method further includes obtaining, by a processing device of the host computing device, a current clock time from the real-time clock device of the host computing device. The method further includes providing the current clock time to the virtual device.

Abstract: The present invention comprises a novel system and method to detect and estimate the time-frequency span of wireless signals present in a wideband RF spectrum. In preferred embodiments, the Faster RCNN deep learning architecture is used to detect the presence of wireless transmitters from the spectrogram images plotted by searching for rectangular shapes of any size, then localize the time and frequency information from the output of the FRCNN deep learning architecture.

Abstract: Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.

Abstract: A computing device may perform a method that includes determining whether internal time reference data is available while booting the computing device. When the internal time reference data is unavailable, the device clock is set to a default time setting. However, when the internal time reference data is available while booting the computing device, the method includes searching the internal time reference data for a most recent time reference, and setting the device clock to a current time setting based on the most recent time reference.

Abstract: In some examples, an electronic device records, in an entry of a time-state data structure that includes a plurality of entries to store respective times, a time in response to invocation of a time-lapse process that lasts a predefined time duration independently of a time clock of the electronic device. The electronic device determines whether times in successive entries of the plurality of entries of the time-state data structure are within a threshold of one another, the threshold based on the predefined time duration. Based on the determining, the electronic device sets a parameter representing a quality of the time clock.

Abstract: Embodiments herein describe techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as “cards”) by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds.

Abstract: In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.

Abstract: A method can include: receiving, in a memory device, a read request from a host device that is coupled to the memory device by an interface; decoding an address of the read request that is received from the interface; decoding a command of the read request to determine whether the read request is for an aligned address operation; maintaining the decoded address without modification when the read request is determined as being for the aligned address operation regardless of an actual alignment of the decoded address; and executing the read request as the aligned address operation on the memory device by using the decoded address.

Abstract: A hub may receive event data captured by a body-worn device and store the event data in a memory of the hub. The event data is then backed up from the hub to a memory of an additional hub communicatively connected to the hub. A copy of event data for a predetermined period of time as included in the event data is then transferred from the memory of the hub to a data store of a network operations center (NOC). In response to the transfer being complete, the hub may delete the event data for the predetermined period of time, send a first command to the additional hub directing the additional hub to delete a backup of the event data for the predetermined period of time, or send a second command to the body-worn device directing the body-worn device to delete the event data for the predetermined period of time.

Abstract: The disclosure relates to detecting phase slips that may occur in a multi-lane serial datalink. Phase slips may occur when a lane experiences lane skew, which may introduce a phase slip with respect to another lane. To detect phase slippage, the system may select a reference lane from among the lanes. The system may generate a pre-deskew delta value based on a difference between the FIFO filling level of the reference lane before a deskew and the FIFO filling level of a second lane before the deskew. The system may generate a post-deskew delta value based on a difference between the FIFO filling level of the reference lane after the deskew and the FIFO filling level of the second lane after the deskew. The system may use a difference between the post-deskew delta and the pre-deskew delta to detect phase slip on the second lane relative to the reference lane.

Abstract: Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.

Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.

Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.

Abstract: A delay lock loop circuit includes a receiver, a delay line circuit, a clock signal generator and a phase detecting circuit. The receiver receives a clock signal and a reference voltage and generates a reference clock signal according to the clock signal and the reference voltage. The delay line circuit is coupled to the receiver and generates a delayed clock signal by delaying the reference clock signal with a delay indication signal. The clock signal generator generates an output clock signal according to the delayed clock signal. The phase detecting circuit generates a detection result by sampling the reference clock signal with a feedback clock signal generated by the output clock signal, and generates the delay indication signal according to a digital value of the detection result.

Abstract: System and method for secure time synchronization in an industrial facility, wherein a synchronization request of a facility component is transmitted to a registration service of a certificate management of the facility and the synchronization request is examined by the registration service, where the synchronization request includes a signature of the requesting facility component, and where depending on an outcome of the examination, a synchronization response is then transmitted to the requesting facility component a system time of the facility component is matched to a system time of the registration service based on the synchronization response.