Abstract: A method and apparatus are provided for interfacing with a synchronous dynamic memory in which memory commands are provided to the memory. The memory is accessed in response to the memory commands. Read data is captured in a data capture circuit having a delay setting. The delay setting is updated in response to detection of a period of read inactivity of the memory.

Abstract: One aspect of the present invention concerns a method for controlling the frequency of oscillation of a local clock signal comprising the steps of (A) generating the clock signal in response to a first control signal, (B) generating the first control signal in response to one of a plurality of adjustment signals selected in response to a second control signal and (C) generating the second control signal in response to a comparison between a local timestamp and an external timestamp.

Abstract: A method for transferring data across different clock domains is provided. The method initiates with detecting a transition of a first clock cycle. The method includes propagating a value associated with the transition of the first clock cycle according to a second clock cycle. The propagation of the value causes a delay of a signal configured to trigger transfer of the data to a logic region operating at the second clock cycle. An interfacing circuit and a programmable logic device are also provided.

Abstract: A multi-link receiving mechanism (MRM) is disclosed comprising a plurality of receivers. Each receiver receives a separate data stream, and all receivers receive the same clock signal. The data streams may arrive at the MRM out of alignment relative to each other (i.e. may have inter-pair skew), and the clock signal need not be aligned with any of the data streams. In response to the clock signal and the data stream, each receiver delays the clock signal by a variable delay to derive a reference signal. This is done to achieve a desired relative alignment between the data stream and the reference signal. Once the reference signal is derived, it is used by the receiver to generate a plurality of latching control signals. These latching control signals are thereafter used by the receiver to latch all of the data units of the data stream. Data from the data stream is thus recovered. Each of the receivers operates in the manner described to recover data from each of the data streams.

Abstract: A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the memory. The adaptive timing system captures data in a data valid window (DVW) in a data signal. In one embodiment, the adaptive timing system comprises a delay circuit for sampling the data signal at a midpoint of the DVW. The adaptive timing system may also comprise an identifying circuit for identifying whether the midpoint of the DVW corresponds to an actual midpoint of the DVW and adjusting the delay circuit accordingly.

Abstract: A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation chip, a CPU evaluation chip and a device, which are used for emulating functions of the logic circuit, the CPU and the flip-flop respectively. When the multi-chip emulation apparatus is used for emulating functions of the single-chip microcomputer in the development, the device for emulating functions of the flip-flop synchronizes the interrupt-request signal to absorb a delay time incurred by the interrupt-request signal due to a physical distance between the peripheral evaluation chip and the CPU evaluation chip so that an interrupt-handling timing in the emulation matches an interrupt-handling timing in the real operation of the single-chip microcomputer.

Abstract: A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to the input clock and control information, to generate the deskewed output clock; and a controller, responsive to the input clock, to generate the control information for controlling the frequency of the deskewed output clock. The programmable clock deskewer may be used to implement a clock tree with various clock outputs for a system on chip integrated circuit.

Abstract: The present invention provides a method and apparatus for updating serial devices. The apparatus includes a plurality of serial registers. The apparatus further includes a device adapted to provide a signal and a plurality of parallel registers, wherein each of the parallel registers is adapted to access at least one of the plurality of serial registers at substantially the same time in response to detecting the signal.

Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.

Abstract: The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.

Abstract: A circuit and a method for aligning transmitted data by adjusting transmission timing for a plurality of lanes. The method includes utilizing different initial values to reset a count value corresponding to a lane when a plurality of COM symbols are detected on the lane, utilizing an increment value to increase the count value corresponding to the lane when a COM symbol is not detected on the lane, and utilizing a plurality of count values corresponding to the lanes to align transmitted data of the lanes when a COM symbol is not detected on the lanes within a predetermined period of time.

Abstract: In some embodiments an apparatus and method may comprise a plurality of lanes between two clock domains, each lane comprising circuitry to generate a first signal when the lane may lose cycle coherency with other of the plurality of lanes, generate a second signal to signify a lane has been delayed, and a control circuit coupled with the plurality of lanes to add latency only to lanes that did not generate a second signal if the control circuit detects a first signal from any of the plurality of lanes.

Abstract: Disclosed herein are methods and circuits to generate a clock signal.

Abstract: A method for synchronizing performances of geographically disparate performers is provided. The method includes setting one or more beat clocks, each beat clock corresponding to a remotes site configured to convey streaming audio over a data communications network to a remotely-located master site. Each beat clock, according to the method, is time-shifted based upon delay and throughput latencies relative to a current-beat time set at the master site. The method further includes receiving at the master site audio renderings of performances by the one or more performers located each remote site. Additionally, when combined with various types of digital media devices, the techniques, mechanisms, and procedure of the invention can create a virtual online media environment.

Abstract: A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level of memory. In response, the variable clock control information generator produces graphics engine clock control information and memory clock control information with respect to each other, such that a relative difference between the graphics engine activity data and the memory activity data is within balance threshold data. Accordingly, the variable clock control information generator adapts to the varying levels of graphics engine activity and memory activity and adjusts the frequency of the graphics engine clock signal and the frequency of the memory clock signal to achieve a balanced relative activity level.

Abstract: An input circuit (1?) provided with a time delay element (40), which circuit is capable of being tested by a controlled high level or low level connection, and a method for the operation thereof. The delay time of the time-delay element can be modified during operation of the input circuit. In particular, the elapsed delay time is read out prior to the testing of the input circuit and is restored again after testing, so that the test does not increase the effective input delay time for the process signals. In addition or as an alternative, the delay time is set to a minimum value prior to the test to enable rapid testing of the input circuit independent of the set delay time.

Abstract: A domain crossing device for use in a semiconductor memory device, including: a unit for comparing a phase of an internal clock signal with a phase of a delay locked loop (DLL) clock signal to generate a first clock selection signal and a phase detection period signal in response to a detection starting signal and a second clock selection signal; a unit for generating a plurality of initial latency signals in response to the phase detection period signal, the detection starting signal and a column address strobe (CAS) latency signal; a unit for receiving the plurality of initial latency signals and the detection starting signal to generate a plurality of latency signals, a clock selection signal and the second clock selection signal; and a unit for generating the detection starting signal based on a self refresh signal, a power-up signal and a DLL disable signal.

Abstract: A method for automatically setting DQS (Distributed Queuing System) and DQ (Data Queuing) receiver reference voltages, the method including: using a delay string to measure a number of delay elements that match a DQS high time and a number of delay elements that match a DQS low time; wherein when the number of delay elements for the DQS low time is larger than the number of delay elements for the DQS high time, the reference voltage is decremented until the number of delay elements are equal; and wherein when the number of delay elements for the DQS low time is smaller than the number of delay elements for the DQS high time, the reference voltage is incremented until the number of delay elements are equal.

Abstract: The invention relates to a method for controlling the reading-in of a data signal at an input of an electrical circuit to an input latch with the aid of a clock signal, with the data item, which is indicated by the data signal, being transferred to the input latch with a clock edge of the clock signal, with the clock edge of the clock signal being shifted in time as a function of a time delay between a signal edge of the input signal at the input and the clock edge, such that the time delay between the signal edge of the data signal and the clock edge is within a predetermined time window.

Abstract: A data transmitting end utilizes a clock signal to transmit at least a data signal to a data receiving end. An adjustable delay compensation circuit for compensating data transmission delay between the data transmitting end and the data receiving end includes an adjustable delay circuit, a clock gating circuit, and at least a target signal generating circuit. The adjustable delay circuit is used for delaying the clock signal by a programmable delay amount to generate a target delay signal. The clock gating circuit is used for allowing the clock signal to reach the adjustable delay circuit when receiving a data transmission enabling signal. The target signal generating circuit is used for receiving the data signal and for sampling the data signal according to the target delay signal.

Abstract: A method of verifying a circuit implementing a data transfer protocol is disclosed. According to one embodiment of the invention, the method comprises steps of providing a block under test that implements a variable latency data transfer protocol; coupling a verification circuit to the block under test; enabling variable latency data transfers to the block under test; and verifying that the block under test is implementing the variable latency data transfer protocol. The method could be implemented to verify the operation of a memory controller of an FPGA, for example. According to another embodiment, a method enabling a multi-stage verification is disclosed. Finally, specific implementations of a verification circuit coupled to an on-chip memory controller of an FPGA are disclosed.

Abstract: The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting the first clock signal using a variable delay device in response to the alignment offset signal to substantially align the edge of the first clock signal to the center of the data packet. Other embodiments are claimed and described.

Abstract: A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to be a second level and to output the clock as a composite clock for clock switching, for a specified period including one of a leading edge and a trailing edge of the clock as well as additional time before and after the edge, when the signal becomes active while the clock is at a first level; a switching demand signal generation circuit that receives the clock and the signal, and outputs a clock switching demand signal; a clock selection signal generation circuit that changes a level of a first clock selection signal when the signal becomes active; and a first selector that selects one of the clock and the clock, according to the level of the signal, and outputs the selected clock.

Abstract: An aspect of the invention is physical layer interface for a network interface including a plurality of input/output pins. The input/output pins are coupled for being multiplexed into a physical layer interface selected from among a Reduced Gigabit Media Independent Interface and a Gigabit Media Independent Interface. The input/output pins internal to a programmable logic device are for access to and from a processor block located in the programmable logic device.

Abstract: A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

Abstract: A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal synchronization/delay circuit. The reset signal synchronization/delay circuit and the first and second counting and delay circuit are triggered by a basic clock signal or a first clock signal derived therefrom to be identical in frequency and phase, and contain counting means whose initial and final counting state are adjustable in order to set, in a clocked fashion, the temporal positions of a first and second load signal that are output by the first counting and delay circuit as well as of a FIFO read clock signal that is output by the second counting and delay circuit and thus adapt them to the temporal requirements of a semiconductor memory system containing the synchronous signal generator.

Abstract: A method for synchronizing a data signal to a clock signal in a source-synchronous system, the source-synchronous system having first and second systems linked by an interface, the first system providing the clock signal to the second system, the second system providing the data signal and a return clock signal synchronous to the data signal to the first system, the method comprising: determining a first time delay between the clock signal and the return clock signal and delaying the data signal by the first time delay; after a predetermined period, determining a second time delay between the clock signal and the return clock signal; determining a difference between the first and second time delays; and, further delaying the data signal by at least a portion of the difference to thereby compensate for a temperature change of the source-synchronous system.

Abstract: A method of controlling an access time for accessing a flash memory comprises comparing a target address of the flash memory with an address of the flash memory that was previously accessed; setting the access time for the flash memory to be a first access time if the target address does not correspond to the same page of the flash memory as the previous address; and setting the access time for the flash memory to be a second access time if the target address corresponds to the same page of the flash memory as the previous address, the first access time being greater than the second access time.

Abstract: A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.

Abstract: In an embodiment of the invention, a method for a phase adjusted delay loop, includes: determining a requested delay value for a code path; and executing a delay loop in the code path in order to obtain a loop delay value that is in phase with the requested delay value. The act of executing the delay loop may include: executing at least one No-operation instruction (NOP) to adjust the loop delay value and to adjust the phase of the loop delay value.

Abstract: The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.

Abstract: An electronic circuit is provided that comprises a plurality of storage elements (101-105) arranged for storing of data elements, and a plurality of processing elements. The plurality of processing elements processes the data elements stored in the storage elements. In operation, the points in time at which respective storage elements load their data elements are mutually different in order to meet a maximum allowable value of the power consumption peaks.

Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.

Abstract: A method of optimizing communication over a high-speed serial bus by minimizing the delay between packets transmitted over the bus is disclosed. The method comprises: calculating the round trip delay between PHYs connected on the bus by pinging; a bus manager sending a configuration packet to all PHYs connected on the bus, the configuration packet containing a minimum gap_count parameter value; and all PHYs connected on the bus sending packets over the bus using the minimum gap_count parameter value as a delay between packets.

Abstract: A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit coupled to a phase comparator in order to generate a delayed clock signal transmitted to the remote member. One input of the main variable delay line receives the reference clock signal.

Abstract: Presented herein is a scheme for reducing the likelihood of erroneous DQS signals. Logic is incorporated proximate to a memory controller and receives a signal indicating a read request and a DQS signal from a memory module. The logic transmits a signal indicating the presence of data, based on the timing relationship between the DQS signals and signal indicating read requests.

Abstract: A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

Abstract: A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, and n delay cells DCELLx (0<x?n). The delay cells DCELL1˜DCELLn are connected in series to each other. Each of the delay cells DCELLx is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an output terminal ty (0<y?n) of a delay cell DCELLy among the delay cells DCELL1˜DCELLn used as output terminal of the delay line.

Abstract: A semiconductor integrated circuit device comprises an internal bus, a plurality of internal modules connected to the internal bus and including a main module performing a predetermined function, and a clock generating unit generating a reference clock and a clock sync signal which indicates positions of valid clock edges in the reference clock, the clock generating unit supplying the reference clock and the clock sync signal to the internal modules. At least one of the internal modules is provided with a sync control module which generates an internal clock based on the reference clock and the clock sync signal.

Abstract: A synchronous input to output protocol translator supporting multiple reference oscillator frequencies and fixed latency data computation and chip crossing circuits enables implementation of a method for delaying osc2 relative to osc1 in a configurable way to provide a constant, minimal Tptcc over a range of refosc frequencies between circuits for data transferred. It requires that the data transferred from a register R1 be sent over multiple wires via configurable delay circuitry for osc2, capture circuitry at the input to R2, and a circuit to transfer a synchronizing signal from a non-delayed clock domain to a delayed clock domain. Relative to osc1, osc2 is a delayed, synchronous clock.

Abstract: A description of deskewing data from the clock from a DRAM, such as, but not limited to a DDR3 DRAM is discussed. For example, the differential signals of a strobe and a clock signal are used to create a first and second loops that can be fed back to a memory controller. The two loops are then compared and a delay is added to the strobe until it matches the delay time of the clock.

Abstract: Methods and apparatuses for emulating a circuit design that includes an in-circuit memory. Sets of reconfigurable logic resources are configured to emulate a logic element of a circuit, where the circuit may include a plurality of logic elements. A memory resource is configured to emulate a portion of the in-circuit memory. Reconfigurable interconnect resources are configured to interconnect the sets of configurable logic resources to the memory resource by way of a memory access arbiter. The memory access arbiter is configured to arbitrate and serialize accesses for the memory resource by the sets of reconfigurable logic resources in an emulation cycle, in accordance with associated priority levels. The priority level of the set of reconfigurable logic resources may be dependent on timing requirements of the set of reconfigurable logic resources and on timing characteristics of the associated logic element of the circuit.

Abstract: In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first output clock signal based on the received divided input clock signal and the received non-divided input clock signal, the first output signal being associated with a first delay. The method further includes, at a delay line, receiving the non-divided input signal, delaying the non-divided input signal for a time substantially equivalent to the first delay, and generating a second output clock signal associated with a second delay substantially equal to the first delay.

Abstract: A method for overload detection according to one embodiment of the invention includes a control process and a data process. In response to a timing signal, the control process sets a state of a timing indicator. Upon execution of a time-constrained operation, the data process checks the state of the timing indicator. In other embodiments, subsequent to an overload detection, an auxiliary data process is configured to execute in a mode that consumes fewer processing cycles.

Abstract: A data storage system for transferring data between a host computer/server and a bank of disk drives through a system interface. The system interface includes a plurality of directors. One portion of the directors is coupled to the host computer/server and another portion of the directors is coupled to the bank of disk drives. The directors control a flow of data between the host computer/server and the bank of disk drives. Each one of the directors has a time element. A time manager provides accurate time information to the time elements. The time elements determine, from the time information fed thereto, and measured time delays, global machine time information for the one of the directors having such time element. The time system is self calibrating.

Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.

Abstract: A system for clockless synchronous data recovery is provided. The system includes an input rate demultiplexer receiving a serial data stream of bits of data transmitted at a bit rate and generating two or more parallel data streams from the serial data stream. One or more delays coupled to the input rate demultiplexer each receives one of the generated parallel serial data streams and delays bits of data and feeds them back to the input rate demultiplexer.

Abstract: Methods, systems, and media are disclosed for improved granularity of a response-request communication on a networked computer system. One example embodiment includes receiving the request-response communication by the networked computer system, and associating the request-response communication with a port, having a nodelay setting, from a set of ports on the networked computer system. Further, the example embodiment includes enabling, based upon the associating, the nodelay setting upon connection of the request-response communication with the port. Further still, the example embodiment includes sending, in accordance with the enabling, the request-response communication to a destination in communication with the networked computer system.

Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.

Abstract: A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the process of phase alignment to allow great flexibility in allowable combinations of slower clock and faster clock frequencies. In one embodiment, an encoded edge select word is generated once at system initialization and used thereafter to select edges of the faster clock on which to sample data that comes from the clock domain of the slower clock. The value of the encoded edge select word is based, in part, on the fixed relationship between the faster clock and the slower clock.