Abstract: Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data signals. The transceiver circuitry supports a phase-locked-loop source synchronous mode that can be used to receive data from transmitting integrated circuits that are clocked with a common clock. Each transmitting integrated circuit transmits a clock and associated data signals over a bus. The transceiver circuitry uses a master-slave architecture. A master dynamic phase alignment circuit in each transceiver receives the clock for that bus and selects a corresponding optimal clock phase to use in receiving input data for the bus from a multiphase clock. The master dynamic phase alignment circuit in each transceiver distributes the optimal clock phase to associated slave dynamic phase alignment circuits. Only a single phase-locked loop circuit is need to generate the multiphase clock.

Abstract: A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.

Abstract: Retiming circuitry for retiming a data signal transmitted from a first environment under control of a first clock signal to a second environment under control of a second clock signal, said first and second clock signals having a known repeat relationship, the retiming circuitry comprising a plurality of delay elements for delaying said data signal; a plurality of inputs connected to said delay elements for receiving said data signal at respectfully different delays; selection means for selecting the data signal at one of said inputs based on said known repeat relationship; and an output for outputting said selected data signal.

Abstract: The present invention relates to a method for controlling a sleep mode of a device in a wireless communications network or in a mobile point-to-point connection in order to turn off system components of the device, especially to turn off a medium access control (2) comprising the steps of: receiving a sleep mode information from an application module in a medium access control (2), coupled to an extended physical layer (PHY), especially to a base band (3), transferring the sleep mode information from the medium access control (2) to the base band (3), setting a sleep signal (sleep) of a power management mode (PMMode) to set one of the system components into sleep state, and, additionally, starting a predetermined first delay timer (T1) to delay the setting of the sleep state for one of the system components.

Abstract: A method and system for synchronizing signals. First and second signals are sent (compressed or uncompressed) from a source to a receiving apparatus of a receiving system. The first signal has content of a first modality (e.g., audio) and the second signal has content of a second modality (e.g., video). The first and second signals are to be displayed on a display apparatus of the receiving system. The first and second signals have been time-synchronized at the source. If the first and second signals are not synchronized in time when received at the receiving apparatus, then the first and second signals may be time-synchronized at the receiving apparatus either manually or through timestamping of both signals at the source, in conjunction with use of a real-time clock at the receiving apparatus.

Abstract: The various embodiments of the invention provide an apparatus, system and method for data content deskewing among a plurality of data channels for data synchronization. The various embodiments determine whether a data alignment signal has been written, for each data channel of the plurality of data channels, such as a comma character. When a data alignment signal has been written in a data channel of the plurality of data channels, the embodiments determine a corresponding channel location of the data alignment signal for each data channel having the data alignment signal. When each data channel of the plurality of data channels has the data alignment signal, and when the data alignment signal is to be read on a next read cycle in at least one data channel, the various embodiments move a corresponding read pointer for each data channel of the plurality of data channels to the corresponding channel location of the data alignment signal.

Abstract: A non-volatile memory array such as a flash memory array may include a power savings circuit to control a stand-by mode of the non-volatile memory array. The power savings circuit may cause a placement of the non-volatile memory array into a stand-by mode in the absence of activity on at least one or more inputs of the non-volatile memory array. Power may be saved automatically without processor intervention by reducing the operating current of the non-volatile memory array. The automatic power savings circuit may provide a chip enable output to an input of stand-by circuitry to control the operation of the standby circuitry without requiring an explicit stand-by command from a processor.

Abstract: A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by a prescribed number of cycles. The select vector is reduced by an amount and is gray encoded to indicate a first time. The receivers are each coupled to the delay-locked loop. Each of the receivers receives the encoded select vector and a corresponding strobe, and locks out reception of die corresponding strobe for a configurable lockout lime following transition of the corresponding strobe. The encoded select vector is employed by a gray code mux therein to determine the configurable lockout time by selecting a delayed version of the corresponding strobe.

Abstract: A method for synchronizing a data signal to a clock signal in a source-synchronous system, the source-synchronous system having first and second systems linked by an interface, the first system providing the clock signal to the second system, the second system providing the data signal and a return clock signal synchronous to the data signal to the first system, the method comprising: determining a first time delay between the clock signal and the return clock signal and delaying the data signal by the first time delay; after a predetermined period, determining a second time delay between the clock signal and the return clock signal; determining a difference between the first and second time delays; and, further delaying the data signal by at least a portion of the difference to thereby compensate for a temperature change of the source-synchronous system.

Abstract: A semiconductor device may include a control signal generator configured to generate a test control signal in response to an externally applied test command signal. First and second transmission gates may be configured to open and close together in response to a test clock signal pulse and the test control signal. A delay circuit may be coupled between the first and second transmission gates so that the delay circuit is configured to receive a test input signal through the first transmission gate and to transmit a delayed test input signal to the second transmission gate, and the delayed test input signal may correspond to the test input signal.

Abstract: Systems and methods for masking strobe signals in strobe-based systems are provided below. These strobe-masking systems receive a strobe signal from a component operating under one clock domain and in turn generate a masked version of the strobe signal. Components of a host system use the masked strobe signal to receive or transfer data from the clock domain of the strobe signal through a mesochronous clock domain crossing into a different clock domain.

Abstract: A multiplier device is configured to include first to nth multipliers M1 to Mn for multiplying a carrier modulated information signal with first to nth mutually phase shifted and identical, substantially square wave mixing signals MS1 to MSn with 50% duty cycle. In order to eliminate fifth or higher order interferences from the output of the multiplier device according to the invention, n is greater than 2, outputs of the multipliers M1 to Mn are respectively coupled through weighting circuits W1 to Wn with respective fixed weighting factors WF1 to WFn to an adder circuit, the mixing signals MS1 to MSn having respective phase angles ?i corresponding to ?i=i*??, the weighting factors WFi corresponding to the sine value of the respective phase angles ?i=i*?? with ?? being the mutual phase difference between each two phase consecutive mixing signals corresponding to ?/(n+1) and i varying from 1 to n.

Abstract: The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB specification to provide synchronization information from an external source, and in another aspect comprising observing USB traffic and locking a local clock signal of a USB device to a periodic signal contained in USB data traffic, wherein the locking is in respect of phase and/or frequency.

Abstract: A clock adjustment apparatus delays a clock signal and adjusts a phase of the signal, thereby increasing or decreasing a delay amount of the clock signal in accordance with a phase relation between a data signal and an adjusted clock signal. The adjusted clock signal is used for receiving the data signal.

Abstract: A method of receiving data. A plurality of data signals and clocking signals are received over a source synchronous communication channel. The plurality of data signals is strobed with the clocking signal at a plurality of coarse time offset delays (e.g., time offset delays spanning over a data bit period). The plurality of error rates associated with the strobing at the plurality of coarse time offset delays is determined. Strobing design of a transmitting component (e.g., edge-strobed, center-strobed, etc.) may be determined based on the plurality of error rates. The error rates of the plurality of data signals strobed with a plurality of time offset delays close to the determined strobing design of the transmitting component is calculated. A time offset delay is selected based on the error rates. The plurality of data signals can be strobed with the selected time offset delay to recover the transmitted data signals.

Abstract: A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.

Abstract: In a network environment, a first master timing generator generates a first frame reference signal and a second master timing generator generates a second frame reference signal. A first data source generates a first data source signal, a first frame source signal, and a first clock source signal in response to a selected one of the first and second frame reference signals. Similarly, a second data source generates a second data source signal, a second frame source signal, and a second clock source signal in response to a selected one of the first and second frame reference signals. A timing recovery circuit generates a recovered reference signal and a recovered clock signal in response to a selected one of the first and second frame reference signals. A phase aligner stores the first data source signal in response to the first frame source signal and the first clock source signal.

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract: Register includes flip-flop circuits each constructed to retain data of n bit in synchronism with a clock pulse, the register retaining a multiplication result of a multiplier dividedly by the flip-flop circuits, n bit per flip-flop circuit. For each of a first and second numeric value data to be multiplied by the multiplier, a control circuit detects the number of consecutive zeros from the lowest-order bit of the data and performs control, on the basis of the detected number of the consecutive zeros and for each flip-flop circuit, as to whether or not the clock pulse should be supplied to the flip-flop circuit. The control circuit obtains an integral quotient value x by dividing by the number n the sum between the detected numbers for the first and second numeric value data, to stop the clock pulse supply to a particular number x of flip-flop circuit counted from the lowest-order.

Abstract: A timing circuit for generating a timing signal having a predetermined relationship with a reference signal. The timing circuit includes a locked loop for generating the recovered clock signal, comparing the phase of the reference signal to the phase of the timing signal, and adjusting the phase of the timing signal based on the comparison; and a PVT (Process-Voltage-Temperature) line operatively associated with the locked loop so that PVT drift in the PVT line counters PVT drift in the locked loop.

Abstract: Systems and methods are disclosed herein to provide signal monitoring techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a phase detector circuit that receives an input signal and samples the input signal to provide binary state signals. A signal monitoring circuit decodes the binary state signals and provides at least one output signal indicating for the input signal path equalization and/or duty cycle distortion.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an accompanying clock signal HA. This accompanying clock signal transmitted by the transmitter equipment A is used by the receiver equipment B to sample the transmitted data. An alternation is effected at the receiver equipment B between a phase of operation during which the clock signal HA accompanying the data is replaced by a local clock signal HLS of the same frequency and a phase of operation during which the local clock signal is periodically re-synchronized with the accompanying clock signal. Means to implement the method are also disclosed.

Abstract: A circuit for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided by the clock circuit. A delay calculation circuit receives the determined number of delay elements and calculates a number of delay elements needed to delay the input control signal by an amount of time. A delay circuit includes a control signal input, a select input for receiving the number of delay elements provided by the delay calculation circuit.

Abstract: A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths. The master device may adaptively modify transmit characteristics based upon data eye information sent via one or more unidirectional data paths by the slave device. The data eye information may correspond to an edge position of data signal transitions received by the slave device on each data path of the plurality of bidirectional data paths. In addition, the master device may modify data path equalization coefficients within the master device for a grouping of the bidirectional data paths such as a byte group, for example, dependent upon the data eye information.

Abstract: Variable compensation for part to part skew of components in a substrate-mounted circuit is described. The variability may be provided through a computer software program acting on a programmable delay buffer such that compensation for a skewed signal may be continuously checked against a reference signal or through other methods. The skewed signal may be delayed until the signal matches, within a predetermined margin of error, the reference.

Abstract: A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.

Abstract: Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance. The interface utilizes request and acknowledge phases and signals and an initiator-target relationship between components that allow each side to throttle the communication rate to an accepted level for each component or achieve a desired bit error rate.

Abstract: Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.

Abstract: A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with deterministic skew adjustment set during a receiver training period. Intrapair skew refers to the skew within a pair of differential signals, and is hence interchangeable with the term differential skew in the context of this document. During the receiver training period, a training data pattern is received, such as alternating ones and zeros (e.g., a D10.2 pattern as is known in the art), rather than an actual data payload. The differential serial communication receiver circuit includes a differential skew compensation circuit to compensate for intrapair skew.

Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

Abstract: A clock distributor circuit is provided which works with power consumption reduced in semiconductor logic circuitry including clock synchronous circuits. The clock distributor circuit includes clock generation circuits generating gated clock signals in response to a clock enable signal to supply clock synchronous circuits with the generated clock signals. It is thus possible to reduce the power that would otherwise consumed by the toggling of the clock signal. A clock distribution method therefore is also provided.

Abstract: A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive PCR input signals. The system also includes a first storage device for generating a first PCR signal corresponding to the time interval between arrival of successive PCR input signals and a PCR inter-arrival time computation filtering device to determine the average time of arrival difference between successive PCR packets. The system further includes an error correction device for minimizing error in the average PCR difference between successive PCR packets, a controlled system clock generator coupled to the output of the error correction device to generate system clock, a second storage device for generating a first system clock output, and a controlled clock period difference computation element for computing the clock period difference between the first and second system clock outputs.

Abstract: Disclosed are a method and system for calculating clock offset and skew between two clocks in a computer system. The method comprises the steps of sending data packets from a first processing unit in the computer system to a second processing unit in the computer system, and sending the data packets from the second processing unit to the first processing unit. First, second, third and fourth time stamps are provided to indicate, respectively, when the packets leave the first processing unit, arrive at the second processing unit, leave the second processing unit, and arrive at the first processing unit. The method comprises the further steps of defining a set of backward delay points using the fourth time stamps, and calculating a clock offset between clocks on the first and second processing units and clock skews of said clocks using said set of backward delay points.

Abstract: This invention provides a technique for enhancing an operating frequency and improving reliability in a system using at least level sense type sequence circuits as a plurality of sequence circuits. A microcomputer includes a clock generator configured as a clock supply source, functional modules operated in sync with a clock signal, level sense type sequence circuits which are contained in the functional modules and configured as clock supply destinations, a clock supply system which propagates the clock signal to the level sense type sequence circuits, etc. The clock supply system includes a clock wiring which propagates the clock signal outputted from the clock generator to ends thereof via a plurality of branches. At least pulse generators are disposed in the midstream of the clock wiring. Each of the pulse generators varies timing provided to change the falling edge of the clock signal, which defines an endpoint of an input operating period of each level sense type sequence circuit.

Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: A technique includes in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus. The technique includes based on the communication, regulating a timing between a strobe signal and a signal that propagates over the data bit line.

Abstract: A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.

Abstract: System and method for synchronizing multiple devices coupled to a system timing module (STM) via respective first transmission media, wherein two or more of the respective first transmission media have different respective transmission times. The STM and devices share a common clock, in phase and with respect to a common reference. Each device is configured to transmit respective signals to the STM within a common clock cycle. Respective delays corresponding to the devices are determined based on the respective transmission times, where the respective delays are applicable to respective signals received from the devices to synchronize received corresponding pulses in the signals to within a common clock cycle. The respective delays are applied to respective signals received from the plurality of devices to synchronize received corresponding pulses in the signals to within the common clock cycle, after which the STM is operable to trigger the devices as a single device.

Abstract: Embodiments of the invention relate to distribution of clocks to CPUs in processing cells of a multi-cell system. In an embodiment, each cell includes an interface, referred to as an agent. A plurality of interfaces, referred to as switches, together with the agents of the cells, connects the cells together. A clock source provides a clock to a switch, which replicates the clock and provides the replicated clocks to its ports. Each port of the switch, receiving a replicated clock, encodes this replicated clock and sends it over a link to each agent of a cell. Each agent of the cells, receiving an encoded clock, decodes this encoded clock, resulting in a decoded, or an extracted, clock. The agent then replicates the extracted clock and provides the replicates of the extracted clock to a plurality of CPUs of the cell. As a result, CPUs in all cells of the system receive clocks that all are synchronized to the clock provided by the clock source.

Abstract: Systems and methods can be employed to sample a signal and determine a frequency of the signal. In one embodiment, the system may comprise a sample network that provides plural indications of signal state associated with different time instances of an input signal. A detector provides an indication of frequency for the input signal based on the plural indications of signal state.

Abstract: An extendible timing architecture for an integrated circuit is disclosed. The extendible timing architecture provides metal programmable components for use with different operational clock frequencies. In some embodiments the architecture utilizes master/slave DLLs with a double data rate memory circuit.

Abstract: An apparatus and a system, as well as a method and article, may operate to independently adjust a plurality of processor clocks coupled to a corresponding plurality of networked processors responsive to one or more status indicators to provide scalable performance and power consumption. The status indicators may indicate the status of routers coupled to the processors. Additional apparatus, systems, and methods are disclosed.

Abstract: A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit.

Abstract: The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period.

Abstract: The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.