Abstract: A circuit according to an embodiment of the present invention comprises a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a PLL circuit which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at an end point of the first clock distribution network, to a start point of the first clock distribution network, and a PLL circuit which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at an end point of the second clock distribution network, to a start point of the second clock distribution network.

Abstract: A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffered clock signal and generates a delayed clock signal, and an output circuit including output signal paths for outputting the output signals synchronously with the system clock signal by using the delayed clock signal. At least one of the output signal paths includes a delay circuit and an output buffer. Each delay circuit provides a programmable delay to the delayed clock signal to generate a unique delayed clock signal used to clock an output signal into the respective output buffer. By programming the delays based upon output skew, the output skew can be improved.

Abstract: Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.

Abstract: In a network environment, a first master timing generator generates a first frame reference signal and a second master timing generator generates a second frame reference signal. A first data source generates a first data source signal, a first frame source signal, and a first clock source signal in response to a selected one of the first and second frame reference signals. Similarly, a second data source generates a second data source signal, a second frame source signal, and a second clock source signal in response to a selected one of the first and second frame reference signals. A timing recovery circuit generates a recovered reference signal and a recovered clock signal in response to a selected one of the first and second frame reference signals. A phase aligner stores the first data source signal in response to the first frame source signal and the first clock source signal.

Abstract: A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.

Abstract: A Mobile Subscriber Directory Assistance (MSDA) system including originating carrier center initiating a directory assistance call, a directory assistance center providing a directory assistance service, and a search environment. The search environment includes an aggregated pointer database and at least one directory number resolution database. A caller requesting a telephone number is connected to a directory assistance service center where search criteria for the requested number are taken. The requested number is identified by searching the aggregated pointer database and the directory number resolution database. The caller is connected to the identified telephone number without releasing this identified telephone number.

Abstract: A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the device in a second state or mode. The second state or mode can be temporary. The changing of the state or mode of the device can be used to perform testing of the chip, during which a memory is written to and read from to verify operation of the chip. The second state or mode of the device may also be used to allow the device to perform alternative functions that are not available during its first state or mode.

Abstract: In a method and device measuring a delay time of a section of a digital circuit, an output signal of the section is saved in different memory locations with a clock and earlier by a time interval with respect to the clock, different durations being assigned to the time interval. The delay time is determined as a function of the greatest of the different durations during which a test proceeds in a positive manner. The test proceeds in a positive manner if the value saved with the clock corresponds with the value saved so as to be earlier by the corresponding time interval.

Abstract: An embedded system optimally operates with minimal power consumption without sacrificing performance. Power consumption can be reduced by independently and dynamically controlling multiple power partitions, wherein components within a partition can have the same power profile. States of operation can be programmably defined in a table and enforced using hardware. Voltages in the table can be dynamically updated during a runtime of the system using a timing feedback module, which is connected to a critical path in a partition. The timing feedback module can output a vector that indicates the timing margin for that critical path. Using this timing margin, software can increase or decrease the voltage to optimize power consumption of that partition.

Abstract: Systems and methods are disclosed for timer architectures. For example, in accordance with an embodiment of the present invention, a timer system includes a prescaler and one or more timer cells each having a multiplexer and a counter.

Abstract: An apparatus for coupling two circuits having different supply voltages is described herein.

Abstract: An integrated circuit memory system includes one or more memory modules in which at least one of the memory modules is responsive to a control signal and has delay control information stored thereon. The memory system further includes a memory controller that is configured to generate the control signal in response to the delay control information.

Abstract: The present invention relates to a data processing circuitry and method of processing an input data pattern and out-putting an output data pattern after a processing delay which depends on a processing activity of the data processing circuitry, wherein the processing delay is estimated based on the input pattern and the processing is controlled in response to the estimated processing delay. The processing control may be a power control based on an activity monitoring or a clock control in a pipeline structure. Thereby, an efficient solution is provided to derive the current activity of the processing circuitry in order to dynamically adapt its operating conditions to its demands.

Abstract: A method and apparatus for enabling repeated switching of a cross-connect and a timing source in a network element through the use of a phase adjuster. In one embodiment, a traffic card includes an aligner to adjust the occupancy of the data in two ingress FIFOs to synchronize their occupancy. In addition, the traffic card includes a clock control logic, including a phase adjuster, to adjust the phase of clock signals driving the two ingress FIFOs to avoid an underflow or overflow.

Abstract: A timing generator f or a semiconductor test device reduces pattern-dependent jitters and timing errors of timing pulse signals. In the timing generator, a delaying circuit (variable delaying means, clock signal delaying circuit) is disposed on an input terminal side of a clock signal of a signal input/output circuit having the flip-flop (reference signal delaying means) which outputs an output signal in accordance with an input timing of the delayed clock signal. The clock signal is delayed by the delaying circuit. The clock signal delaying circuit may be replaced with a phase locked loop circuit.

Abstract: An apparatus for performing stuck fault testings within an integrated circuit is disclosed. A delay chain structure includes a first select register, a second select register, a decoder and a chain of multiplexors. With a set of select signals, the first select register generates a set of true encoded select signals, and the second select register generates a set of complement encoded select signals. Coupled to the first and second select registers, the decoder decodes the set of true encoded select signals and the set of complement encoded signals for controlling the chain of multiplexors. Each multiplexor within the chain of multiplexors is connected to one of the outputs of the decoder. The chain of multiplexors generates a single output value based on the set of select signals.

Abstract: Trigger reception on different instrumentation devices may be synchronized by each instrumentation device generating one or more trigger enable signals and delaying performance of an operation in response to a trigger signal until a transition in a trigger enable signal. An instrumentation system may include several instrumentation devices and a communication medium coupling the instrumentation devices. One of the instrumentation devices may process data in response to a sample clock signal. That instrumentation device may also generate a trigger enable signal and delay performing an operation in response to a trigger signal transmitted via the communication medium until a transition in the trigger enable signal occurs. The trigger enable signal is not the sample clock signal. The trigger enable signal may be synchronized to another trigger enable signal generated by another one of the instrumentation devices.

Abstract: A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon occurrence of a cycle synchronization event on the local portal; the peer portal sampling its local cycle timer to obtain a sample value when the peer portal receives the synchronization signal; a bridge manager at an upstream portal communicating the sample value to a bridge manager at an alpha portal; the bridge manager at the alpha portal using the sampled time value to compensate for delays through a bridge fabric, calculate the correction to be applied to a cycle timer associated with the alpha portal, and correct the cycle timer.

Abstract: A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal when the lengthy operation is activated. The clock control circuit receives the clock signal and outputs a gated clock signal only when the first device is not producing the control signal. The processor unit runs off of the gated clock signal. The first device may be a memory, and the lengthy operation may be correction of a soft error in memory. According to a second aspect, the first device requires a longer clock cycle rather than more clock cycles. The clock can be gated to effectively double the period when the lengthy operation is activated.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: Circuits, methods, and apparatus that provide a precise phase shift for a read strobe or other signal. One embodiment provides a read strobe delay line including a series of delay elements, where inputs or outputs of at least some of delay elements are received by a multiplexer. One input of this multiplexer is selected as the read strobe signal. Further precision adjustment may be made in the delay of the read strobe signal by using a delay line in a reference delay-locked loop, where that delay line also includes a series of delay elements, and inputs or outputs of at least some of the delay elements are multiplexed.

Abstract: Circuits, methods, and apparatus that prevent control signals from changing state while the control signals are being used to delay a read strobe signal. An exemplary embodiment of the present invention provides a control circuit that provides a plurality of control bits to a delay line, where the delay line delays or phase shifts a read strobe signal a duration, where the duration depends on the state of the control bits. The delayed read strobe signal is used to clock one or more data registers. To avoid undesired changes in the duration that the read strobe signal is delayed, the control bits are retimed before being provided to the delay line. A specific embodiment waits for an edge of the strobe signal to be output by the delay line before providing the control bits to the delay line. Another specific embodiment waits until no edge of the strobe signal is being delayed by the delay line before providing the control bits to the delay line.

Abstract: In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.

Abstract: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.

Abstract: Delays through components of a programmable device are determined transparently to the user through the use of mimic paths. For each delay path to be measured, at least one mimic path is created that has similar components and characteristics to the actual path to be measured. A signal fed through this mimic path will experience similar delay to a signal passing through the actual path, which can be affected by temperature and voltage variations during operation. A swept clock signal can be passed to a register latching the mimic signal data, producing output that can be fed to lead/lag logic to determine a current value of the delay through the mimic path. This delay can be compared to a previous delay determination to approximate an adjustment to be made to a sampling clock used to latch the actual data into the appropriate register at the middle of the latching window.

Abstract: A programmable synchronizer system for effectuating data transfer across a clock boundary between a core clock domain and a bus clock domain, wherein the core clock domain is operable with a core clock signal and the bus clock domain is operable with a bus clock signal, the core and bus clock signals having a ratio of N core clock cycles to M bus clock cycles, where N/M?1. A first synchronizer is provided for synchronizing data transfer from a core clock domain logic block to a bus clock domain logic block. A second synchronizer is operable to synchronize data transfer from the bus clock domain logic block to the core clock domain logic block. Control means are included for controlling the first and second synchronizers, the control means operating responsive at least in part to configuration means that is configurable based on skew tolerance and latency parameters.

Abstract: The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising edge of the read clock occurs during the second half of the write clock cycle. Responsive to this determination, the data written into the FIFO buffer element is shifted in order to reduce skew.

Abstract: A method, apparatus and system are provided for bundle skew management and cell synchronization. According to one embodiment, determination is made as to whether a link upon which a cell was received was an expected link in a predetermined round-robin order. If the link upon which the cell was received was not the expected link in the round-robin order, a wait for arrival of a cell on the expected link for up to the value of a timer for the expected link is made. If the link is not the expected link, the link may be removed from the round-robin order and cell synchronization may be performed.

Abstract: A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is driven by an output clock signal generated by a delay lock loop (DLL). The output clock signal is phase-shifted relative to a reference clock signal received by the DLL such that the data removed from the output latch is synchronous with the reference clock signal. Further the duty cycle of the output clock signal is adjusted in a phase inverse relationship to the duty cycle distortion introduced by the output latch. As a result, the output data signal has reduced duty cycle distortion.

Abstract: A transmission arrangement and method permits time-sensitive data to be transmitted through a packet-switched network and arrive synchronously at separate end points without synchronising all payload carrying nodes in the network. This is achieved by propagating a timing reference through the network from the sending node to the end nodes, each end node adjusting that phase of its local frequency generator to this timing reference. The sending node then sends data structure information to the end nodes, enabling the end nodes to regenerate the timing and structure of the synchronous data stream. Finally delay information is sent to each end node that allows the end nodes to adjust the start of synchronous data transmission by an amount such that all will commence transmission substantially simultaneously. With this information the end nodes independently recreate a signal in synchronisation.

Abstract: A method transfers a signal from a transmitting device to a receiving device. The signal is output from the transmitting device using a driving circuit. A reference clock signal is received in the transmitting device. An output clock signal is generated according to the received reference clock signal and a feedback clock signal in a phase locked loop. A delay is provided in a path of the reference clock signal and a path of the feedback clock signal. The delay is configured to make the output signal meet a predetermined valid data timing requirement.

Abstract: A baseboard management controller (BMC) hosts a real-time clock and non-volatile RAM replacement that does not require a battery power supply. The BMC includes an I/O mapped interface responsive to I/O accesses to an address range associated with storage locations of a real-time clock circuit and storage locations holding configuration information. The BMC receives power when a processor coupled to the BMC is not powered. The I/O address range may include 70h and 71h. A network interface may communicate information between a network external to the BMC and the real-time clock and/or the storage locations holding the configuration information. The network external to the BMC may communicate clock synchronization and/or configuration information to the BMC.

Abstract: A method and apparatus for determining the write delay time of a memory are provided. The apparatus includes a CPU, a memory, a north bridge chipset, a south bridge and a BIOS. The north bridge chipset, which is connected to the CPU and the memory, writes a pattern to the memory according to different write delay times. The BIOS reads the pattern stored in the memory, and checks the correctness of the read pattern to determine the common write delay time.

Abstract: A system and method for coordinating synchronizer controllers disposed in different clock domains, e.g., a core clock domain and a bus clock domain, wherein a clock synchronizer arrangement is employed for effectuating data transfer across a clock boundary therebetween. A bus clock synchronizer controller operable in the bus clock domain includes circuitry for generating a set of inter-controller clock relationship control signals, which are provided to a core clock synchronizer controller. Responsive to the inter-controller clock relationship control signals, circuitry in the core clock synchronizer controller is operable to synchronize the core clock signal's cycle and sequence information relative to the bus clock signal.

Abstract: An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input data of each operation unit, a plurality of second wire sets that extend in a second direction in the matrix and transfer output data of each operation unit, and a plurality of switching units that are arranged at each intersection between the first and second wire sets and can select and connect any wire in the first wire sets and any wire in the second wire sets. The plurality of operation units include a plurality of types of operation units with different data paths that are suited to special-purpose, processing, with an arrangement of operation units of the same type in the first direction or the second direction being formed in at least part of the data processing block.

Abstract: The invention relates to a method for synchronizing a first clock C to a reference clock A, the first clock C being connected to said reference clock A via a processing unit B. The invention moreover relates to a processing unit B and to a synchronization system. In order to enable a synchronization of said first clock C to said reference clock A via said processing, unti B. it is proposed that the processing unit B generates a correction message cmsg for the first clock C based on timestamps exchanged between the processing unit B and the reference clock A, which exchanged of timestamps is triggered by clock pulses cclk received in the processing unit B from the first clock C.

Abstract: A master device communicating a first range of speeds at which the master device is operable, to a first slave device, the master device and the first slave device determining a second range of speeds most closely matched to the first range of speeds at which each of the master device and the first slave device is respectively operable; and the master device setting the operating range of speeds of each of the master device and the first slave device to the second target range of speeds.

Abstract: An adjustable logic circuit includes a pulse filter and delay circuit, a state machine and combinational logic circuit, and a data strobe generation circuit. The pulse filter and delay circuit is operative to read an adjustable configuration value and, based thereon, to implement a delay between an internal clock and both a data signal and a data strobe signal, the delay being a fraction of a clock period. The state machine and combinational logic circuit are operative to select a data value from a plurality of data values, and to provide a data signal based upon the data value. The data strobe generation circuit is operative to provide the data strobe signal at a time when both the data signal is valid and the delay is compatible with a predetermined external device.

Abstract: A recording medium and a method and apparatus for managing data are provided. The method includes recording additional data in a data file separate from a file containing main data and recording navigation information that links the main data and the additional data. The additional data are segmented into a plurality of predetermined units, each of the predetermined units including time information indicating a presentation start time of the corresponding unit.

Abstract: An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

Abstract: A method for synchronizing data utilized in a redundant, closed-loop feedback control system is disclosed. In an exemplary embodiment, the method includes configuring a plurality of control nodes within the control system, with each of the plurality of control nodes transmitting and receiving data through a common communication bus. At each of the plurality of control nodes during a given control loop time T=N, the receipt of externally generated data with respect to each control node is verified, the externally generated data having been generated during a preceding control loop time T=N?1. At each of the plurality of control nodes during the given control loop time T=N, output control data is calculated using the externally generated data. During the given control loop time T=N, the calculated output control data from each individual control node is further transmitted over the communication bus to be later utilized by other control nodes during a subsequent control loop time T=N+1.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A distributed multi-axis motion control system comprises a multicast communications network having several node components. Each of the node components includes a clock and an actuator. The actuators are part of a motor system and a pattern profile table of the motor system is generated. The pattern profile table is translated into a separate single-direction-of-motion pattern table to separately direct the motion of each of the actuators of the node components. A grandmaster clock generates synchronization signals which are transmitted through the network at a sync interval and which synchronize the clocks. Time-bombs are generated at an interval which is a whole number multiple of the sync interval. The time-bombs cause concurrent execution of the first and subsequent steps from the single-direction-of-motion pattern tables to produce synchronized multi-axis motion of the motor system.

Abstract: An interfacing logic is implemented in one or more processors and a memory controller in a multiprocessor system. The interfacing logic enables all processors to receive snoops and snoop responses substantially at the same time by delaying data transmitted over faster busses before the data is provided to a local logic at a receiving end of the faster busses. The interfacing logic comprises two or more paths of a multiplexer component connected to a storage component. The storage components are connected to another multiplexer component for selecting one of the two or more paths. Preferably, a bus control logic in the receiving end determines how much delay is performed to compensate for delay differences between data busses.

Abstract: A sampling device includes a first delay circuit and a second delay circuit in a parallel configuration, where the first delay circuit and the second delay circuit are responsive to a clock signal. A data sampling circuit may use an output of the first delay circuit and an output of the second delay circuit to sample a data signal synchronized with the clock signal. The data signal and the clock signal may be synchronized according to a double data rate (DDR) protocol.

Abstract: A method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains is described. In one embodiment, the invention is an apparatus. The apparatus includes a first subsystem and a second subsystem coupled to the first subsystem. The apparatus also includes a clock signal generator coupled to the first subsystem and coupled to the second subsystem. The clock signal generator is to supply a first clock to the first subsystem and to supply a second clock to the first subsystem and to supply a third clock to the second subsystem. Each of the first clock, the second clock and the third clock are derived from a common clock, the first clock having a first predetermined phase offset relative to the third clock, and the second clock having a second predetermined phase offset relative to the third clock.

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract: Method and apparatus for serial data transfer between at least two modules (10, 12) connected to each other by way of a serial data bus (18) where the data transfer is governed by a clock signal (CLK). The modules (10, 12) each comprise a receiver unit (30) for the reception of the data and a transmitter unit (22) for the transmission of data. The output of a data value by the transmitter unit (22) of one module (12) to another module (10) at the serial data bus (18), and the import of the data value by the receiver unit (30) of the corresponding other module (10) are initiated by slopes of the clock signal (CLK). The clock signal that triggers the transmission of this data value in the one module (12) is delayed via a delay element (38) one pulse repetition period (?TP) of the clock signal (CLK).

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: One or more methods and systems of resynchronizing or dynamically retuning a clock signal over a high speed clocked data interface are presented. In one embodiment, the system and method utilizes first and second delay lines, a first pair of digital logic devices to generate a first data sequence, a second pair of digital logic devices to generate a second data sequence, a memory, a set of software instructions resident in the memory, a processor, and a user interface. The first and second data sequences are input into a digital logic circuit that compares the two sequences and generates an output. The output is clocked into a digital logic device to generate an indicator signal that is used to resynchronize or dynamically re-tune the clock signal.