Abstract: A synchronous clear emulation circuit is provided. The synchronous clear emulation circuit includes a register having an asynchronous clear port. Moreover, the synchronous clear emulation circuit is configured to emulate a synchronous clear port by using the asynchronous clear port. The synchronous clear port is emulated by outputting a data output signal that is synchronous with the clock signal and the data output signal is based on an asynchronous clear signal received at the asynchronous clear port. The asynchronous clear port performs a function of the asynchronous clear port without the synchronous clear port implemented within the register.

Abstract: Methods and apparatus are provided for trimming of one or more CDR clock buffers using a histogram of clock-like data patterns. One or more clock buffers in a clock and data recovery system are trimmed by receiving a first transmitted clock-like data pattern in a reduced rate mode, wherein the first transmitted clock-like data pattern is transmitted using a first rate mode and wherein the reduced rate mode divides the first rate mode by an integer value that is greater than one; locking the clock and data recovery system using the received version of the first transmitted clock-like data pattern in the reduced rate mode; receiving a second transmitted clock-like data pattern, wherein the second transmitted clock-like data pattern has a run-length that is an integer division of a run-length of the first transmitted clock-like data pattern, wherein the integer division is greater than one; and adjusting a phase of the one or more clock buffers using the second transmitted clock-like data pattern.

Abstract: An embodiment of a circuit includes an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.

Abstract: In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow.

Abstract: A system and method for efficient timing optimization for asymmetric paths to replicated units. A microprocessor may include multiple instantiations of a processing core. Chip-level interconnects may have asymmetric routing paths to the multiple cores. The interconnect routes may need to be stable early in the design cycle and yet possess multiple timing paths to the multiple instantiated cores. Modifications to the input/output ports of the cores may provide the necessary timing requirements for the cores without dynamically altering the chip-level interconnects.

Abstract: In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method comprising: beginning a link negotiation stage between the device and the host using the device reference clock; during the link negotiation stage, sampling data received from the host to determine a frequency offset of the host reference clock; applying the frequency offset to the device reference clock to create a corrected device reference clock; and completing the link negotiation stage using the corrected device reference clock. This completing may include either continuing the original link negotiation stage or restarting it.

Abstract: Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word.

Abstract: A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is synchronized with a local clock signal, and capturing data from a delayed data signal associated with the delay in a local domain.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: Protocol analyzer systems enable synchronization of timestamps and the capture of data across serially chained boxes that are used together to monitor and capture network data. Through experiment, it can be determined how long it takes to propagate a signal to each box in the chain. These values are then recorded in each box in a delay register so that each box has a recorded delay value corresponding to the time required to propagate a signal to or receive a signal from every other box. Each box applies a control signal, such as a run signal or a trigger signal, to the ports in the box only after the expiration of the delay value indicated in the delay register. The box initiating the signal has the largest delay since the other boxes need to get the signal before the boxes can begin to operate with a common counter, with successive boxes having smaller delays.

Abstract: A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The method includes receiving the additional data associated with the main data, the additional data being divided into a plurality of segment units; and reproducing the additional data in a synchronous manner with the main data using time information if indication information indicates a presence of the time information. The time information indicates a presentation time of the additional data with respect to the main data. The main data and the additional data are reproduced according to management data, the management data including link information for linking the main data and the additional data.

Abstract: A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state signals provided by the apparatus, perform corresponding actions, and generate corresponding synchronized command signals; and a peripheral module structured to receive the synchronized command signals and generate output signals to be processed by the processor core in accordance with the control algorithm.

Abstract: Systems and methods for performing output delay adjustment are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave device, and each slave device passes the clock to the next slave device in turn, and the last slave device returns the clock to the master device. The master device compares the outgoing clock to the returned clock and determines if an output delay adjustment is needed. If so, the master device generates and outputs commands for the slave devices to perform output delay adjustment. The slave devices apply the output delay to the clock signal, but may also apply the delay to other output signals. Each of the slave devices has a circuit for performing output delay adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller.

Abstract: To synchronize units of a formation evaluation/drilling operation evaluation system, a time delay associated with a communications link between a master unit and a slave unit of the formation evaluation/drilling operation evaluation system is determined. The master unit has a master time clock that provides universal time. The time delay associated with the communications link is used to enable synchronization of time provided by a slave time clock in the slave unit to the universal time.

Abstract: One or more counter units of a data acquisition device used to perform sampling operations. Each of the counter units is configurable to operate in a selected one of a plurality of modes. During operation, at least one of the counter units may receive a measurement signal (or input signal) acquired by the data acquisition device and also a sample clock signal. The counter unit may sample the measurement signal based on the selected operational mode and timing of the sample clock, and at a rate that is independent of the frequency of the measurement signal. Furthermore, the counter unit may sample the measurement signal based on a selected one of a plurality of timing modes associated with the sample clock signal. The counter units may take samples of the measurement signal to perform at least one of the following types of measurements: period, frequency, pulse-width, semi-period, time separation, or event counting.

Abstract: The asynchronous circuit insensitive to delays comprises at least one time delay insertion circuit on the propagation path of a signal. The delay insertion circuit comprises, between an input and an output of the signal, a Muller C-element and a plurality of delay circuits connected in series to an output of the Muller C-element. The outputs of the delay circuits are connected to corresponding inputs of a multiplexing circuit having an output constituting the output of the delay insertion circuit. The Muller C-element comprises an input connected to the output of the last delay circuit via an inverter gate, and an input constituting the input of the signal to the delay insertion circuit. The multiplexing circuit control circuit preferably comprises a random generator.

Abstract: The invention provides an integrated circuit with reduced electromagnetic interference induced by memory access. The integrated circuit includes a random code generator, a request receiver and a memory unit. The random code generator generates a plurality of random codes according to a predetermined delay parameter. The request receiver obtains an input clock signal according to a plurality of data requests and spreads the spectrum of the input clock signal based on the random codes to derive a non-periodic output clock signal. The memory unit accesses image data to be displayed in response to the data requests and the output clock signal.

Abstract: A circuit system periodically checks a system-environment monitor value, and then obtains a system-environment monitor value index corresponding to the system-environment monitor value in the environment-adjustment look-up table. Finally, the circuit system adjusts a signal delay time according to a delay adjustment value corresponding to the system-environment monitor value index.

Abstract: To include a first level shift circuit that converts a first internal clock signal having an amplitude value of a first voltage into a second internal clock signal having an amplitude value of a second voltage, a second level shift circuit that converts a first internal data signal having the amplitude value of the first voltage into a second internal data signal having the amplitude value of the second voltage, a clock dividing circuit that generates third and fourth internal clock signals, which are complementary signals, based on the second internal clock signal, and an output circuit that outputs external data signals continuously from a data output terminal in synchronization with the third and fourth internal clock signals based on the second internal data signal. According to the present invention, because a level shift of a signal is performed before it is input to the output circuit, there occurs no skew in output data.

Abstract: A Multi-Level Processor 200 for reducing the cost of synchronization overhead including an upper level processor 201 for taking control and issuing the right to use shared data and to enter critical sections directly to each of a plurality of lower level processors 202, 203 . . . 20n at processor speed. In one embodiment the instruction registers of lower level parallel processors are mapped to the data memory of upper level processor 201. Another embodiment 1300 incorporates three levels of processors. The method includes mapping the instructions of lower level processors into the memory of an upper level processor and controlling the operation of lower level processors. A variant of the method and apparatus facilitates the execution of Single Instruction Multiple Data (SIMD) and single to multiple instruction and multiple data (SI>MIMD). The processor includes the ability to stretch the clock frequency to reduce power consumption.

Abstract: Systems and methods for correcting clock duty cycle are provided for application in serial-connected devices operating as slave devices. A master device provides a clock to the first slave device, and each slave device passes the clock to the next slave device in turn, and the last slave device returns the clock to the master device. The master device compares the outgoing clock to the returned clock and determines if a duty cycle correction is needed. If so, the master device generates and outputs commands for the slave devices to perform duty cycle adjustment. Each of the slave devices has a circuit for performing duty cycle adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller.

Abstract: An Apparatus, method, and system for transmitting data in a Wireless Local Access Network (WLAN) in a power management state are provided. The method includes registering a standby state entrance to an Access Point (AP), switching to an active state at a period, determining whether transmission standby data exists in the AP, transmitting, if the transmission standby data exist in the AP, a standby state entrance frame notifying the entrance to the standby state to the AP, transmitting an active request signal requesting a switching to an active state to the CPU, transmitting a signal notifying standby state release to the AP if a signal notifying switch completion to an active state is received from the CPU after the active request signal is transmitted, and receiving transmission standby data from the AP.

Abstract: A method of calibrating read operations in a memory system is disclosed. The method involves placing a memory controller in a calibration mode, and performing a series of dummy read operations. Each of the read operations performs a read of pre-specified data stored in at least one memory component while using different ones of delayed enable signals. Data read from respective dummy read operations is compared to identify successful read operations while the timing information from successful read operations is compared to identify a suitable delayed enable signal.

Abstract: A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated delay-locked loop. The memory device may be included in a processing system. Moreover, a method for improving timing budgets in a registered dual in-line memory module (RDIMM) may be implemented using the memory device having a register with an integrated delay-locked loop.

Abstract: Clock synchronization for a wireless communication system is described. The communication system utilizes a server with a radio coupled to receive a radio frequency (RF) signal and a clock interface to receive a reference clock signal. The server includes a network interface configured to receive, from a base station, a time that the RF signal was received at the base station. The server further includes a processing device configured to determine when the RF signal was transmitted and a location of the base station, and configured to calculate clock offset value representative of a time to delay a local clock signal at the base station to synchronize the local clock signal at the base station with the reference clock signal.

Abstract: A timing error correction method used at the transmitting end in high-speed serial data transmission system comprises inputting a predefined parallel data training sequence and a clock signal, converting the training sequence into serial data, counting the number of the rising or falling edges of the serial data within a certain period, sending an adjustment signal for adjusting the time delay of the clock signal, obtaining a reasonable serialization timing, so that the number of the rising edges or falling edges of the serial data being equal to a predefined correct number. The corresponding timing error correction system comprises a data path, an adjustable delay clock path, a serialization unit for converting the parallel data into serial data, a driver unit, and a counting judging unit for counting the number of the rising or falling edges of the serial data and sending an adjustment signal to the adjustable delay clock path so as to control the timing of the serialization unit.

Abstract: The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a reset stage for resetting the network node in response to a bus reset pulse received through the network and a control means for issuing a bus reset pulse of a predetermined length substantially greater than a clock period of the clock signal of the local crystal oscillator. Further the network node includes a bus reset detector for determining a length of the received bus reset pulse based on the local time reference. The bus reset detector in the network node is also adapted to adjust the local time reference based on the determined length of the received bus reset pulse.

Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.

Abstract: Systems and methods are disclosed herein to provide channel-to-channel skew control in accordance with one or more embodiments of the present invention. For example in accordance with an embodiment, a method of adjusting skew between first and second channels includes receiving a first channel output signal and a second channel output signal from the first and second channels, respectively; detecting a phase difference between the first channel output signal and the second channel output signal; and controlling, based on the detected phase difference, a signal delay within at least the first channel or the second channel to reduce skew between the first channel output signal and the second channel output signal.

Abstract: A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.

Abstract: An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to the output of the synchronizing circuit. The delay circuit provides an output clock signal having a delay with respect to the clock signal from the synchronizing circuit according to one of a plurality of programmable time delays selected in accordance with a selection signal. The method of generating a clock signal includes synchronizing an internal clock signal to an external clock signal, and delaying the internal clock signal different amounts based on a selection value indicative of external clock frequency to provide the clock signal.

Abstract: Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Abstract: Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.

Abstract: A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchronization at one of the first edges. Output of the data is stopped at the second edge that follows the one of the first edges of the read control signal if the read control signal and the write control signal are in synchronization at the one of the first edges.

Abstract: Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: According to one embodiment, a method is described for relaying streaming data from a first external device and to transmit streaming data to a second external device. The method comprises (i) receiving a first delay time to be needed by the second external device from the second external device, (ii) calculating a third delay time by adding the first delay time to a second delay time to be needed in the information processing device, and (iii) transmitting the third delay time to the first external device.

Abstract: A router, for routing at least one input signal to at least one output, comprises at least one input module and at least one output module. Each of the input and output modules includes at least one clock selector circuit for selecting from among a first and second clock signal, and an oscillator signal, as a common output clock signal for the at least first router, based in part on whether at least one of the first and second clock signals has toggled. The clock selector circuit provides redundancy as well as distribution of clock signals among elements within each module.

Abstract: A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.

Abstract: In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first and second clock inputs. The input buffer circuitry is adapted to select an input clock signal among the first single-ended input clock signal, the second single-ended input clock signal, and a differential input clock signal derived from the first and second single-ended input clock signals. A phase-locked loop (PLL) is adapted to receive an input clock signal selected by the input buffer circuitry and to generate a PLL clock signal based on the selected input clock signal. A clock output provides an output clock signal based on the PLL clock signal.

Abstract: A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.

Abstract: I2C clock generators are implemented using a variety of methods. Using one such method, a method is implemented using logic circuitry arranged in a state machine to control the clock signal (110) on the I2C bus. A first state (202) of the state machine determines whether to effect a clock stretching delay. A second state (206) of the state machine determines whether the I2C bus is configured to run in a standard clock mode or in another one of multiple faster clock modes. A third state (210) of the state machine drives the clock signal in one binary logic state for more than about 0.5 microseconds before allowing the clock signal (110) to be driven in the other binary logic state and allowing the clock signal to remain in the other binary logic state for more than about 0.5 microseconds.

Abstract: A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Abstract: A proposal for power management control of an interconnect structure based on power state transition control. The power state transition is based on generating early warning signals and an idle timeout value setting based on response time and detection of subsequent requests.

Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.

Abstract: A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.

Abstract: An embodiment of the invention relates to a clock signal generator and a related method to produce a clock signal that is a rational but non-integer submultiple of a reference clock signal by employing a dithered pulse signal and a fractional phase signal. The rational submultiple includes an integer part and a fractional part, the fractional part including a numerator and a denominator. A dithered pulse generator is configured to produce the dithered pulse signal from a count of the reference clock signal that is reset dependent on the integer part, and a fractional phase signal from a count that is incremented by the numerator and that is reset dependent on the denominator. A phase controller is configured to delay the dithered pulse with a delay proportional to the fractional phase to produce the output clock signal. The delay may be calibrated by internal logic.

Abstract: A controller may include a measurement circuit configured to generate a proxy signal representing delay variations in the controller. The measurement circuit may also generate a measurement value from the proxy signal. A control circuit may be configured to convert the measurement value into a control value. A delay circuit may be adjusted by the control value to alter an amount of delay of a signal.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.