Abstract: A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal. A corresponding method of deskewing a differential signal and a system and circuit therefor are also provided.

Abstract: A digital circuit system includes: a register, for receiving and registering digital data; an operation unit, for operating and generating resulting data according to the digital data registered in the first registering unit; a second register, for receiving and registering the resulting data; a multi-phase clock signal generating unit, for generating a plurality of reference clock signals having different phases with each other; a first selector, for selecting one of the reference clock signals to output a first clock signal to the first registering unit; and a second selector, for selecting another of the reference clock signals to output a second clock signal to the second registering unit.

Abstract: A device may include a processor to execute a thread. The processor may be further configured to execute a set of wrappers that are called from within the thread to invoke a set of one-shot signal objects to generate delayed signals. Each of the set of wrappers may be configured to detect whether different ones of one-shot signal objects that were invoked from within the thread have generated signals at periodic time intervals, determine a delay to be used for invoking one of the set of one-shot signal objects, and invoke the one of the set of one-shot signal object to generate one of the delayed signals based on the delay when the different ones of one-shot signal objects have generated signals at periodic time intervals. The processor may be further configured to receive the delayed signals generated from the set of one-shot signal objects over a time period.

Abstract: A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled to an external data terminal, a second input coupled to an external data strobe terminal, and an output coupled to an internal data terminal. The transmit circuit (340) has a first input coupled to the internal data terminal, a second input for receiving an internal clock signal, a first output coupled to the external data terminal, and a second output coupled to the external data strobe terminal. The controller (210) enables the shared DLL (360) for use by the receive circuit (320) during a receive cycle, and enables the shared DLL (360) for use by the transmit circuit (340) during a transmit cycle.

Abstract: The invention relates to an automation device, with which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The device has a microcontroller (110), which is assigned at least one clock generator (120) and one memory unit (150), and which is connected at least to one data source (140), which is designed to output a data bit-stream to be transmitted.

Abstract: Techniques for managing lower power states for data links are described. An apparatus may comprise a memory unit to store a device connection manager for a controller of a bi-directional serial link connected to a device. The apparatus may comprise a processor operative to execute the device connection manager, the device connection manager operative to read a register of the controller storing information indicating an interface of the controller for the bi-directional serial link is operating in a lower power management state, send a control directive on a periodic basis for the interface to transition to a temporary active state, and receive an interrupt from the interface indicating the device is disconnected from the bi-directional serial link during a temporary active state. Other embodiments are described and claimed.

Abstract: A system is described for encryption and decryption of digital data prior to the digital data entering the memory of a digital device by generating a key, sub-key and combining the sub-key with mixed digital data, where the encryption and decryption occurs between the memory controller and the input output register.

Abstract: Updating timers of central processing units (CPUs) in a multiprocessor apparatus involves the repeated performance of update operations by a device that is coupled to the CPUs via a memory interface. The operations include selecting one of the plurality of CPUs and determining an offset value that estimates a delay time to process a timer update at the selected CPU. A corrected timer value of the selected CPU is determined based on the offset value and a reference time. The corrected timer value is written to a cache line of the selected CPU to cause the selected CPU to update the timer of the selected CPU.

Abstract: A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP value so as to output an adjusted clock signal. By synchronizing transmission data with the adjusted clock signal, reception data is generated. A data adjustment circuit delays the transmission data on the basis of a TAP2 value. By synchronizing the delayed transmission data with the adjusted clock signal, adjusted reception data is generated. A data adjustment control circuit generates the TAP2 value on the basis of a result of a comparison between the reception data and the adjusted reception data, and outputs to a clock adjustment control circuit an instruction to update the TAP value.

Abstract: A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.

Abstract: To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a control method thereof. The data fetch circuit includes an RL measuring part 10 measuring a latency measurement value RLB from an input of a read instruction signal RD to a valid edge of a data strobe signal DQS and an RL count comparing part 30 outputting a BL count start signal BST giving an instruction of a cancel of the cut-off of the data strobe signal DQS after standing by during the time based on the latency measurement value RLB in accordance with an input of a delay read instruction signal RDD.

Abstract: A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices.

Abstract: A local skew detecting circuit for a semiconductor integrated circuit includes a reference delay block that receives a test signal and generates a reference delay signal by delaying the test signal by a predetermined delay time, and a first timing detecting block coupled with the reference delay block, the first timing detecting block configured to receive the test signal, generate a first delay signal by delaying the test signal by the same predetermined delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal.

Abstract: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed version of the reference clock that lags the reference clock by a prescribed number of cycles. The select vector is reduced by an amount and is gray encoded to indicate the lockout time. The receivers are each coupled to the delay-locked loop. Each of the receivers receives the encoded select vector and a corresponding strobe, and locks out reception of the corresponding strobe for the lockout time following transition of the corresponding strobe. The encoded select vector is employed by a gray code mux therein to determine the lockout time by selecting a delayed version of the corresponding strobe.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: Methods and apparatus provide a delayed clock signal to a plurality of serially connected processing elements, such as a bidirectional pipeline processor. The processing elements include forward and reverse processing paths and forward and reverse processing time intervals along the respective paths. The forward and reverse processing time intervals begin when a block of data, such as encryption data, is gated into an individual processing element for processing and terminate when the processed block of data is gated into a subsequent adjacent processing element along the respective forward or reverse processing path. A clock signal distribution circuit provides a clock signal to the plurality of processing elements such that the clock signal arrives at successive processing elements along the clock signal distribution circuit with an increasing amount of delay so that one of the forward or reverse processing time intervals is greater than the other.

Abstract: In a device and a method to execute commands in components of an imaging system, in particular of a magnetic resonance tomography system, local clocks in the components are temporally synchronized, commands, including a respective command execution time specification which respectively specifies at which point in time a command should be executed, are sent to the components, the commands are received by the components, commands and command execution time specifications that are received by components are stored in these components, and a stored command is respectively executed when a time indicated by the local clock coincides with the stored command execution time specification regarding the command.

Abstract: A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares the frequency of the reference oscillator clock with the frequency of a calibratable oscillator clock, turns off the reference oscillator clock and adjusts, in response to a difference in those frequencies, the frequency of the calibratable oscillator clock towards that of the reference oscillator clock.

Abstract: A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting the clock signal to a counting circuit; wherein the replica buffer and the output buffer have the same delay time such that the clock signal received by the counting circuit can be synchronized with that received by the external memory, and therefore the counting circuit can accurately count to a predetermined time according to the clock signal and output an enabling signal to enable a data control signal. The present invention further provides a signal synchronizing method for the memory controller.

Abstract: A device may include a processor to execute a thread. The processor may be further configured to execute a set of wrappers that are called from within the thread to invoke a set of one-shot signal objects to generate delayed signals. Each of the set of wrappers may be configured to detect whether different ones of one-shot signal objects that were invoked from within the thread have generated signals at periodic time intervals, determine a delay to be used for invoking one of the set of one-shot signal objects, and invoke the one of the set of one-shot signal object to generate one of the delayed signals based on the delay when the different ones of one-shot signal objects have generated signals at periodic time intervals. The processor may be further configured to receive the delayed signals generated from the set of one-shot signal objects over a time period.

Abstract: Circuits for measuring a clock signal include a variable digital delay line that is configured to delay the clock signal by variable amounts in response to variable values of a digital control word that are applied thereto, to produce a variably delayed clock signal. A capture stage is responsive to the variably delayed clock signal and to the clock signal to capture a logic state of the variably delayed clock signal during transitions of the clock signal. A controller is configured to generate the variable values of the digital control word that are applied to the variable digital delay line and to identify a value of the digital control word in response to the capture stage capturing a change in the logic state of the variably delayed clock signal during a transition of the clock signal. Related methods and memory devices are also described.

Abstract: A method for adjusting the working frequency of a chip is provided. The method detects a frequency adjustment range of a graphic chip when a system is booted. Then, an application program in full screen mode is executed, and a control hot key is enabled. Afterwards, an input of the control hot key is received to display a user interface. Finally, an input frequency inputted from the user interface is received, and the working frequency of the graphic chip is adjusted according to the input frequency in the frequency adjustment range. Therefore, even though the application program is executed in full screen mode, the working frequency of the graphic chip can still be adjusted according to requirements in any time, which is convenient for the user.

Abstract: A first transfer circuit includes pipeline circuits having different number of stages, and switch circuits that exclusively supply the pipeline circuits with first and second read data. A second transfer circuit includes pipeline circuits having different number of stages, and switch circuits that exclusively supply the pipeline circuits with third and fourth read data. Outputs of the first and second transfer circuits are sequentially output from a multiplex circuit. When a first operation mode is selected, all the pipeline circuits are activated. When a second operation mode is selected, one of the pipeline circuits in the first transfer circuit and one of the pipeline circuits in the second transfer circuit are activated, whereas the others of the pipeline circuits are inactivated.

Abstract: The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed.

Abstract: In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagation speed is substantially equal to the second propagation speed. In one embodiment, the system further includes a plurality of system elements coupled to the bi-directional loop, wherein each respective system element of the plurality of system elements is configured to determine a time reference common to each as an average arrival time at the respective system element of a first signal transmitted in the first direction over the bi-directional loop and a second signal transmitted in the second direction over the bi-directional loop.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: A method and multi-component electronic module device are provided that control the timing of output of data from a plurality of components on the multi-component module. One or more of the components are programmed to delay outputting data by a corresponding amount of time. In one embodiment, the one or more components are programmed such that all of the components output data at substantially the same time when they respond to a control signal. This is particularly useful for multi-component modules that are configured to respond to control signals in a so-called fly-by (or other) configuration that results in the control signal arriving at the components at different times causing the components to react to the control signal at different times.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A frequency regulator for varying a clock frequency of a power-supplied consumer operated in a clocked manner, wherein the frequency regulator is implemented to perform an overall variation of the clock frequency from an actual frequency to a set frequency, such that the overall variation is obtained by a plurality of clock changes, each with a different amount of change, wherein each of the respective amounts of change depends on a power change caused by the associated clock frequency change.

Abstract: The present invention discloses a computer motherboard, which comprises: at least one memory module slot, a flash memory, a central processing unit socket; wherein, the memory module slot is used to plug at least one memory module; the flash memory is used to store BIOS programming codes, in which the BIOS programming codes are provided with at least one memory configuration programming codes for configuring the memory frequency and memory timing of the memory module; the central processing unit socket is used to plug the CPU, and the CPU is at least used to execute the memory configuration programming codes, so, after execution, they could provide a plurality of parameter options for memory frequency and memory timing of the memory modules to be selected one from them.

Abstract: Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set.

Abstract: The present invention provides a method and mechanism for data recovery with phase synchronized clock using interpolator and timing loop module and a data latching circuit. The interpolator can be considered as a programmable delay circuit with a specified delay resolution over the clock period.

Abstract: A method and system for shaping an electronic pulse with a two-pulse response. An input node receives an initial electronic pulse and splits the electronic pulse into a first path and a second path. An output node combines together the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance. An Ethernet chip generates two pulses and transmits the pulses along a first path and a second path respectively. A power combiner/splitter combines together the pulses along the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance.

Abstract: A computer system for writing data to a memory is disclosed. The memory controller in the computer system comprises a system clock, which is generated by the memory controller. A first register captures the lower data word based on the rising edge of the system clock. A second register, coupled to the first register, captures the output of the first register based on the rising edge of the system clock. A third register, captures the upper data word based on the falling edge of the system clock. A forth register, coupled to the third register, captures the output of the third register based on the falling edge of the system clock. A first multiplexer is coupled to a forth register and a second register. A delay element, coupled to the system clock and a first multiplexer, adjusts the phase of the system clock. A second multiplexer, coupled to the system clock, generates a data strobe.

Abstract: A controller may include a measurement circuit configured to generate a proxy signal representing delay variations in the controller. The measurement circuit may also generate a measurement value from the proxy signal. A control circuit may be configured to convert the measurement value into a control value. A delay circuit may be adjusted by the control value to alter an amount of delay of a signal.

Abstract: A programmable delay clock buffer circuit, preferably implemented in a single IC, includes a clock circuit and a plurality of variable delay lines. The clock circuit receives an input clock and is clock feedback signal and generates an intermediate clock. Each of the delay lines is configured to receive the intermediate clock and to receive at least one delay control input. A first variable delay line of the plurality is configured to generate, based on a first delay control input, a first delay from the intermediate clock to produce a clock output signal. A second variable delay line of the plurality is configured to generate, based on a second delay control input, a second delay from the intermediate clock to produce a clock feedback signal. A method of distributing clock with through programmable delay lines is also presented.

Abstract: A memory controller performs a read test for each of a plurality of memory devices to generate a read delay time of each memory device. There is a prime memory device and a subset of memory devices. For each memory device of the subset, the read delay time for the prime memory device is compared with the read delay time of each memory device of the subset of memory devices to generate a differential delay for each memory device of the subset. For each subset memory device, a write test start time of the prime memory device is combined with a differential delay of each memory device to generate a write test start time for the each memory device. A write test for each memory device uses the write test start time for each subset memory device to generate a write launch time for each subset memory device.

Abstract: The invention provides an integrated circuit with reduced electromagnetic interference induced by memory access. The integrated circuit includes a random code generator, a request receiver and a memory unit. The random code generator generates a plurality of random codes according to a predetermined delay parameter. The request receiver obtains an input clock signal according to a plurality of data requests and spreads the spectrum of the input clock signal based on the random codes to derive a non-periodic output clock signal. The memory unit accesses image data to be displayed in response to the data requests and the output clock signal.

Abstract: An interval centroid-based watermark encoder encodes a watermark into a packet flow. Intervals are defined for the packet flow. Some of the intervals are selected as group A intervals while other intervals are selected as group B intervals. Group A and group B intervals are paired and assigned to watermark bits. A first or second value may be encoded by increasing the relative packet time between packets in either the group A (for the first bit value) or group B (for the second bit value) interval(s) of the interval pair(s) assigned to the watermark bits that are to represent the first or second bit value and the beginning of the same group interval(s). The relative packet times may be measured by a decoder and used to calculate a centroid difference for each interval pair. The centroid differences may be used to reconstruct the watermark.

Abstract: A circuit is described comprising a first (10) and a second circuit module (20) and a synchronization module (30). The first and the second module are mutually asynchronous, and are coupled by the synchronization module. The synchronization module (30) comprises: a transfer register (31) for storing data which is communicated between the two circuit modules, a control circuit (32) for controlling the register in response to a respective timing signal (St1, St2) from the first and the second circuit module, the control circuit comprising a control chain for generating a control signal (CR) for the transfer register (31). The control chain includes at least: a repeater (34) for inducing changes in the value of the control signal, at least one edge sensitive element (35) for delaying a change in the signal value until a transition in a selected one of the timing signals is detected.

Abstract: The invention relates to an embedded system, and in particular, to an embedded system capable of compensating setup time violation. An embedded system comprises a serial flash and an access circuit. The serial flash further comprises an input pin and an output pin. The access circuit further comprises a processor, a shift register, a serial flash controller, and a time compensator. The input pin receives an adjusted input signal and the output pin sends an output signal. The processor controls the operation of the access circuit. The serial flash controller enables an operational clock of the access circuit. The time compensator compensates a timing of the output signal by referring to the operational clock. The shift register converts data in parallel form to serial form.

Abstract: Serializing circuitry is provided that can multiplex multiple device output signals and that can drive time-multiplexed data signals on the bus wires of a data path of an electronic system. Bus registers placed at the ends of the bus wires can register or buffer the data signals transmitted over the bus wires. The registered signals may be passed on to deserializing circuitry for demultiplexing the data signals to provide parallel device input signals. The bus registers and the serializing/deserializing circuitry can be provided along signal paths that require additional latency.

Abstract: A memory card includes a clock I/O circuit, a data I/O circuit, a delay element, and an adjustment value holding circuit. The clock input/output circuit receives a first clock from a host apparatus. The data I/O circuit receives a second clock from the host apparatus in a write timing adjustment mode. The data I/O circuit transmits and receives data to and from the host apparatus in a data transfer mode. In the write timing adjustment mode, the delay element adjusts a phase of the second clock in accordance with the first clock so as to receive the data received in the data transfer mode in response to the first clock. The adjustment value holding circuit holds an adjustment value for the phase of the second clock adjusted. In the data transfer mode, the delay element adjusts a phase of the data in accordance with the adjustment value.

Abstract: A fault tolerant computer comprises a first unit, a second unit, a delay buffer and a delay time setting unit. The first unit executes a computer program in response to an input signal. The second unit executes the computer program in the same execution environment as the first unit in response to the input signal. The delay buffer controls a delay time of a timing when the input signal is input to the first unit with respect to a timing when the input signal is input to the second unit. The delay time setting unit sets the delay time to zero when receiving a synchronization mode signal and sets the delay time to be larger than zero when receiving a delay mode signal.

Abstract: In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.

Abstract: A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the memory. The adaptive timing system captures data in a data valid window (DVW) in a data signal. In one embodiment, the adaptive timing system comprises a delay circuit for sampling the data signal at a midpoint of the DVW. The adaptive timing system may also comprise an identifying circuit for identifying whether the midpoint of the DVW corresponds to an actual midpoint of the DVW and adjusting the delay circuit accordingly.

Abstract: The present invention relates to an event driven digital signal processor 1 comprising: a central arithmetical unit 5, a register 4, a controller 3, an instruction memory 2, and input/output devices. The instruction memory 2 is arranged to include time performance constraints and events. An event control unit 6 is arranged to recognize an event and to control processing to be carried out as a consequence of the event while fulfilling the time performance constraints. The controller 3 is arranged to suspend processing of the time performance constraints after initiating operations in the event control unit 6. The controller 3 resumes processing when advised by the event control unit 6.

Abstract: A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver.

Abstract: The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clock. This is achieved by adding logic sensing when a DRAM device will not imminently be called upon to output data and when the device has stabilized. Waiting for the DLL delay interval to stabilize before locking the delay interval still allows the DLL to immediately and effectively resume operations when the DLL is needed to synchronize the output of the DRAM device with the system clock. The DLL delay interval can be locked, together with the DLL clock, after the DRAM device is deselected by the chip select control line, after a number of no operation commands have been received, and/or after any command issued to the DRAM device has been completed.