Abstract: The present invention relates to an apparatus and method for throttling a clock of a bus used for data exchange between devices in a computer such as a portable computer or notebook. Methods according to the invention can set a throttle rate of a clock to a predetermined initial value, detect a current remaining battery capacity or a current load to the CPU, and adjust the set throttle rate to a prescribed or calculated value according to the detected remaining battery capacity or the CPU load. Thus, power consumption is reduced, and, in the case of a battery-powered computer, battery life and operating time are extended.

Abstract: A method and apparatus for adjusting clock skew involves using a plurality of oscillators distributed across the apparatus where at least one of the plurality of oscillators has a frequency dependent on a characteristic of the apparatus. A processor is arranged to adjust a bias generator dependent on the frequency. The bias generator is arranged to adjust a delay through a tunable buffer. The tunable buffer is arranged to propagate a clock signal dependent on the adjustment of the delay through the tunable buffer dependent on the bias generator.

Abstract: An image processing apparatus including an image processing circuit, a frequency dispersion circuit, and a timing signal generator. The image processing circuit processes an image signal, and the frequency dispersion circuit performs frequency dispersion relative to a reference clock signal by continuously modulating an oscillating frequency of the reference clock signal in a predetermined modulation cycle and to generate a frequency dispersion clock signal. The timing signal generator generates a timing signal that controls an operation of the image processing circuit using the frequency dispersion clock signal, in synchronism with the predetermined modulation cycle used for the frequency dispersion.

Abstract: An apparatus for generating a second signal having a clock based on a second clock from a first signal with a first clock comprises first and second means for sampling the first signal to determine whether the first signal has a predetermined logic state, wherein first means samples the first signal with the second clock, and second means samples the first signal with a clock phase shifted to the second clock. Means for generating the second signal generates the second signal based on the second clock if it has been determined by at least one means for sampling that the first signal has the predetermined state. Especially for time critical applications, such as a DDR-RAM, a valuable latency saving is provided by the present invention.

Abstract: A network synchronization method allows reduced frequency fluctuations due to synchronization control in a network. Each node connected to the network has time information individually varying in a period of T. A time master node periodically notifies its own time information to time slave devices. Each time slave node prepares update-possible time points having a period of T/N (N>1). When receiving master time information, each time slave node updates its own time information using the master time information at an update-possible time point just after the master time information has been received.

Abstract: Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register.

Abstract: A method and apparatus for using different timings to latch signals sent by two memory devices of identical design to compensate for differences in the lengths of conductors across which the signals must propagate.

Abstract: An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the aid of the reference clock, the transmission clock of the output unit of the transmitting logic/memory component is generated, such that transmitted signals arrive in a receiving unit of the receiving component synchronously with the internal clock signal of that component.

Abstract: According to some embodiments, a potential clock signal is selected based on a comparison between a selected first clock signal and a second clock signal.

Abstract: Interconnect logic performs a transaction on an interconnect. The transaction may include multiple phases and the interconnect logic may include a counter state machine coupled to an interconnect state machine. The counter state machine may assert a signal to the interconnect state machine that may cause the interconnect state machine to prolong one or more phases of the transaction.

Abstract: In a memory system having a memory controller 20 and at least one DRAM 30, the memory controller 20 receives a continuous and alternate inversion signal as a pseudo clock signal from the DRAM 30, and generates an internal reception clock signal for a DQ signal on the basis of the continuous and alternate inversion signal and a base clock signal. Then, the memory controller 20 counts the number of the receiving internal clocks from the moment an OUT1 command is issued to the DRAM 30 until a high-level data signal is received as the DQ data signal from the DRAM 30, and retains the count result as the number of delay clocks. Thus, the memory controller 20 can receive read data (DQ signal) on the basis of the internal reception clock signal when time equivalent to the number of the delay clocks passes after the read command is issued.

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Abstract: A method for multi-bit de-skewing of parallel bus signals is disclosed. The method includes receiving data comprising a multi-bit word and a training pattern. After a first control word of the training pattern is detected, the number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of a parallel bus is calculated. The number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of the parallel bus is transmitted to a bit delay line. The system then outputs a de-skewed data word.

Abstract: A first feature of a data processing system is in that, in a data transfer path including a plurality of signal lines used for data transfer, a phase control is performed independently for each of the signal lines. A second feature is in that data is selectively transferred from a coupling exchange to a signal processor or a signal memory. A third feature is in that the signal processor, the signal memory and the coupling exchange are coupled to each other. By the features, the phase margin in the transfer data and clocks is widened and high speed transfer can be realized. Since data can be directly written in the signal memory, the signal processor can be efficiently used. Further, efficiency in processing and transfer of signals is improved.

Abstract: As provided, a system and method for automatically correcting timers to improve timing accuracy. The system and method provides for the use of inexpensive low tolerance resonators or oscillators that meet the internal timing specifications of applications of isochronous I/O over Profibus. Accordingly, the specified error rate (jitter) to appropriately maintain I/O is met efficiently and at low cost.

Abstract: Techniques to determine and indicate the extent to which transitions of an input signal deviate from a desired transition region. In an implementation, an indication may be provided when a transition of an input signal occurs within the desired transition region and an indication may be provided when a transition of an input signal occurs outside the desired transition reagion. In an implementation, a difference between a number of times when input signal transitions occur inside and outside of the desired transition region may be provided. Accordingly, a receiver of the input signal may decide whether to ignore or use the input signal based on the difference between a number of times when input signal transitions occur inside and outside of the desired transition region.

Abstract: An object of the present invention is to provide a programmable logic device capable of exchanging information with a logic constitution connected to a control processor and operating synchronously with a standard clock. The present invention comprises a control processor operating according to a high speed clock obtained by multiplying a standard clock, an input unit for inputting signal information into the control processor, and an output unit for outputting the signal information of the control processor as a signal, and characterized in that while the control processor is executing a plurality of processings according to the high speed clock, control is determined according to a value of the signal captured by the input unit synchronously with the standard clock within one cycle and a value of the output unit is changed by the control.

Abstract: A signal-aligning circuit includes a phase-adjusting circuit, a first control circuit, a second control circuit, and a tuning circuit. The first control circuit outputs a first voltage signal reflecting a phase difference between a first input signal (reference signal) and a second input signal (adjusted signal) and having a static phase offset due to asymmetries in the first control circuit. The second control circuit is a replica of the first control circuit, and receives the reference signal at two inputs thereof and outputs a second voltage signal reflecting the same static phase offset. The tuning circuit compares the first and second voltage signals and tunes a bias current in the first and second control circuits, whereby the static phase offsets of the first and the second control circuits becomes zero when the adjusted signal is phase-aligned with the reference signal in the steady state.

Abstract: An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.

Abstract: A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.

Abstract: A signal phase shifting circuit shifts the phase of an input signal, such as a STROBE signal, based on a reference signal, such as a CLOCK signal, to facilitate, for example, receiving of double data rate data. The signal phase shifting circuit includes a reference signal period dividing circuit having a feedback delay matching array operatively coupled to one of a plurality of voltage control delay lines. This signal phase shifting circuit also includes a variable delay circuit that provides a phase shifted output signal, such as a phase shifted STROBE signal, that includes a delay stage in a phase shifted output signal drive buffer coupled to the delay stage, such as a voltage control delay line. The feedback delay matching array includes a plurality of serially coupled buffer stages operatively coupled to compensate for delay variations associated with the phase shifted output signal drive buffer in the variable delay circuit.

Abstract: The preferred embodiments of the present invention are directed to the selective phase lag and time delay of clock signals within a computer system to compensate for additional parasitic capacitance that may be added to that system because of its open architecture. More particularly, the preferred embodiments are directed to clock signal path circuits where each circuit has multiple signal paths of varying lengths. By allowing the clock signals to propagate along a particular path, phase lag or time delay is added to those clock signals. Selection of a particular path for the clock signal is made by activating electrically controlled switches which themselves are activated or deactivated by software programs that run during power-up of the computer system that determine required phase lag or time delay of those clock signals as a function of parasitic capacitance in the computer system.

Abstract: A control device and a method for controlling and/or regulating the operational sequences in a motor vehicle, and a method for starting such a control device, which provide a program in a storage medium of the control device that is able to be executed independently of the frequency of the CPU, which allows the pulse frequency of the CPU to be checked and employs measures for reprogramming the program to be initiated. During starting or operation of the control device, the frequency of the CPU is checked first or the frequency of the CPU is compared to the frequency expected in the program. If necessary, measures for reprogramming the program are subsequently initiated.

Abstract: A PWM control circuit, microcomputer and electronic equipment which can generate high-resolution PWM signals through a small-sized scale of circuit. The PWM control circuit includes a PWM period value setting register, a counter, an edge-point value setting register, a PWM output circuit for varying the level of the PWM signal at a first edge-point, and a delay value setting register provided on low order side of the edge-point value setting register, for specifying a delay time of the first edge-point. The PWM output circuit delays the first edge-point by a period smaller than one clock period of CLK, in accordance with the value in the delay value setting register. This can improve the resolution of the PWM signal. One-bit or two-bit value is stored in the delay value setting register. Based on the stored value, the first edge-point can be delayed by ½, ¼, 2/4 or ¾ clock period.

Abstract: A method for synchronizing a data exchange between a data source and a control device is provided. A synchronization request signal is first transmitted via the bus system to the data source, which then measures a signal propagation time from the control device to the data source. In the data source, a transmission delay time is set which is dependent on the measured signal propagation time. Data which are to be transmitted are delayed by the transmission delay time. A bus system for synchronizing a data exchange is also provided. After receiving a synchronization request signal, the data source measures signal propagation times and sets a transmission delay time in a transmission delay device on the basis of the measured signal propagation times.

Abstract: According to one aspect of the invention, a method is provided in which a plurality of data signals are transmitted in parallel mode via a parallel bus from a first device to a second device. Phase information of each data signal received at the second device is detected against a corresponding clock signal. The phase information is sent from the second device to the first device. At the first device, an output delay of each data signal is adjusted based on the phase information received from the second device.

Abstract: The system and method generates two clock signals, one with a 2 ns delay with respect to the other, from a single PLL to enable a RGMII.

Abstract: A network system includes a network having a network bus, such as unshielded differential twisted-pair wires, electrically connected to a plurality of remote devices, and a network controller for digitally directing transmissions with the remote devices via the network bus. The network system also includes a plurality of network device interface elements adapted to interconnect the network controller with respective remote devices via the network bus. Each network device interface element includes a local oscillator, and is capable of transmitting and receiving messages via the network bus. To at least partially limit electromagnetic emissions from the local oscillator, each network device interface element further includes a spread-spectrum clock. And to further aid in limiting electromagnetic emissions, each network device interface element can further include a suppression assembly.

Abstract: An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

Abstract: A memory control chip, control method and control circuit. Instead of accessing a plurality of memory modules in a memory bank by referencing the same clocking signal, each memory module references a clocking signal having the same frequency but a slightly different preset phase so that the data within each memory module is accessed at a slightly different time. Ultimately, simultaneous switch output noise is greatly reduced and fewer power/ground pins are required in a package.

Abstract: A method for selectively deskewing data traveling through a bus in a network device is disclosed. Bit-level data is received from each data line of a plurality of data lines of the bus. Vertical line information is detected for the plurality of data lines to determine if there is a match with a training pattern. A skew distance is calculated once there is a match with the training pattern. Then, the plurality of data lines are bit aligned based on the skew distance.

Abstract: Apparatus for recovering timing of data input to a receiver, the apparatus consisting of an interpolator which receives the input data and generates interpolated-data in response to an interpolation coefficient, and a feed-forward equalizer having at least three taps. Each tap consists of a multiplier which is coupled to multiply a respective input sample by a respective adaptive equalization coefficient. The taps are arranged in sequence so that the input sample to each of the taps, except to a first tap in the sequence, is delayed relative to a preceding tap in the sequence. The equalizer receives and equalizes the interpolated-data so as to generate equalized-data from the interpolated-data. The apparatus also includes a timing sensor which adjusts the interpolation coefficient responsive a third adaptive equalization coefficient comprised in the equalization coefficients.

Abstract: Method and apparatus for providing a measure of jitter and skew of a clock signal is described. The clock signal may be used as an input to a digital circuit. In one embodiment, a digital delay circuit is used in conjunction with a processing circuit to continuously measure the jitter of an input clock signal, thus providing clock signal performance measurement over time. In another embodiment, a pair of digital delay circuits are used to continuously measure the skew or delay between a reference clock signal and a input clock signal, thus providing a measurement of the skew of the input clock signal over time. The digital delay circuit(s) are formed on-chip, and thus an on-chip determination of jitter or skew may be provided.

Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the signal “READ” is logically combined with the primary clock signal “CLK” in a control circuit of a modified glitch latch such that the glitch latch will only reset, and therefore a reset edge or “glitch” will only appear, when new data is read and the signal IN will return to zero and allow the modified glitch latch to recover.

Abstract: A clock data recovery system is provided for resampling a clock signal according to an incoming data signal stream. It comprises a clock generator for generating said clock signal wherein one of the frequency and phase of that clock signal is dependent upon a control signal. It is further provided a phase detector operable to detect the phase difference between said clock signal and said incoming data signal stream and is operable to generate a phase difference signal. A loop controller has a variable-gain and is operable to control said clock generator by generating said control signal. That control signal is dependent in said phase difference signal and that variable-gain. The variable-gain is dependent upon a transition rate of the incoming data signal stream. The loop controller can comprise a low-pass filter to generate from the phase difference signal a low-pass filered phase signal and to adjust the bandwidth of the clock data recovery system.

Abstract: A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates signals in response to receiving clock signals from a clock source. A second timer detects the presence or absence of signals from the first timer and in response to an absence outputs a circuit reset signal to a circuit. The circuit in turn issues a reset signal to the PLL and to other systems.

Abstract: A delay element is coupled to a first interface, which is coupled to a second interface via interconnect. Traces in the interconnect for propagating output signals from the first interface to the second interface have varying lengths. In order to reduce undesirable effects resulting from simultaneously switching the output signals, the delay element programmably and selectably delays the output signals according to the lengths of the traces they respectively travel to the second interface. Additionally, the effect of varying lengths of interconnect on receiver timings can be accommodated by using the delay element to programmably and selectably sample data at a receiver interface.

Abstract: During decoding and processing of program clock reference (PCR) values in MPEG-2 transport streams, a first initial difference value is obtained by calculating a difference between a first detected PCR value and a system time clock (STC) value generated when the first PCR value is detected. Depending on the update status of the PCR values, a second initial difference value is obtained by calculating a difference between a second detected PCR value and a STC value generated when the second PCR value is detected. Thereafter, a composite difference value is obtained by further calculating a difference between the first initial difference value and the second initial difference value. Subsequently, the first and second initial difference values, and the composite difference values are calculated for a predetermined number of detected PCR values so that the decoder clock signal is generated and maintained at approximately the same frequency as an encoder clock signal.

Abstract: A method for supplying a data signal read from a memory to an internal circuit of a semiconductor integrated circuit is described. First, supply timing information determining supply timing of the data signal provided to the internal circuit is generated using the data signal read from the memory. Then, the data signal read from the memory is supplied to the internal circuit in accordance with the supply timing information, so that data is provided at proper timing even if surrounding environment or a clock frequency is changed.

Abstract: A scheme for multi-frequency at-speed logic Built-In Self Test (BIST) is provided. This scheme allows at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. The scheme is also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. Scanable memory elements of the digital circuit are connected to define plurality of scan chains. The loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. The BIST controller, Pseudo-Random Pattern Generator (PRPG) and Multi-input Signature Register (MISR) work at slower frequency than the fastest clock domain. After loading of a new test pattern, a clock suppression circuit allows a scan enable signal to propagate for more that one clock cycle before multiple capture clock is applied.

Abstract: An apparatus comprising a circuit that may be configured to (i) change a frequency of one or more first signals in response to a second signal and (ii) generate a third signal in response to either the second signal or a predetermined time period expiring.

Abstract: A method and apparatus are disclosed for adjusting the individual data hold time of data output buffers. Clock signals for the output buffers are respectively and individually adjusted for each of the output buffers to ensure a desired timing relationship among all of the data output by the buffers.

Abstract: A interface, which connects memory and an integrated circuit, having a write path and read path that allow synchronous data propagation is provided. Further, a method for synchronizing data propagation through a read path and a write path of an interface is provided. The interface uses clock signals and paths based on a clock signal to synchronize the flow of data through various paths within the interface.

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract: A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The link bus protocol establishes a method in which data receiving circuitry of a target device can be put into a known state during a final stage of a source strobe event such as e.g., a data transfer. Once in the known state, the source strobes are stopped on the link bus. The target device uses internal logic clocked by a system clock rather than the source strobe to continuously sample the state of the receiving circuitry to see if the state has deviated from the known state. A change detect circuit determines if the receiving circuitry has deviated from the known state and if so, detects a new source strobe event. The change detect circuit detects the new event in the less stringent clock domain, which allows greater control of the skew and asymmetry of the source strobe.

Abstract: A method is provided to reduce clock skew in an integrated circuit having a number of circuit blocks, which comprises the following steps. A first source clock coupled to a clock input terminal of a first circuit block within the circuit blocks is provided, as is a second source clock coupled to a clock input terminal of a second circuit block within the circuit blocks. When the second circuit block is configured to operate in synchronization with the first circuit block, the clock input terminal of the second circuit block is switched to the first source clock, and thus both the first circuit block and the second circuit block can operate in accordance with the same first source clock.

Abstract: A programmable skew clock signal generator has a frequency generator circuit (104) consistent with the invention produces an output signal F?0 from a reference signal Fref A frequency accumulator (132, 152) is preloaded with a preload value PK1 and receives one reference signal cycle as a clock signal, receives a constant K1 as an input thereto, with the frequency accumulator (132, 152) having a maximum count KMAX and producing an overflow output. A phase accumulator (136, 156) is preloaded with a preload value PC1 and receives one overflow cycle output from the frequency accumulator (132, 152) as a clock signal and receives a phase offset constant C1 as an input thereto. The phase accumulator (136, 156) has a maximum count CMAX and produces a phase accumulator (136, 156) output. A delay line (320) is clocked by the reference signal Fref and produces a plurality of delayed reference clock signals at a plurality of tap outputs.

Abstract: A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier which is distributed on low impedance interconnection transmission lines. The PSK modulation contains the digital data while the carrier itself constitutes the clock signal, and the clock signal and digital data are transmitted in a synchronous manner. The carrier frequency may be near fT, the maximum operation frequency of the transistors. Since the digital data and clock signal are simulaneously transmitted on the same interconnection, the digital data never becomes skewed with respect to the clock signal, or vice versa.

Abstract: A method, computer program product, and data processing system for estimating and correcting the amount of clock skew in end-to-end network timing measurements is disclosed. Measured delays are combined with their time of measurement to create ordered pairs. These ordered pairs represent points within a Cartesian plane. The convex hull of these points is determined, and an optimal line segment from the resulting polygon is selected and extrapolated to create an affine function estimating clock skew over time. The optimal line segment of the polygon is one that optimizes a selected objective function. The objective function is selected so as to be an appropriate measurement of the accuracy of the resulting linear function as an estimate of the actual clock skew.

Abstract: A circuit for generating a pulse with minimal delay after receiving a trigger signal includes a passgate, a gating circuit, and a reset circuit. The passgate is enabled by control signals received at the gating circuit having a trigger signal as one of the control signals. The trigger signal is also presented as an input to the passgate. When enabled, the passgate propagates the trigger signal to an output. A predetermined time after the trigger signal appears at the passgate input, a passgate control signal is turned off, thereby preventing the trigger signal from further passing through the passgate. The reset circuit is then turned on, which pulls the signal at the output of the passgate to a reference voltage, ending the pulse. Once the pulse is generated, it can be rectified and further combined with other signals to produce signals used in other parts of the circuit.