Correction For Skew, Phase, Or Rate Patents (Class 713/503)
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Patent number: 7315956Abstract: A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for executing timing-sensitive instructions. The timing and event processor includes a plurality of instruction sequencers for executing timing-sensitive instruction threads and a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.Type: GrantFiled: August 29, 2002Date of Patent: January 1, 2008Assignee: Analog Devices, Inc.Inventors: Poul R. Jensen, deceased, Thorkild Leth Moller, legal representative, Morten Nielsen, Mogens Christiansen
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Patent number: 7308381Abstract: Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial circuit is obtained from a first statistical timing characteristic of signal paths included in the extracted partial circuit. Next, timing verification for the integrated circuit is performed using the second statistical timing characteristics corresponding to the respective statistical clock skews.Type: GrantFiled: July 31, 2006Date of Patent: December 11, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hirokazu Yonezawa
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Patent number: 7302601Abstract: A device is provided for synchronizing, on a reference clock signal, an exchange of data with a remote member. The device includes a main variable delay line controlled by a first processing unit coupled to a phase comparator in order to generate a delayed clock signal transmitted to the remote member. One input of the main variable delay line receives the reference clock signal.Type: GrantFiled: April 2, 2003Date of Patent: November 27, 2007Assignee: STMicroelectronics S.A.Inventors: Nicolas Graciannette, Benoit Marchand
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Patent number: 7296175Abstract: A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.Type: GrantFiled: October 22, 2004Date of Patent: November 13, 2007Assignee: International Business Machines CorporationInventors: Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard Charles Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius, Barry Joe Wolford
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Patent number: 7296104Abstract: A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.Type: GrantFiled: September 12, 2005Date of Patent: November 13, 2007Assignee: Sun Microsystems, Inc.Inventors: Brian L. Smith, Jue Wu, Jyh-Ming Jong, Wai Fong, Leo Yuan, Prabhansu Chakrabarti
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Patent number: 7287176Abstract: An apparatus, a method and a storage medium for carrying out a deskew among multiple lanes for use in a division transmission of large-capacity data.Type: GrantFiled: May 23, 2003Date of Patent: October 23, 2007Assignee: Electronics and Telecommunications Research InstituteInventors: Dae Up Kim, Sung Soo Kang, Hae Won Jung, Hyeong Ho Lee
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Patent number: 7284143Abstract: In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first output clock signal based on the received divided input clock signal and the received non-divided input clock signal, the first output signal being associated with a first delay. The method further includes, at a delay line, receiving the non-divided input signal, delaying the non-divided input signal for a time substantially equivalent to the first delay, and generating a second output clock signal associated with a second delay substantially equal to the first delay.Type: GrantFiled: December 29, 2003Date of Patent: October 16, 2007Assignee: Texas Instruments IncorporatedInventors: James S. Song, Achuta R. Thippana, Minh G. Chau
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Patent number: 7277969Abstract: On the basis of a period of a timing signal, a signal propagation delay in a device unit, signal propagation delay in the timing signal bus and the data bus, and a setup time of another device unit or a device connected to the data bus, a timing at which noise caused by active connection of the first device to the data bus is propagated to the other device unit or the device is computed in a step of noise propagation computing, and on the basis of the timing computed in the step of noise propagation computing, a connection timing at which the first device unit is connected to the data bus. With thes two steps, a noise caused by active connection of a device unit does not affect other device units and devices connected to the same data bus.Type: GrantFiled: December 27, 2005Date of Patent: October 2, 2007Assignee: Fujitsu LimitedInventor: Ryohei Nishimiya
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Patent number: 7278047Abstract: A method for operating a device (such as a printer) having a first interface (such as USB interface) connectable to a first computer and a second interface (such as an Ethernet interface) connectable to a second computer. A phase lock loop (PLL) circuit is obtained which is driven by a clock source, which is adapted for switching between operating at the first and second clock frequencies, and which is operatively connected to the first and second interfaces to provide a clock signal to the first and second interfaces. The PLL circuit is operated at the first clock frequency when the first interface is active and is operated at the second clock frequency when the second interface is active. A device includes the first and second interfaces, the PLL circuit, and the clock source.Type: GrantFiled: October 14, 2002Date of Patent: October 2, 2007Assignee: Lexmark International, Inc.Inventors: John W. Douglas, Darrel L. Henry, Samuel W. Gardiner, Jimmy D. Moore, Jr., Duane E. Norris
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Patent number: 7278069Abstract: A data transmission apparatus and method employing the phase noise characteristics within the receiving registers to measure and control the characteristics of the channel as a function of the data pattern and to compensate for production tolerances within the channel by altering the timing characteristics of the signal at either the transmitter or receiver as a function of the data. Time offsets between different signals that form the communication channel are measured for different frequencies and/or for different data patterns transmitted through the channel and stored to compensate for an inter-signal skew by performing relative alignment of the measured offsets to a main clock edge.Type: GrantFiled: April 30, 2003Date of Patent: October 2, 2007Inventors: Igor Anatolievich Abrosimov, Vasily Grigorievich Atyunin, Alexander Roger Deas, Ilya Vasilievich Klotchkov
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Patent number: 7275171Abstract: A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the process of phase alignment to allow great flexibility in allowable combinations of slower clock and faster clock frequencies. In one embodiment, an encoded edge select word is generated once at system initialization and used thereafter to select edges of the faster clock on which to sample data that comes from the clock domain of the slower clock. The value of the encoded edge select word is based, in part, on the fixed relationship between the faster clock and the slower clock.Type: GrantFiled: May 22, 2003Date of Patent: September 25, 2007Assignee: Rambus Inc.Inventors: Jade M. Kizer, Benedict C. Lau, Bradley A. May
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Patent number: 7275174Abstract: A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26) The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.Type: GrantFiled: August 22, 2006Date of Patent: September 25, 2007Assignee: Raytheon CompanyInventors: Frank Nam Go Cheung, Richard Chin
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Publication number: 20070220297Abstract: A method and a system of sharing of a clock by an electronic circuit between at least one first task clocked by at least one first counter and at least one second task clocked by a second counter, the two counters varying at the rate of said clock, the content of the first counter plus or minus an offset value being, on each execution of the second task, assigned to the second counter.Type: ApplicationFiled: February 14, 2007Publication date: September 20, 2007Applicant: STMicroelectronics S.A.Inventors: William Orlando, Stephan Courcambeck
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Patent number: 7272741Abstract: Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.Type: GrantFiled: June 2, 2004Date of Patent: September 18, 2007Assignee: Intel CorporationInventors: Jeffrey R. Wilcox, Shivnandan Kaushik, Stephen H. Gunther, Devadatta V. Bodas, Siva Ramakrishnan, David Poisner, Bernard J. Lint, Lance E. Hacking
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Patent number: 7272742Abstract: A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffered clock signal and generates a delayed clock signal, and an output circuit including output signal paths for outputting the output signals synchronously with the system clock signal by using the delayed clock signal. At least one of the output signal paths includes a delay circuit and an output buffer. Each delay circuit provides a programmable delay to the delayed clock signal to generate a unique delayed clock signal used to clock an output signal into the respective output buffer. By programming the delays based upon output skew, the output skew can be improved.Type: GrantFiled: August 31, 2004Date of Patent: September 18, 2007Assignee: Micron Technology, Inc.Inventors: Aaron M. Schoenfeld, Vladimir Mikhalev
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Patent number: 7272743Abstract: A circuit according to an embodiment of the present invention comprises a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a PLL circuit which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at an end point of the first clock distribution network, to a start point of the first clock distribution network, and a PLL circuit which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at an end point of the second clock distribution network, to a start point of the second clock distribution network.Type: GrantFiled: September 7, 2004Date of Patent: September 18, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Kohei Oikawa
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Patent number: 7269672Abstract: A design method for a bus system comprising a noise propagation computation step and a connection timing computation step. Based on the cycle of a timing signal, a signal propagation delay in a device unit, signal propagation delays in a timing-signal bus and a data bus, and a setup time in the device unit or device connected on the data bus, the noise propagation computation step computes timing at which, when the device unit is connected on the data bus being active, noise propagates to other device units other than the connected device unit or to the device connected on the data bus. Based on the timing computed in the noise propagation computation step, the connection timing computation step computes connection timing at which the device unit is connected on the data bus.Type: GrantFiled: February 13, 2004Date of Patent: September 11, 2007Assignee: Fujitsu LimitedInventor: Ryohei Nishimiya
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Patent number: 7269754Abstract: A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.Type: GrantFiled: December 30, 2002Date of Patent: September 11, 2007Assignee: Intel CorporationInventors: Sridhar Ramaswamy, Amit Bodas, Zohar B. Bogin, David E. Freker, Suryaprasad R. Kareenahalli
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Patent number: 7260736Abstract: A device and method to detect and correct for clock duty cycle skew in a high performance microprocessor having a very high frequency clock. The device includes a delay chain circuit to delay the clock signal and to determine the presence of clock duty cycle skew. The device uses simple latches, flops, and phase-detectors to compare and identify the nature of the clock duty cycle skew. Simple logic is employed to measure and determine the amount and direction of de-skew to apply to the clock signal. After the de-skew operation, the clock duty cycle cycles used to control the execution of the microprocessor are of a more uniform time duration.Type: GrantFiled: November 19, 2003Date of Patent: August 21, 2007Assignee: Intel CorporationInventor: Binglong Zhang
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Patent number: 7257727Abstract: Systems and methods are disclosed for timer architectures. For example, in accordance with an embodiment of the present invention, a timer system includes a prescaler and one or more timer cells each having a multiplexer and a counter.Type: GrantFiled: March 4, 2004Date of Patent: August 14, 2007Assignee: Lattice Semiconductor CorporationInventor: Edward A. Ramsden
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Patent number: 7257169Abstract: A receiver for deserializing a stream of data bits, including a single clock which is adapted to generate a first plurality of clock phases, and a sample generator which is adapted to sample the stream so as to generate initial data values of each of the bits at times defined by the first plurality of clock phases. The receiver further includes digital circuitry which is adapted to group the initial values into a second plurality of sampling phase sets, according to the clock phases at which the values were sampled, and assign each of the phase sets a respective grade in response to at least some of the initial values. The circuitry selects a decoding phase set from the phase sets in response to the respective grades, and decodes the stream in response to initial values of the decoding phase set to generate decoded values of the consecutive bits.Type: GrantFiled: December 16, 2002Date of Patent: August 14, 2007Assignee: Mysticom Ltd.Inventors: Boaz Shahar, Eyran Lida, Eyal Massad
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Patent number: 7249275Abstract: A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality of clock signals to the elements, and a control circuit for controlling the phase-locked loop to adjust the frequencies of the clock signals, so as to execute the overclocking operations on the elements, respectively. The method includes the steps of: increasing the frequency of a first clock signal until one of the elements can't work normally due to an utmost frequency of the first clock signal; resetting all the elements and operating the element corresponding to the first signal according to a safe frequency of the first clock signal; and repeating the above steps to perform overclocking operation on each of the other elements.Type: GrantFiled: September 3, 2004Date of Patent: July 24, 2007Assignee: Realtek Semiconductor Corp.Inventors: Wen-Shiung Weng, Chi-Kung Kuan, Sheng-Kai Chen, Ming-Chun Chang, Yi-Shu Chang
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Patent number: 7249274Abstract: In some embodiments, a system and method for making a scalable clock gearing mechanism may allow multiple devices operating on different clock speeds to communicate. In an embodiment, a mechanism may be used to input data clocked on a first clock frequency and output the data on a second clock frequency. The mechanism may temporarily store the data until the next clock cycle of the second clock. Further, the mechanism may make use of multiple inputs or outputs to input or output multiple data units during a single clock cycle to keep the delay between the arrival and departure of the data small.Type: GrantFiled: December 30, 2003Date of Patent: July 24, 2007Assignee: Intel CorporationInventor: Darrell S. McGinnis
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Patent number: 7245686Abstract: Signal processing apparatus, including a circuit which processes signals received on multiple channels so as to extract therefrom at least first and second sequences of symbols, and a FIFO, which receives and stores at least one bit of each of the symbols in a first interval of the first sequence and a second interval of at least the second sequence, the second interval at least partially overlapping the first interval. The apparatus includes a predictor, which determines, for each of the symbols in the first interval of the first sequence an expected value of the at least one bit in a corresponding one of the second symbols in the second interval, and logic, which compares the expected value with the at least one bit of each of the second symbols in the FIFO, so as to determine a relative skew between the first and at least the second channel.Type: GrantFiled: December 16, 2002Date of Patent: July 17, 2007Assignee: Mysticom Ltd.Inventors: Rami Weiss, Baruch Bublil, Israel Greiss
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Patent number: 7245684Abstract: A system and method for compensating for skew in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. In a system embodiment, a phase detector is provided for detecting a phase between the first and second clock signals. A skew state detector disposed in communication with the phase detector is operable to generate a skew state signal which tracks a phase relationship between the clock signals. A synchronizer control signal generator responds to the skew state signal by generating at least one control signal to compensate for the skew between the first clock signal and the second clock signal.Type: GrantFiled: July 30, 2003Date of Patent: July 17, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventor: Richard W. Adkisson
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Patent number: 7243253Abstract: A method and apparatus for enabling repeated switching of a cross-connect and a timing source in a network element through the use of a phase adjuster. In one embodiment, a traffic card includes an aligner to adjust the occupancy of the data in two ingress FIFOs to synchronize their occupancy. In addition, the traffic card includes a clock control logic, including a phase adjuster, to adjust the phase of clock signals driving the two ingress FIFOs to avoid an underflow or overflow.Type: GrantFiled: June 23, 2003Date of Patent: July 10, 2007Assignee: Redback Networks Inc.Inventors: Michael McClary, Sharath Narahari
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Patent number: 7242734Abstract: A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.Type: GrantFiled: June 18, 2003Date of Patent: July 10, 2007Assignee: Zarlink Semiconductor Inc.Inventors: Simon J. Skierszkan, Wenbao Wang
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Patent number: 7242257Abstract: The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides an auto-calibration system. The system includes: a plurality of delay line elements (DLEs) adapted to be connected in a loop; a state machine coupled to the plurality of DLEs and operative to provide state data for the plurality of DLEs; a start oscillation signal receiving circuit coupled to the loop and operative to trigger the loop in response to receipt of a start oscillation signal; and a calibration circuit coupled to the loop and operative to acquire calibration data for the plurality of DLEs.Type: GrantFiled: May 7, 2004Date of Patent: July 10, 2007Assignee: Credence Systems CorporationInventor: Ahmed Rashid Syed
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Patent number: 7239681Abstract: A system and method for maintaining a stable synchronization state in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain and second circuitry disposed in a second clock domain. In a system embodiment, a first circuit portion generates a load signal indicative of a known acceptable state for which a cycle can be loaded. A second circuit portion is in communication with the first circuit portion in order to generate a lock signal indicative of a tolerable tracked skew between a first clock signal of the first clock domain and a second clock signal of the second clock domain. A third circuit portion, responsive to the load signal, the lock signal and a zero skew point indicator, generates a synchronization stable state signal indicative of locking between the first clock signal and the second clock signal.Type: GrantFiled: July 30, 2003Date of Patent: July 3, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventor: Richard W. Adkisson
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Patent number: 7237136Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.Type: GrantFiled: January 20, 2004Date of Patent: June 26, 2007Assignee: Micron Technology, Inc.Inventors: Wen Li, Aaron Schoenfeld, R. Jacob Baker
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Patent number: 7234070Abstract: A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and a transmitter coupled to the downstream data bus. Similarly, each of the memory modules includes a receiver coupled to the downstream data bus and a transmitter coupled to the upstream data bus. Each receiver includes a receive clock generator that is synchronized by coupling a known pattern of data to the receiver. The receiver determines which phase of the receive clock best captures the known pattern and uses that receive clock phase during normal operation.Type: GrantFiled: October 27, 2003Date of Patent: June 19, 2007Assignee: Micron Technology, Inc.Inventor: Ralph James
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Patent number: 7234069Abstract: Circuits, methods, and apparatus that provide a precise phase shift for a read strobe or other signal. One embodiment provides a read strobe delay line including a series of delay elements, where inputs or outputs of at least some of delay elements are received by a multiplexer. One input of this multiplexer is selected as the read strobe signal. Further precision adjustment may be made in the delay of the read strobe signal by using a delay line in a reference delay-locked loop, where that delay line also includes a series of delay elements, and inputs or outputs of at least some of the delay elements are multiplexed.Type: GrantFiled: March 12, 2004Date of Patent: June 19, 2007Assignee: Altera CorporationInventor: Brian D. Johnson
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Patent number: 7231537Abstract: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.Type: GrantFiled: July 3, 2003Date of Patent: June 12, 2007Assignee: Micron Technology, Inc.Inventor: Dean Nobunaga
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Patent number: 7231536Abstract: Circuits, methods, and apparatus that prevent control signals from changing state while the control signals are being used to delay a read strobe signal. An exemplary embodiment of the present invention provides a control circuit that provides a plurality of control bits to a delay line, where the delay line delays or phase shifts a read strobe signal a duration, where the duration depends on the state of the control bits. The delayed read strobe signal is used to clock one or more data registers. To avoid undesired changes in the duration that the read strobe signal is delayed, the control bits are retimed before being provided to the delay line. A specific embodiment waits for an edge of the strobe signal to be output by the delay line before providing the control bits to the delay line. Another specific embodiment waits until no edge of the strobe signal is being delayed by the delay line before providing the control bits to the delay line.Type: GrantFiled: March 12, 2004Date of Patent: June 12, 2007Assignee: Altera CorporationInventors: Yan Chong, Chiakang Sung, Joseph Huang, Philip Pan
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Patent number: 7228451Abstract: A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.Type: GrantFiled: November 8, 2005Date of Patent: June 5, 2007Assignee: Altera CorporationInventors: Triet Nguyen, David Jefferson, Srinivas Reddy, Keone Streicher
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Patent number: 7224756Abstract: A clock generator system and method for providing and operating a codes with a clock signal at a desired operational rate are disclosed. The clock generator system also has a phase-locked loop circuit. The clock generator system determines whether an available clock signal within a circuit environment of the codec has a desired clock rate. If the available clock signal has the desired clock rate, the clock generator system supplies and operates the codec with the available clock signal. If the available clock signal does not have the desired clock rate, the phase-locked loop circuit generates from the available clock signal a desired clock signal having the desired clock rate and supplies and operates the codec with the desired clock signal.Type: GrantFiled: May 13, 2002Date of Patent: May 29, 2007Assignee: Cirrus Logic, Inc.Inventors: Krishnan Subramoniam, Jens Puchert, Anand Venkitachalam, Brian K. Straup, John L. Melanson
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Patent number: 7225354Abstract: A circuit and a method for aligning transmitted data by adjusting transmission timing for a plurality of lanes. The method includes utilizing different initial values to reset a count value corresponding to a lane when a plurality of COM symbols are detected on the lane, utilizing an increment value to increase the count value corresponding to the lane when a COM symbol is not detected on the lane, and utilizing a plurality of count values corresponding to the lanes to align transmitted data of the lanes when a COM symbol is not detected on the lanes within a predetermined period of time.Type: GrantFiled: June 30, 2004Date of Patent: May 29, 2007Assignee: VIA Technologies Inc.Inventor: Wayne Tseng
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Patent number: 7219250Abstract: A status indication detection apparatus comprises an input storage stage, an intermediate storage stage and an output storage stage. Status indications are input into the input register of the input stage and are shifted to the intermediate and to the output stage. The input and intermediate storage stages operate with a first reference clock in a first clock domain whilst the output storage stage operates with a different second reference clock in the second clock domain. In accordance with the invention a reading out of the intermediate register of the intermediate stage is only possible during the generation of a hold signal which keeps a current status indication in the intermediate storage stage and blocks a transfer of a new status indication from the input stage.Type: GrantFiled: July 3, 2002Date of Patent: May 15, 2007Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Maren Abendroth, legal representative, Hans-Ulrich Fleer, Torsten Abendroth, deceased
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Patent number: 7216279Abstract: An integrated circuit, where a hard macro is resident within the integrated circuit. The hard macro receives a clock signal at a frequency that is below the operational frequency of the integrated circuit, and produces a clock signal having a frequency that is at least equal to the operational frequency of the integrated circuit. The hard macro has a first input that receives a first signal from the tester. A second input receives a second signal from the tester, offset by substantially ninety degrees from the phase of the first signal. A speed select input receives a signal, where the signal is selectively set at one of a logical high indicating a first multiplier to be applied in the hard macro, and a logical low indicating a second multiplier to be applied in the hard macro. A clock multiplication circuit receives the first signal, selectively receives the second signal, and receives the speed select signal, and produces the clock signal.Type: GrantFiled: July 19, 2005Date of Patent: May 8, 2007Assignee: LSI Logic CorporationInventors: Kevin J. Gearhardt, Anita M. Ekren
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Patent number: 7216247Abstract: The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising edge of the read clock occurs during the second half of the write clock cycle. Responsive to this determination, the data written into the FIFO buffer element is shifted in order to reduce skew.Type: GrantFiled: August 5, 2004Date of Patent: May 8, 2007Assignee: Texas Instruments IncorporatedInventors: Keerthinarayan P. Heragu, Patrick Bosshart
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Patent number: 7216249Abstract: A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the S/N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.Type: GrantFiled: June 9, 2003Date of Patent: May 8, 2007Assignee: Rohm Co., Ltd.Inventors: Masayu Fujiwara, Masaki Onishi
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Patent number: 7216250Abstract: The present invention relates to a clock control circuit apparatus including a first oscillation circuit for generating a first clock signal and a second oscillation circuit for generating a second clock signal and capable of, when the two clock signals are put to use, improving the reliability of oscillation operations thereof. In the clock control circuit apparatus, a sub-clock correction unit corrects an oscillation frequency of a sub-clock signal on the basis of a main clock signal, while a main clock monitoring unit monitors an oscillation state of the main clock signal on the basis of the sub-clock signal.Type: GrantFiled: December 23, 2003Date of Patent: May 8, 2007Assignee: DENSO CorporationInventors: Toshihiko Matsuoka, Yoshinori Teshima, Shinichi Noda, Susumu Tsuruta, Hiroshi Fujii, Hideaki Ishihara
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Patent number: 7210050Abstract: A source synchronous scheme in which data from one clock domain is synchronized to a clock of a second clock domain. Using a more reliable clock of the second domain to control and adjust the alignment after the data is latched in allows more robust performance to maintain correctly ordered data. In this manner, a write pointer based on strobe signal(s) from the first clock domain may be avoided.Type: GrantFiled: August 30, 2002Date of Patent: April 24, 2007Assignee: Intel CorporationInventor: Sanjay Dabral
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Patent number: 7206239Abstract: Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using a selected internal clock signal, a clock signal with an optimal phase is obtained from among the plural internal clock signals having the different phases with one another, and a skew generated by being divided into the plural chips is adjusted automatically to thereby realize a proper operation of the circuits as a whole.Type: GrantFiled: October 28, 2005Date of Patent: April 17, 2007Assignee: Fujitsu LimitedInventors: Kazuhiko Kikuchi, Masaya Kitagawa, Jun Masuko
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Patent number: 7203611Abstract: There is provided a timing generator generating a timing signal of a predetermined period. The timing generator includes a set/reset latch, a set unit supplying the set signal, and a reset unit supplying the reset signal, in which the set unit includes: a first variable delay circuit that delays a given reference clock to output a first set signal; a second variable delay circuit that delays the given reference clock to output a second set signal having a phase different from the first set signal; an OR circuit that computes a logical sum of the first set signal and the second set signal to generate the set signal; and a third variable delay circuit that delays the set signal output from the OR circuit to adjust a skew between the set signal and the reset signal.Type: GrantFiled: August 4, 2005Date of Patent: April 10, 2007Assignee: Advantest CorporationInventor: Masaru Doi
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Patent number: 7203860Abstract: A clock recovery circuit has a phase comparator circuit, a phase adjusting circuit, and a duty cycle correction circuit. The phase comparator circuit carries out phase comparison between an input signal and an output signal, and outputs a phase control signal proportional to a phase difference between the input signal and the output signal. The phase adjusting circuit receives the phase control signal from the phase comparator circuit, adjusts the phase of the input signal, and produces the output signal, and the duty cycle correction circuit receives the output signal from the phase adjusting circuit, and corrects the duty cycle of the output signal.Type: GrantFiled: April 3, 2003Date of Patent: April 10, 2007Assignee: Fujitsu LimitedInventors: Hideki Ishida, Masaaki Kaneko
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Patent number: 7200769Abstract: Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.Type: GrantFiled: January 2, 2002Date of Patent: April 3, 2007Assignee: Altera CorporationInventors: Yan Chong, Chiakang Sung, Bonnie I. Wang, Joseph Huang, Xiaobao Wang, Philip Pan, Tzung-Chin Chang
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Patent number: 7194649Abstract: Several algorithms are provided to estimate and remove relative clock skews from delay measurements based on the computation of convex hulls. The algorithms are linear in the number of measurement points for the case with no clock resets. For the more challenging case with clock resets, i.e., the clocks are reset to some reference times during the measurement period, linear algorithms are provided to identify the clock resets and derive the best clock skew lines. The algorithms are also extended to environments in which at least one of the clocks is controlled by Network Time Protocol. These algorithms can also be extended for active clock synchronization to replace or further improve Network Time Protocol.Type: GrantFiled: May 29, 2002Date of Patent: March 20, 2007Assignee: International Business Machines CorporationInventors: Zhen Liu, Cathy Honghui Xia, Li Zhang
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Patent number: 7191353Abstract: A master device communicating a first range of speeds at which the master device is operable, to a first slave device, the master device and the first slave device determining a second range of speeds most closely matched to the first range of speeds at which each of the master device and the first slave device is respectively operable; and the master device setting the operating range of speeds of each of the master device and the first slave device to the second target range of speeds.Type: GrantFiled: March 31, 2003Date of Patent: March 13, 2007Assignee: Intel CorporationInventor: Laurance F. Wygant
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Patent number: 7190736Abstract: A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or system. The technique is based on the phase shift keying (PSK) modulation of an RF high frequency carrier which is distributed on low impedance interconnection transmission lines. The PSK modulation contains the digital data while the carrier itself constitutes the clock signal, and the clock signal and digital data are transmitted in a synchronous manner. The carrier frequency may be near fT, the maximum operation frequency of the transistors. Since the digital data and clock signal are simultaneously transmitted on the same interconnection, the digital data never becomes skewed with respect to the clock signal, or vice versa.Type: GrantFiled: October 5, 2005Date of Patent: March 13, 2007Assignee: Micron Technology, Inc.Inventor: Leonard Forbes