Abstract: Cycle-accurate real-time clocks and methods to operate the same are disclosed. An example real-time clock comprises a first counter to count cycles of a selectively-operable clock, a multiplexer to select from at least an output signal associated with the first counter or a continuously-operating clock, and a second counter to count cycles of an output signal of the multiplexer.

Abstract: A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

Abstract: Signal processing circuitry having parallel processing channels has clock-generation circuitry that generates (i) high-speed clock signals used to drive the channels and (ii) synchronization signals used to reset the processing of the channels. In one embodiment, the signal processing circuitry has multiple multiplexing channels arranged in one or more macrocells, each macrocell having one or more channels and a phase-locked loop (PLL) that generates a high-speed PLL clock signal and a synchronization signal for the macrocell's channels. Each channel has a counter that implements a state machine used to drive the multiplexing processing, where the state machine is reset to a specified state upon receipt of each synchronization pulse in the synchronization signal.

Abstract: Provided is a smart card for communicating with a host computer through a universal serial bus (USB). The smart card includes an internal clock signal generator to generate an internal clock signal, a period detector to detect a period of the internal clock signal and to generate a control code according to the detected period, and a transmission clock generator to generate a transmission clock signal which varies from the internal clock signal according to the control code. The smart card transfers data in sync with the transmission clock signal.

Abstract: A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a physical interface, a plurality of data line amplifiers, a clock line amplifier, a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module may be set based upon a training sequence received from a link partner. The training sequence may received during startup or reset, immediately after startup or reset completes, or may be received periodically during training intervals.

Abstract: To provide a system clock distributing apparatus and a system clock distributing method for reducing a skew of a system clock and a synchronizing signal at low cost. The system clock distributing apparatus for matching the timing of data by using the synchronizing signal includes an oscillator 1 that generates a periodical synchronizing signal and a PLL 2, a memory that stores the data, at least one CPU 13 that conducts a computing process using the data stored in the memory, at least one MAC 14 that controls an access from the CPU 13 to the memory, and at least one NB 12 that generates the system clock having a frequency that is an integral multiple of the synchronizing signal, and controls the CPU 13 and the MAC 14 based on the operation by the system clock.

Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Abstract: A method for optimizing signal operating parameters for a signal sent over a data transmission channel through a programmable logic device (PLD) is provided. A transmit test pattern is generated and is associated with a set of signal operating parameters for the transmission and receiving of the test pattern over a data transmission channel. The data transmission channel loops from a transmit port to a receive port of the PLD. A determination of whether the received test pattern matches the transmit test pattern is performed. The match results and the set of signal operating parameters are recorded. At least one of the signal operating parameters of the set of signal operating parameters is modified through a processor of the PLD. Another transmit pattern is transmitted and received according to the modified set of signal operating parameters and the results are recorded. Methods for optimizing data transfer into a PLD and corresponding apparatuses are included.

Abstract: Embodiments of the invention relate to distribution of clocks to CPUs in processing cells of a multi-cell system. In an embodiment, each cell includes an interface, referred to as an agent. A plurality of interfaces, referred to as switches, together with the agents of the cells, connects the cells together. A clock source provides a clock to a switch, which replicates the clock and provides the replicated clocks to its ports. Each port of the switch, receiving a replicated clock, encodes this replicated clock and sends it over a link to each agent of a cell. Each agent of the cells, receiving an encoded clock, decodes this encoded clock, resulting in a decoded, or an extracted, clock. The agent then replicates the extracted clock and provides the replicates of the extracted clock to a plurality of CPUs of the cell. As a result, CPUs in all cells of the system receive clocks that all are synchronized to the clock provided by the clock source.

Abstract: Disclosed is a method for calculating clock offset and skew between two clocks in a computer system. The method comprises the steps of sending data packets from a first processing unit in the computer system to a second processing unit in the computer system, and sending the data packets from the second processing unit to the first processing unit. First, second, third and fourth time stamps are provided to indicate, respectively, when the packets leave the first processing unit, arrive at the second processing unit, leave the second processing unit, and arrive at the first processing unit. The method comprises the further steps of defining a set of backward delay points using the fourth time stamps, and calculating a clock offset between clocks on the first and second processing units and clock skews of said clocks using said set of backward delay points.

Abstract: Apparatus for limiting an output signal frequency of an on-chip clock generator is presented. Electronic circuitry compares the value of a ratio between the internal clock signal frequency and the reference clock input signal frequency with minimum and maximum calibration word signals, in order to determine if the reference clock input signal frequency is within a permitted range. If the reference clock input signal frequency is not within the permitted range, the apparatus sends a tamper alert to the chip or to a system, and the output clock signal frequency is not changed according to the reference clock input signal frequency, thereby protecting the chip from erroneous or tampered clock signal. The output clock signal is buffered from the reference clock input signal insuring that the output clock signal frequency is within the permitted range. The apparatus can operate without providing the reference input clock signal.

Abstract: A circuit including a deskew circuit. The deskew circuit is configured to receive a first signal having a first edge delayed from a second edge of a second signal by a first delay and a third edge delayed from a fourth edge of the second signal by a second delay. The deskew circuit is configured to provide a third signal having a first deskewed edge delayed from the first edge by a third delay and a second deskewed edge delayed from the third edge by a fourth delay. The difference between the fourth delay and the third delay is substantially equal to the difference between the first delay and the second delay.

Abstract: Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.

Abstract: A programmable logic device has programmable phase-shifting circuitry. The phase-shifting circuitry is used to generate a set of skewed clock signals that is used to adjust the relative timing of device elements in a circuit synthesized in the programmable logic device. By suitably adjusting the relative timing of the device elements, the circuit critical path lengths are effectively reduced leading to improved circuit frequency performance. Algorithms are provided for establishing clock skew values that lead to improved circuit performance. The algorithms are incorporated in computer aided design tools to enable automatic optimization of circuit designs.

Abstract: Apparatus (100) for communicating clock correction data between two or more clocked entities (102, 104) using a standardized clock correction unit or quanta. A source-native pre-scaler (302) can convert source-native clock correction values to scaled source-native clock correction values. The pre-scaler can perform this conversion by multiplying each source-native clock correction value by a factor N1. A source-native divider (308) can divide an adjusted source-native clock correction value by a value M1 to produce a standard quotient and a standard remainder. The standard quotient defines a standard clock correction value. Further, a source-native accumulator 306 can accumulate a sum comprised of the scaled source-native clock corrections and the standard remainder produced from the source-native divider. The sum can define the adjusted source-native clock correction value.

Abstract: A method and apparatus are disclosed for detecting a presence of a device. Specifically, a method and a system are disclosed that may comprise providing a clock driver having a pair of differential clock signal lines capable of connection to a device, providing a presence detection signal for transmission through the pair of differential clock signal lines, determining whether the presence detection signal is received through the pair of differential clock signal lines, identifying the absence of the device if no presence detection signal is received through the pair of differential clock signal lines, identifying the presence of the device if the presence detection signal is received through the pair of differential clock signal lines, and notifying a system management module of the presence of the device.

Abstract: Systems and methods for driving data over a data bus are disclosed. One embodiment of a system may comprise a bus clock signal that is a copy of a system clock signal that controls the timing associated with transferring data over the bus, a data clock signal that is designed to lead the system clock by a portion of a clock cycle to drive data over the bus ahead of the bus clock signal, an output latch device that drives data over the data bus in response to an edge of the data clock signal and a skew corrector that mitigates racing of data over the data bus in the event that the data clock lags the bus clock.

Abstract: Disclosed is a method for minimizing the buffer size of an elasticity FIFO queue when synchronizing data between two clock domains. Data communication is typically sent by a transmitter device to a receiver device. The transmitted data signal includes an embedded clock signal and null data characters, as specified by the data communication signal protocol. A null character indicates an empty data frame and is included as part of most standard communication protocols. An embodiment skips one or more null characters from the elasticity FIFO queue during a single clock cycle when it is detected that the write pointer is catching up to the read pointer. By skipping multiple null characters during a single write cycle, the read pointer is moved ahead by one or more queue locations and the write pointer is insured to not catch up to the read pointer for a wider variation in frequencies between a transmitter and receiver than is normally possible.

Abstract: A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and a transmitter coupled to the downstream data bus. Similarly, each of the memory modules includes a receiver coupled to the downstream data bus and a transmitter coupled to the upstream data bus. Each receiver includes a receive clock generator that is synchronized by coupling a known pattern of data to the receiver. The receiver determines which phase of the receive clock best captures the known pattern and uses that receive clock phase during normal operation.

Abstract: A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group is delayed by less than a bit time to align the eyes with the nearest clock edge of a received clock signal. In addition to aligning the eyes of the individual data bits with the nearest clock edge, IAP patterns are used to determine the amount of further delay needed to line up the individual data beats from each data bit. If the data beats for the data bits are not aligned, all but the slowest data beat are delayed to align the data beats for all bits. The additional delay is achieved using sample latches that result in a delayed signal with less jitter. As a result of having less jitter, the received, de-skewed, and aligned clock/data group can be forwarded to the operative portion of the receiving chip at an increased frequency.

Abstract: A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value.

Abstract: A system, method and computer program product for calibrating a Time Of Day (TOD)-clock in a computing system node provided in a multi-node network. The network comprises an infrastructure of computing devices each having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The system implements steps for obtaining samples of timing values of a computing device in the network, the values including a physical clock value maintained at that device and a TOD-offset value; computing an oscillator skew value from the samples; setting a fine steering rate value as equal to the opposite of the computed oscillator skew value; and, utilizing the fine steering rate value to adjust the physical clock value and correct for potential oscillator skew errors occurring in the oscillator crystal at the computing device.

Abstract: A method for transferring variable isochronous data and an apparatus therefor are provided. The method for transferring variable isochronous data includes the steps of (a) determining isochronous transfer to be terminated when the bus is in an idle state for a time interval which is larger than an isochronous gap period, (b) detecting a residual gap having a time interval which is larger than the time interval of an isochronous gap and smaller than the time interval of a subaction gap, (c) checking whether bandwidth for the transfer of isochronous data remains when the residual gap is detected in the step (b), and (d) transferring the isochronous data when it is determined that the bandwidth remains in the step (c).

Abstract: The capacity of a single high-speed serial link between programmable logic devices or other integrated circuits may be provided using multiple lower-speed serial links arranged in parallel. Circuitry is provided for synchronizing and deskewing serial data streams from the multiple lower-speed serial links. At a receiving integrated circuit, a first-in-first-out buffer may be associated with each of the lower-speed serial links. Each first-in-first-out buffer may be used to provide both synchronization functions and channel alignment functions.

Abstract: Provided are a method, system, and device to effectuate a transfer of data from one clock domain to another. In accordance with one aspect of the description provided herein, bits of data to be transferred are shifted in the first clock domain. The shifted bits of data to be transferred may be sampled in a second clock domain at a fixed time within each clock signal of the first clock domain. A stream of sampled bits may be output in the second clock domain. Additional embodiments are described and claimed.

Abstract: The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an accompanying clock signal HA. This accompanying clock signal transmitted by the transmitter equipment A is used by the receiver equipment B to sample the transmitted data. An alternation is effected at the receiver equipment B between a phase of operation during which the clock signal HA accompanying the data is replaced by a local clock signal HLS of the same frequency and a phase of operation during which the local clock signal is periodically re-synchronized with the accompanying clock signal. Means to implement the method are also disclosed.

Abstract: When receiving request commands from different hosts, a data system generates corresponding phase control signals and access signals based on the formats of each request command. Based on the phase control signals, timing signals corresponding to respect request commands and including a plurality of enabling time slots are generated in a way that only one timing signal includes an enabling time slot at a certain point of time. Next, an access control signal is outputted to a storage device during the enabling time slot of a corresponding timing signal. Therefore, the storage device only needs to respond to one request command at a certain point of time, and multiple data access can be effectively controlled in the data system.

Abstract: The skew adjusting circuit for parallel signals includes: a deskew signal generating circuit which generates a deskew signal by performing a predetermined logical operation and transmits the deskew signal to a receiving circuit; a skew detecting circuit which detects the skew by obtaining correlation between the deskew signal and the data signal and then obtaining an average value of the correlation; and a delay amount adjusting circuit which adjusts the skew by controlling the amount of delay of the data signal in accordance with the average value obtained by the skew detecting circuit. As a result, it is possible to reduce power consumption and circuit size, while suppressing the number of logic processing circuits to be added for skew adjustment, when parallel signals are transmitted in circuits which needs high-speed characteristic.

Abstract: A method for optimizing signal operating parameters for a signal sent over a data transmission channel through a programmable logic device (PLD) is provided. A transmit test pattern is generated and is associated with a set of signal operating parameters for the transmission and receiving of the test pattern over a data transmission channel. The data transmission channel loops from a transmit port to a receive port of the PLD. A determination of whether the received test pattern matches the transmit test pattern is performed. The match results and the set of signal operating parameters are recorded. At least one of the signal operating parameters of the set of signal operating parameters is modified through a processor of the PLD. Another transmit pattern is transmitted and received according to the modified set of signal operating parameters and the results are recorded. Methods for optimizing data transfer into a PLD and corresponding apparatuses are included.

Abstract: A controller arrangement and method for effectuating data transfer between a first clock domain and a second clock domain. In one embodiment, inversion circuitry inverts a first clock signal associated with the first clock domain into an inverted first clock signal that is used in effectuating a SYNC pulse during coincident edges of the inverted first clock signal and a second clock signal associated with the second clock domain. Clock synchronizer controller circuitry operates responsive to sampled sync pulses based on the SYNC pulse to generate domain synchronizer control signals for effectuating data transfer between the first and second clock domains.

Abstract: A state machine circuit may be used to control a multiplexing circuit that selects and provides respective ones of multiple input clock signals to a clock-synthesizing circuit that generates a synthesized clock signal in response to such input clock signals. The state machine circuit may, for example, be configured so that the synthesized clock signal is a spread-spectrum clock signal and/or a clock signal having a nominal frequency that is greater than a nominal frequency of each of the input clock signals.

Abstract: Exemplary schemes for multi-frequency at-speed logic Built-In Self Test (BIST) are provided. For example, certain schemes allow at-speed testing of very high frequency integrated circuits controlled by a clock signal generated externally or on-chip. Some of the disclosed schemes are also applicable to testing of circuits with multiple clock domains which can be either the same frequency or different frequency. In particular embodiments, the loading and unloading of scan chains is separated from the at-speed testing of the logic between the respective domains and may be done at a faster or slower frequency than the at-speed testing. In certain embodiments, only the capture cycle is performed at the corresponding system timing. In some embodiments, a programmable capture window makes it possible to test every intra- and inter-domain at-speed without the negative impact of clock skew between clock domains.

Abstract: A sample rate converter (SRC) is used to slave hardware devices to a master hardware device. A clock manager registers the time at each clock of each device, communicates with memory that stores the clock times, and reports correlations between each clock time and the time at a reference clock. The processing of a data stream can be slaved to one or more hardware devices. The processing of a wake up period can be slaved to the clock of the master hardware device by adjusting the wakeup period. Slaving of hardware devices to the master hardware device can also be accomplished by finding a correlation between the clock times in memory and the reference clock. Each correlation can be input into an SRC corresponding to each slave hardware device. Each SRC can then generate or consume a data stream at the actual rate of the corresponding slave hardware device.

Abstract: A clock selector for selecting a set of candidate clock signals from among a plurality of input clock signals. The phase selector includes control logic adapted to generate a plurality of control signals and a plurality of muxes controlled by the control signals and arranged in two or more stages having at least a first stage and a last stage. The input to the first stage is the plurality of input clock signals. At least one stage is adapted to (i) receive a plurality of clock signals, (ii) drop at least the first or the last clock signal of the received plurality of clock signals, and (iii) output a reduced plurality of clock signals. The output of the last stage is the set of candidate clock signals.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: A method of transmitting encoded computer display images between computers over a nondeterministic network is disclosed. During a display session in which images are transmitted from a host to a client, the client requests sections of encoded image updates at a predetermined time in advance of when the requested at least one section is to be transmitted by the display controller. When the requested section is received, a time value is compared to a display controller timing value and, if the difference between the compared times is outside of an acceptable range, the client adjusts a predetermined time at which time the client requests image sections from the host.

Abstract: A data transfer circuit includes a first transfer circuit receiving the first transfer signal, a second transfer circuit receiving the second transfer signal, a third transfer circuit receiving the first transfer signal and an inverted first transfer signal from the first transfer circuit and transferring the first transfer signal in response to a reply signal, a fourth transfer circuit receiving the second transfer signal and an inverted second transfer signal from the second transfer circuit and transferring the second transfer signal in response to the reply signal.

Abstract: The present invention is directed to a duty cycle correction apparatus that can be implemented in a small size, and is capable of performing a phase lock more rapidly, and reducing the amount of current being consumed, and to a method thereof. The duty cycle correction apparatus in accordance with the present invention for use in a semiconductor memory device includes a delay line unit for delaying a first clock signal to produce a first delayed clock signal; an output tap unit for delaying the first delayed clock signal by a pulse width of a first logic state of the first clock signal under the control of a toss control signal derived from a second clock signal; and a phase mixer for mixing the clock signal from the output tap unit and one of the first and second clock signals.

Abstract: A system and method for digital communication wherein a host provides a host clock and a clockless device transmits to the host a bit stream synchronized according to the clock at a data rate that is an integer multiple of the clock rate. A training mechanism using training data detects time skew between host clock and bit stream, and a digital skew compensation mechanism compensates, substantially in real time, for the skew and for variations in the skew that may occur with the passage of time, in accordance with a vote among at least three samples of a bit of the bit stream, subsequent sampling being retarded or advanced if, respectively, an early or late sample is in disagreement with the vote. Preferably, the compensation value is selected from at least four possible compensation values, and can be stored in a memory to hasten subsequent restarts of the system.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit.

Abstract: An adjusting circuit for adjusting timings of memory signals of a computer system is provided. The adjusting circuit includes: a clock generator for generating a plurality of reference signals, all having the same frequency but different phase; a multiplexing unit connected to the clock generator for receiving the reference signals, wherein the multiplexing unit selects a first reference signal according to a selecting signal; and an adjusting unit connected to the multiplexing unit for receiving a signal and delaying to output the signal according to the first reference signal selected by the multiplexing unit.

Abstract: A system and method for improved synchronous access of stored data are provided herein. A data requestor transmits a clock signal and a read request signal for reception by a data source, whereupon skewed versions of the clock signal and the read request signal are received due to the delays in the signal paths between the data requestor and the data source. Accordingly, the data requestor provides skewed clock and read request signals to its input sampling module to simulate the delays of the signal paths. Additionally, the data requestor provides process information associated with the requested data to a dual clock first in-first out (FIFO) buffer. When the input sampling module detects a read request using the skewed read request signal, the input sampling module can use this signal and the skewed clock signal to sample a data signal from the data source to obtain the requested data.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: Phase frequency detectors with limited output pulse width and related methods are disclosed. The proposed phase frequency detector generates a first output signal and a second output signal corresponding to phase difference or frequency difference between a first signal and a second signal. When the phase difference between the first and second signals is greater than a predetermined delay, the pulse width of the first output signal is limited, so that the proposed phase frequency detector has a limited equivalent output pulse width.

Abstract: A method for determining if a measurement of an elapsed time for an execution of a software routine in a computer system is valid. A clock skew is used between the clocks of two processors such that the size of the clock skew is greater than the maximum possible elapsed time for the execution of the software routine. The software routine is executed with a clock value recorded before (start time) and after (end time) execution. An elapsed time is calculated as a difference between the start time and the end time. Whether the elapsed time is valid is determined by checking for a positive value of the elapsed time and comparing the value of the elapsed time with the clock skew.

Abstract: Systems and methods for deskewing parallel data lines using at least one extra channel in parallel to the parallel data lines to carry data for comparing to data on the parallel data lines.

Abstract: According to embodiments of the present invention, a phase-locked loop (PLL) may include circuitry to select a wide pulse width for the phase-frequency detector control signal when the PLL is in a frequency acquisition stage, a narrow pulse width for the phase-frequency detector control signal when the PLL is in a phase capture stage, and a wide pulse width of the phase-frequency detector control signal when the PLL is in a lock stage.

Abstract: De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.

Abstract: A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. A first circuit of the memory controller receives the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, and a second circuit of the memory controller receives the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal. The first timing offset is independent of the second timing offset.