Abstract: A data processing system, method, and computer program product for automatically tracking insertions of integrated circuit devices into receptacle devices. An insertion of an integrated circuit device is automatically detected utilizing the data processing system. An insertion count that is associated with the integrated circuit device is automatically incremented in response to a detection of an insertion of the integrated circuit device. The insertion count is used to track insertions of the integrated circuit device.

Abstract: The present invention is related to “trace” and debugging capability in the operation of the Java programming utility. It represents a means to execute a program in such a way that the sequence of statements being executed can be observed. It is related to “debugger”, which is a program designed to aid in debugging another program by allowing the programmer to step through the program, examine the data and monitor conditions, such as the values of the variables, and correct the problem.

Abstract: A data regenerator for regenerating a data signal, including a convertor for converting a received data signal into a binary data signal in dependence on conversion parameters, an error corrector for correcting errors in the binary data signal based on error correction code contained in the binary data signal to produce a corrected binary data signal, and a performance monitor for comparing the corrected binary data signal with an uncorrected representation of the binary data signal to determine information about the relative number of logic“1”s and logic “0”s that have been corrected by the error corrector and output a feedback signal representative of the relative number, wherein the convertor adjusts at least some of the conversion parameters in dependance on the feedback signal.

Abstract: A bridge fault modeling and simulation apparatus including a neural network simulates the effects of bridge defects in complementary metal oxide semiconductor integrated circuits. The apparatus includes a multilayer feedforward neural network (MLFN), implemented within the framework of a very high speed integrated circuit hardware description language (VHDL) saboteur. The saboteur is placed between logic cells in the IC simulation. The apparatus computes exact bridged node voltages and propagation delay times with due attention to surrounding circuit elements. It results in faster simulation and achieves excellent accuracy.

Abstract: For the purpose of providing a method for producing data media, and for providing such data media, by means of which both the need for reinstallation and the time required for restoring a given content to its pre-incompatibility state are minimized, this invention proposes a method for producing such a data medium with a restorable original base data content, whereby, in a section of the data medium designated as the active-data zone, an original base data content is generated, a separate section of the data medium is designated as the recovery zone, and a retrievable backup copy is saved from the active-data zone into the recovery zone.

Abstract: A source code is entirely described in a high-level language. The source code includes a library description and a versatile description other than the library description to correspond to a target processor-adapted assembler code. The library description is made up of functions defined in high-level language. In order to produce target processor-adapted software, a dedicated translator transforms the library description into, one by one, an assembler code, while a compiler compiles the versatile description. A simulator includes a compiler that is operable to compile the library description with reference to a library.

Abstract: A method and apparatus for monitoring the response times of computer system components in order to improve computer system reliability and performance are provided. The method and apparatus are particularly applicable to computer systems with memory circuits, such as SLDRAMs, that have programmable response times. A response time monitoring circuit in the form of a phase detector includes a plurality of flip-flops with the data inputs commonly connected to receive a response ready signal from a component, such as a memory circuit, in response to a command to perform a task. Each clock input of the flip-flop is connected to a clock signal at a different phase of a response period. The outputs of the flip-flops determine the phase at which the response ready signal was generated by the component.

Abstract: A computer-implemented method and system for reporting failures in an application program module to a corporate file server. The failure may be a crash or a set-up failure. Once detected, the program failures are categorized, i.e. bucketed, and reported directly to a local file server operated by a corporation. The corporate file server may be used to store the failures encountered by users in a corporate environment until these failures are reported to a server operated by the manufacturer of the program module (a destination server). Once the failures are reported to the destination server, developers or programmers may examine the data and determine what is causing the failures in the program module. A failure reporting executable on the user's computer provides communications between the failed application program module and the local file server.

Abstract: A method and apparatus for reference data scrubbing is provided.

Abstract: A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a destination register for retrieving the information. A first number of cycles before retrieval of the information to the destination register then is determined, and the information is transferred from the source register to delaying device, such as queuing device, for the first number of cycles. Finally, the information is written from the delaying device to the destination register. An apparatus for implementing variable length delay instructions includes an input line for reading information from a source register; delaying device for receiving said information read from the source register; a multiplexer; and a select line. A trigger signal is transmitted to the multiplexer, thereby instructing the multiplexer to write the information to a destination register.

Abstract: The present invention provides for detection apparatus with functionalized fluorescent nanocrystal compositions and methods for making and using these compositions in biological detection applications, material separations, and in the production of biosensors. The compositions are fluorescent nanocrystals coated with at least one coating material comprising ligands with functional groups or moieties with conjugated electrons and moieties for imparting solubility to fluorescent nanocrystals in aqueous solutions. The coating material provides for functionalized fluorescent nanocrystal compositions which are water soluble, chemically stable, and emit light with a high quantum yield and/or luminescence efficiency when excited with light. The coating material may also have chemical compounds or ligands with moieties for bonding to target molecules and cells as well as moieties for cross-linking the coating.

Abstract: A system and method for data transmission incorporating a hybrid automatic repeat request (ARQ) function at each node in an ad-hoc network. Each node is configured to calculate an optimum segment size for transmission and thereafter executes the ARQ function to transmit and receive data segments with forward error correction and error detection coding. The coding allows the node to detect and locate errors within received segments and to provide an acknowledgement only after all segments are correctly received. A negative acknowledgement from the receiving node states the location of failed segments, and only failed segments are then retransmitted. The failed segments can be retransmitted in their original location and in other segment locations which contained segments that did not fail, thus reducing maximum time to successfully deliver the segments.

Abstract: A system and method for testing and maintaining a predetermined bit rate on a line connection between a transmission assembly and at least one terminal, where initiation of a drop below the predetermined bit rate triggers at least one corrective measure for increasing the bit rate.

Abstract: A data storage system adapted to maintain redundant data storage sets at a destination location(s) is disclosed. The data storage system establishes a copy set comprising a source volume and a destination volume. Data written to a source volume is automatically copied to the destination volume. The data storage system maintains a data log that may be activated when the destination volume is inaccessible due to, for example, a malfunction in the destination storage system or in the communication link between the source system and the destination system. I/O commands and the data associated with those commands are written to the data log, and after a destination system becomes available the information in the data log is merged into the destination volume to conform the data in the destination volume to the data in the source volume. The data log competes for disk capacity with other volumes on the system, and log memory is allocated as needed.

Abstract: The present invention provides a method, system and program product for dynamically detecting an errant data sequence transmitted over a network and performing a corresponding action. Specifically, a data sequence is received by a server from a client and compared to a definable data structure. The data structure comprises rules that each correspond to a state of communication between the server and the client. Each rule sets forth a predetermined data sequence, an optional condition and an action. If the received data sequence: (1) matches one of the predetermined data sequences in the data structure; (2) is relevant to (was received during) the state of communication to which the matched predetermined data sequence corresponds; and (3) meets any enumerated conditions, a corresponding action is implemented.

Abstract: A system for computer-based testing includes a test driver that has an executable code that controls the test driver to deliver a test to an examinee, a resource file that stores information relating to data content, presentation format, progression, scoring, printing, timing, and/or results reporting of the test, which is accessible to the test driver to enable the test driver to retrieve the test specification and content and to deliver the test to the examinee, and an expansion module that retrieves the information relating to the data content, the presentation format, the progression, the scoring, printing, timing, and/or the results reporting of the test from the resource file and provides the information to the test driver during delivery of the test, expanding the functionality of the test driver without necessitating modification to the executable code of the test driver.

Abstract: An application specific integrated circuit includes a multiplicity of operational blocks each of which includes at least one respective data bus and at least one respective visibility bus and a respective addressable multiplexer for selecting between those buses to provide an output on a to respective block bus. An interface block includes a first addressable multiplexer for selecting output data from a selected one of the blocks and providing an output; a register coupled to the output of the first addressable multiplexer; and a second addressable multiplexer for selecting between data provided by the output of the first addressable multiplexer and data in the register. Different portions of externally supplied address words are applied to the first addressable multiplexer and the respective addressable multiplexer, and a decoder is responsive to the address words for controlling the second addressable multiplexer. The arrangement provides a common multiplexing system for data buses and visibility buses.

Abstract: A data transmission and distribution system that includes a series of payloads, where each of the payloads is formed from bits of audio or video information, and where different levels of protection are applied to different sets of bits in each payload. The system divides the bits associated with each payload into high priority bits and low priority bits and forms a group of check bits for each payload by applying an error correction algorithm to the high priority bits in the payload. The system also forms each payload from a first set of the high priority bits, the check bits, the low priority bits and a redundant set of the high priority bits and the check bits and transmits the payloads formed from the first set of the high priority bits, the check bits, the low priority bits and the redundant set of the high priority bits and the check bits.

Abstract: A data structure contains sequence number metadata which identifies an input/output (I/O) operation such as a full stripe write on a redundant array of independent disks (RAID) mass storage system, and also contains revision number metadata which identifies a subsequent I/O operation such as a read modify write on only a fractional component of the entire user data. The sequence number and revision number metadata are used in an error detection and correction technique, along with parity metadata, to detect and correct silent errors arising from inadvertent data path and drive data corruption. An error to a portion of the stripe is detected by a difference in sequence numbers for all of the components of data. An error arising after an I/O operation is detected by a revision number which is different from the correct revision number.

Abstract: A circuit board, for use with a high speed backplane, includes transmitter and receiver with circuitry for correcting for multipath signal errors. A training sequence that is often a pseudo-random signal is transmitted by the transmitter on a first circuit board to a receiver located on a second circuit board. The receiver on the second circuit board includes an analog-to-digital signal converter, an equalizer, and a binary digital-to-analog reconverter for receiving the training sequence. The equalizer preferably comprises a series of connected registers having taps in between, a plurality of individual weighting means attached to each of the taps, and a summing means connected to the weighting means. A training sequence is transmitted from the first circuit board to the receiver on the second circuit board, enabling the receiver to adaptively determine a set of weighting means coefficients for correcting the multipath errors in subsequent signals.

Abstract: A system and method for system monitoring. The system monitors parameters and when parameters cross thresholds, the system transmits an event message to the service provider and determines if an alarm should be generated. During system operation, data is collected periodically and new monitoring data is compared with recently stored monitoring data to identify events and alarms. The service provider transmits monitoring interfaces to the customer including current status concurrently with indicators of prior operating states, such as uncleared alarm indicators. The monitoring interfaces selectively show operating status for the monitored environment, domains, systems, or individual monitored components. For each monitored element, a multi-tier arrangement divides the operating status into three operating ranges, such as normal, non-critical, and critical, with current status displayed on the monitoring interfaces on a domain, system, element, or component basis.

Abstract: In one aspect of the invention, a method for testing includes interposing a tester between first and second logic. The first logic and second logic have respective first and second output drivers. The tester operates in test cycles to detect dynamic contention responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during an immediately succeeding one of the test cycles. Static contention is detected responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during the same one of the test cycles.

Abstract: A testing unit is provided with a test data communication port adapted to output test data to a device being tested. The testing unit also has an expected test result data communication port adapted to output expected test result data to the device. The device being tested generates test result data in response to the test data, and compares the test result data with the expected test result data to generate test status data, such as a pass or fail indication.

Abstract: Systems and techniques to test a software product in one or more computer systems. In general, in one implementation, the technique includes calling components in a first computer system during execution of a test, recording the calls, and rerunning the recorded calls in a second computer system in order to recreate the behavior of the first computer system during execution of the test.

Abstract: A system and method is provided for uniquely handling exception an interrupts in at least two different processors in a multiprocessor system. Initially, the memory address identified in a common exception vector table is written to contain an instruction which copies the current version of an IRQ-mode banked register into the program counter of the processor for subsequent execution. Next, each processor initializes independent IRQ-mode registers to contain the respective addresses for their individual IRQ handler routines. Upon receipt of an interrupt request or other exception, the processor receiving the request changes to an IRQ-mode, resulting in at least one register change from a normal register to the previously initialized IRQ-mode register. Next, the processor looks in the exception vector table for the appropriate interrupt handler address location and jumps to the identified memory location.

Abstract: A method for processing first data representing parameters relating to several components of an electrical circuit provides an associated first data record for each component. The components of the circuit are checked against specific parameters. The parameters relate to the connection of the components to networks, or to electrical/geometric characteristics of the components. The check of the “basic rules” results in the formation of binary values. The binary values are then logically linked to check an “overall rule”. One such overall rule is, for example, the rule for checking the circuit for adequate electrostatic discharge (ESD) protection. A computer readable storage medium and a data processing system, each containing computer-executable instructions for performing the method, are provided.

Abstract: The maximum performance state available to a processor in a computer system, in terms of operating frequency and/or voltage, changes according to thermal criteria. When the temperature increases above a predetermined threshold, the maximum performance state available is reduced. Multiple temperature thresholds may be utilized providing for a gradually reduced maximum performance state as temperature increases. When the temperature returns to a lower level, the maximum performance state available is increased. Changing the maximum available performance state according to temperature provides for more gradual reduction in performance as temperature increases, which results in higher average system performance as temperature increases. Thus, a more gradual reduction in performance is provided while still maintaining a high speed rating of the processor in more ideal conditions.

Abstract: A circular VTOL aircraft with a central vertically mounted turboprop engine 14, driving contra-rotating co-axial propellers 24, above a central jet engine (or engines) 12, horizontally mounted on a turntable pod 11 which is steerable through 360 degrees. The turboprop provides vertical thrust from contra-rotating propellers compressing air from an upper circular intake 5 downward through a circular shaped rotor-chamber 6 to a circular vent 10 at the base of the craft. The resulting column of compressed air supports the craft during take-off and landing operations and provides a cushion of air in normal flight. The horizontally mounted jet turbine provides main thrust for horizontal flight and vectored thrust for VTOL. The passenger cabin 21 is circular and is situated in the main body of the disc-shaped craft. Fuel tanks are situated around the circumference of the craft to maximise fuel capacity. The flight-deck 2 is situated at the top centre of the craft, above the engine unit 15, which is detachable.

Abstract: Provided herein are compositions of functionalized, fluorescent nanocrystals comprising fluorescent nanocrystals coated with an imidazole-containing compound; compositions of functionalized, fluorescent nanocrystals comprising fluorescent nanocrystals coated with an imidazole-containing compound and cross-linked with a phosphine cross-linking compound; compositions of functionalized fluorescent nanocrystals operably bound to molecular probe; a process of making functionalized, fluorescent nanocrystals; and a process of using functionalized, fluorescent nanocrystals in a detection system.

Abstract: The invention includes a system and method for tracking errors, the system residing on a user's desktop communicating with a central database over a network. The system comprises an error log including error recording tools for enabling the user to record an error; error resolution tools for enabling the user to resolve the error; and error follow-up tools for enabling a user to follow up on resolved errors; error reporting tools for enabling a user to generate error reports from the user's desktop; and communication tools for enabling the user to transmit logged errors to the central database and to receive reports generate from errors logged in the central database.

Abstract: A method for retrieving information related to a desired item from a database storing information which are collected from a system to be monitored is disclosed. A plurality of states of the system are displayed in time sequence on screen of a display. Each of the states is represented by a plurality of items of collected information. When inputting a desired item of a state selected from the states displayed on the screen, a state of the system is retrieved from the database based on the desired item, and the retrieved state is displayed on the screen.

Abstract: A method of centralised data position information and storage and utilisation comprising the steps of arranging a byte stream of data into partitioned logical data, storing data position information relating to the logical data in a reserve storage area, transferring the information from the reserve storage area to a centralised storage area configured to store information relating to substantially all the partitioned logical data and utilising the information to locate a target data using a search algorithm.

Abstract: A trouble report processing system provides an electronic interface between a telephone company's trouble report input system and its trouble report resolution system. The interface eliminates the need for the trouble report input system to generate a paper ticket that must be carried to a trouble report resolution system. An operator receives a call and generates a trouble report which is stored in the trouble report input system as an electronic trouble ticket. The interface continually, periodically or as desired, monitors the trouble report input system for the presence of new electronic trouble tickets. When the interface finds a new electronic trouble ticket, it acquires the information contained therein and uses it to build a trouble ticket in a format that the trouble ticket resolution system can process.

Abstract: A method and apparatus are disclosed for detecting a fault in a transceiver of a base transceiver system. In the transceiver having a down converter, a microprocessor reads a predetermined first minimum value and a predetermined first maximum value of received input signal levels, measures an instantaneous control voltage generated from an automatic gain controller (AGC) and converts the measured instantaneous AGC control voltage into a received input signal level. When the converted received input signal level is below the predetermined first minimum value, the microprocessor determines that a fault exists in the amplifier operation of the down converter. Similarly, when the received input signal level exceeds the predetermined first maximum value, the microprocessor determines that a fault exists in the amplifier operation of the down converter.

Abstract: A Fault-tolerant Operational Environment system, and method, which makes it possible for network operators and third parties (for example, software houses) to implement their service ideas directly and without passing via the network suppliers, and at the same time to ensure that faulty Service Applications implemented in such a way have no negative effects. By an operational environment system (FOE) according to the invention.

Abstract: A TCP-connection-router performs encapsulated clustering by dividing each encapsulated cluster into several Virtual EC (VECs), dynamically distributing incoming connections within a VEC based on current server load metrics according to a configurable policy. In one embodiment, the connection router supports dynamic configuration of the cluster, and enables transparent recovery which provides uninterrupted service to the VEC clients.

Abstract: A method and apparatus are provided for performing an array DML operation. During the performance of the operation on a data item in the array, and if an error occurs, then error information is stored and the array operation continues by performing the operation on the next data item in the array. The error is used to create update input data for the DML operation, and the update input data can be supplied during run-time of the program.

Abstract: An improved system for processing at least partially structured data includes a method for comparing a population of terms in a term repository, including standardizing each term within the population of terms based on at least one standardization rule. The method also includes comparing at least a pair of terms including determining a match between the terms if, once standardized, they are substantially identical.

Abstract: A method and apparatus for automotive testing comprises a base station and at least two handsets adapted to provide a testing function in at least two corresponding technically distinct areas. Embodiments employ Kelvin connectors and/or Hall effect probes and/or induction probes. System operation is effected by the simplest and minimum number of control commands.

Abstract: The quality of service in a digital television link is monitored cyclically by means of an analyzer which analyzes the transport stream packets to deduce therefrom many standardized analysis parameters which are complex to interpret. The invention minimizes the number of measurements of these parameters by preselecting first and second analysis parameters and periodically determining a first maximum for variations from the first selected parameters and a second maximum for variations from the second parameters selected to deduce therefrom, respectively, a first parameter which is representative of the synchronization relative to the equipment units in the link and at least one second parameter which is representative of a degradation in a link.

Abstract: A computer-implemented method in which report program language is converted to object-oriented source code, such as Java, using the report program language compiler. The object-oriented source code emulates the behaviour of the report program language, such as VARPG. Applications written in RPG are converted to Java and therefore can run on every platform for which a Java virtual machine exists. RPG programmers now have the ability to write internet applications. Java applications and applets can be written in RPG and existing RPG applications can be converted to Java applets.

Abstract: The present invention provides for a system and method for improvement of radio transmitter and receiver frequency accuracy for a local radio communication unit that communicates digital data with a remote communication unit. In the local unit the received radio signal is down-converted, and converted to complex baseband digital samples by an analog-to-digital converter. A downlink digital phase rotator applies a fine frequency shift to the samples in accordance with a receiver frequency offset command. The resultant baseband signal is used by the data demodulator and by a receiver frequency error estimator to obtain receiver frequency errors. A data modulator generates baseband complex samples which are shifted in carrier frequency by an integrated uplink digital phase rotator in accordance with a transmitter frequency offset command. The modulated samples are then converted by a digital-to-analog converter and upconverted in frequency for radio transmission to the remote unit.

Abstract: A method, apparatus, and article of manufacture for resolving long-busy conditions for synchronized data sets. A long-busy condition is detected in a first one of the synchronized data sets. Further access to the first data set is prevented and all subsequent accesses are directed to another, available, second one of the data sets during the long-busy condition. All updates that are made to the second data set during the long-busy condition are identified and stored in a data structure. An untimed read operation is used to determine when the long-busy condition has cleared. Once the long-busy condition is cleared, the first data set is placed into a recovery mode, wherein the identified updates are applied to the first data set. During the recovery mode, the first data set is read-inhibited to prevent read accesses thereto, but the first data set is write-enabled to allow write access thereto.

Abstract: A method and apparatus are used in accordance with the present invention in concurrent program analysis for detecting potential race conditions such as data races in computer programs. A feature of the method and apparatus of the present invention is verifying annotations of addressable resources in a program. The present invention verifies annotations by checking if thread-local resources are indeed thread-local, and that thread-shared data spaces are not in fact thread-local. In accordance with the purpose of the invention, the method provides for detecting potential race conditions, such as data races, in a computer program. The computer program can spawn a plurality of threads that are capable of being executed concurrently. The method includes receiving a source code of the computer program. The source code includes an element annotated as either thread-local or thread-shared.

Abstract: A parallel-to-serial-to-parallel circuit are disclosed, the circuit interfacing with a data bus, preferably with a processor for byte alignment and other operations. The parallel-to-serial-to-parallel circuit includes an input bit shift register having a predetermined number of register positions and an output bit shift register with the same number of register positions. The output of the input bit shift register is fed into the output bit shift register through a multiplexer. The input bit shift register may receive a bit write from a bit bus, a partial parallel write from a data bus with corresponding data validity data received on a shadow bus, and full parallel write from the data bus. The output bit shift register may transmit a bit read to the bit bus or a full parallel read to the data bus. Data received is shifted to the output bit shift register and compiled into full parallel data or read out as single bits. Offset bits may be introduced in the data stream for data alignment.

Abstract: In a management network, active alarms are received by management devices, acting as agent or as superior manager, each of which can be stored on any of the management devices and can be handled for a specific period of time by operators. The management devices can have different management levels. Operators are coupled to the management devices to handle active alarms for a specific period of time. A checking function is introduced having one or more checking attributes for reciprocal information about alarm handling between the management devices. The checking function having the checking attributes results in automatic coordination between the management devices situated in a manager-agent relationship on different management levels during alarm handling.

Abstract: There is provided a semiconductor integrated circuit device for realizing in the higher accuracy the verification of a plurality of operations of a clock generation circuit to form an internal clock signal and enabling verification for various performances of the internal clock signal generation circuit while simplifying the structure thereof. In such semiconductor integrated circuit device, a measuring circuit for conducting at least two kinds of measurements among the measurements of lock time until the predetermined internal clock signal corresponding to the input clock signal can be obtained, the maximum frequency of the internal clock signal and jitter of the internal clock signal is provided to the clock generation circuit to form the internal clock signal corresponding to the input clock signal inputted from an external terminal. Thereby, operations of the clock generation circuit can be verified with higher accuracy within the semiconductor integrated circuit device.

Abstract: A method, apparatus, and article of manufacture, and a memory structure for accepting data input into a computer is disclosed. The method comprises the steps of presenting a component to the user, wherein the component includes an input area for accepting the input data, and the component is subject to a constraint for the data, accepting user input into the component input area, and following an assistance policy associated with the component when the user input violates the value constraint. In one embodiment, the value constraint for the input data is organized according to the component content type. In another embodiment, the method comprises the steps of defining a component comprising an input area for accepting input data, associating the component with a value constraint according to a content type of the input area, and associating the component with an assistance policy selected from a set of assistance policies.

Abstract: A data storage facility provides a remote copy operation that copies data write updates from a primary data store to a remote site by identifying which bytes in a block update have changed and sending only the changed bytes from the primary data store to the remote site. An exclusive-OR (XOR) logic operation is used to identify the changed bytes by XOR'ing the original data block with the changed block. Data compression can then be used on the XOR data block to delete the unchanged bytes, and when the compressed block is sent to the remote site, only the unchanged bytes will be sent, thereby reducing the bandwidth needed between the primary store and the remote site.

Abstract: Reliably detecting malfunction of an abnormality-monitoring circuit during operation of a processing unit. An electronic control unit provided with a CPU level-inverts and outputs an actuating signal during each iteration of a base routine. An abnormality-monitoring circuit clocks a fall interval of the actuating signal as charging voltage of a gradually discharged capacitor, and outputs a reset signal to the CPU when this charging voltage falls to a defined value. When a check-starting condition is fulfilled, the CPU inhibits a subsequent level inversion of the actuating signal until a predetermined time elapses after a prior level inversion. When the signal inhibition is canceled, when the charging voltage VC of the capacitor is not within a reference range (VL-VH), the CPU determines the abnormality-monitoring circuit to have malfunctioned.